(12) United States Patent (10) Patent No.: US 6,351,011 B1. Whitney et al. (45) Date of Patent: *Feb. 26, 2002

Transcription

1 USOO B1 (12) United States Patent (10) Patent No.: US 6,351,011 B1 Whitney et al. (45) Date of Patent: *Feb. 26, 2002 (54) PROTECTION OF AN INTEGRATED 4992,333 A 2/1991 Hyatt CIRCUIT WITH VOLTAGE WARIABLE 5,142,263 A 8/1992 Childers et al. MATERALS 5,189,387 A 2/1993 Childers et al. 5, A 11/1993 Childers (75) Inventors: Stephen J. Whitney, Lake Zurich; 5:3. A 3.E. Marinez et al. Edwin James Harris, IV, Des Plaines; A 9 ya AA 2Y /1997 Jeffrey S. Niew, Burr Ridge; Michael 5,781,395 A 7/1998 Hyatt J. Weber, Wheeling, all of IL (US) 5,869,869 A 2/1999 Hively 5,955,762. 9/1999 Hively (73) Assignee: Littlefuse, Inc., Desplaines, IL (US) 5,970,321. A 10/1999 Hively 6.211,554 B1 * 4/2001 Whitney (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 4(b) by 0 days. WO WO 99/ /1999 This patent is Subject to a terminal dis- WO WO 99/ /1999 sk - claimer. FOREIGN PATENT DOCUMENTS cited by examiner Primary Examiner. Sheila V. Clark (21) Appl. No.: 09/481,927 (74) Attorney, Agent, or Firm-Bell, Boyd & Lloyd LLC (22) Filed: Jan. 12, 2000 (57) ABSTRACT Related U.S. Application Data A number of integrated circuit dies having on board protec tion against electrical overstress (EOS) transients are pro (63) Continuation-in-part of application No. 09/456,243, filed on Vided. Generally, the devices have an integrated circuit die Dec. 7, with an outer periphery and a functional die area. A plurality (60) Provisional application No. 60/ , filed on Dec. 8, of conductive input/output pads are formed on the integrated circuit die. Typically, a first conductive guard rail is disposed (51) Int. Cl."... H01L23/62 on the integrated circuit die and forms a gap between each (52) U.S. Cl.... 7,355; 7/787; 7,659 one of the input/output pads. A voltage variable material is (58) Field of Search s 7/ disposed in the gaps between the conductive guard rail and the input/output pads. Typically, a plurality of electrical s leads are electrically connected to a respective one of the (56) References Cited plurality of conductive input/output pads. At normal oper ating Voltages, the Voltage variable material is non U.S. PATENT DOCUMENTS conductive. However, in response to an EOS transient, the /1942 Grisdale Voltage variable material Switches to a low resistance State, A 6/1957 Bocciarelli providing a conductive path between the conductive guard 4,331,948 A 5/1982 Malinaric et al. rail and the input/output pads. 4, /1988 Hyatt et al. 4977,357. A 12/1990 Shrier 26 Claims, 7 Drawing Sheets SSSSSSSSSSSSSSSS N N SS SNN22NN SSS ka raps 1 N1 7-vs. N 4 N1 7-y-Nzz. N 4 NN 30 30

2 U.S. Patent Feb. 26, 2002 Sheet 1 of 7 US 6,351,011 B1 FIG.1 20 Amps t(nanose conds) High Resistance of OVP Device 2 (as a function of 3 changing voltage levels) A4 Lo W Voltage

3 U.S. Patent Feb. 26, 2002 Sheet 2 of 7 US 6,351,011 B1 FIG FUNCTIONAL Y DIE AREA PZ FIG Liz, t 27. i-34- YZ FUNCTIONAL LA 1. E. Z' A 4. L 27 Z% 2 19 L / Y FIG SeeBS&S ZS2N ŠEis 7 Y / / / / -/ a 30

4 U.S. Patent Feb. 26, 2002 Sheet 3 of 7 US 6,351,011 B1 FIG V Z Z / / / / / / / / / / / / / / /7ZZZZZZZ 1 F-4 L s Y L 19 A FUNCTQNAL DIE AREA AB, Y 42 a A 2.É * Las AAN- Ez E74 / / / / / / / / / /L / EŠssists Y / / / / / 10

5 U.S. Patent Feb. 26, 2002 Sheet 4 of 7 US 6,351,011 B1 2 FIG Azazz.f44, 4 40 C N Y 40 2-y 3- H-. a N < Z FUNCTIONAL 2 T Y A Azz == AREA Aziz 40 6 e Y - Y K as /O / Az -- / / / / / / / / / / / / / t 1 / / / / / / / / / / / / / / / / / ) LEAD FRAME 30 USED FOR ASSEMBLY FIG / 55 Yasy S.N.S.S SSSSSSSSSSSSSSSS 40 SS Rsy ASSN2i\SY N N N Ya 1 4 N 4N Y 4R IN AN Q 30 30

6 U.S. Patent Feb. 26, 2002 Sheet 5 of 7 US 6,351,011 B FIG.10 R^^ S.SYS, SNYSNNYSYNYSYNYNYNYN 2 FIG É>SSY 2.77 Z 7 NYYYYYYYYY / / / / / / / /

7 U.S. Patent Feb. 26, 2002 Sheet 6 of 7 US 6,351,011 B1 45 FIG. 13 LEAD FRAME Y a & s Dr. 20 LEAD FRAME GROUND

8 U.S. Patent Feb. 26, 2002 Sheet 7 of 7 US 6,351,011 B y 18O ADHESIVE 2N2Z4ANZAN 27-7FEazzzzz LAYER 2. As S17 Sf 1YSS) 24 VS/2SC TNN in 176 VVM AREA FIG YZ /// / ////// / &N2 N&S2. (2. CZ77N N2 N277 N.S

9 1 PROTECTION OF AN INTEGRATED CIRCUIT WITH VOLTAGE WARIABLE MATERALS This application is a Continuation-In-Part of U.S. appli cation Ser. No. 09/456,243, filed Dec. 7, 1999, that claims the benefit of U.S. Provisional Application No. 60/111,498, filed Dec. 8, BACKGROUND OF THE INVENTION The present invention generally relates to the use of Voltage variable materials for the protection of an integrated circuit against electrical overstress (EOS) transients. There is an increased demand for materials and electrical components which can protect electronic circuits from EOS transients which produce high electric fields and usually high peak energies capable of destroying circuits or the highly Sensitive electrical components in the circuits, ren dering the circuits and the components non-functional, either temporarily or permanently. The EOS transient can include transient Voltage or current conditions capable of interrupting circuit operation or destroying the circuit out right. Particularly, EOS transients may arise, for example, from an electromagnetic pulse, an electrostatic discharge, lightning, or be induced by the operation of other electronic or electrical components. Such transients may rise to their maximum amplitudes in microsecond to SubnanoSecond time frames and may be repetitive in nature. A typical waveform of an electrical OverStreSS transient is illustrated in FIG. 1. The peak amplitude of the electrostatic discharge (ESD) transient wave may exceed,000 volts with currents of more than 100 amperes. Materials for the protection against EOS transients (EOS materials) are designed to respond essentially instanta neously (i.e., ideally before the transient wave reaches its peak) to reduce the transmitted Voltage to a much lower value and clamp the Voltage at the lower value for the duration of the EOS transient. EOS materials are character ized by high electrical resistance values at low or normal operating Voltages and currents. In response to an EOS transient, the material Switches essentially instantaneously to a low electrical resistance value. When the EOS threat has been mitigated these materials return to their high resistance value. These materials are capable of repeated Switching between the high and low resistance States, allowing circuit protection against multiple EOS events. EOS materials are also capable of recovering essentially instantaneously to their original high resistance value upon termination of the EOS transient. For purposes of this application, the high resistance state will be referred to as the off-state' and the low resistance state will be referred to as the on-state. FIG. 2 illustrates a typical electrical resistance versus d.c. Voltage relationship for EOS materials. Circuit components including EOS materials can shunt a portion of the excessive Voltage or current due to the EOS transient to ground, thus, protecting the electrical circuit and its components. The major portion of the threat transient is either dissipated at the Source resistance or reflected back towards the Source of the threat. The reflected wave is either attenuated by the source, radiated away, or re-directed back to the Surge protection device which responds with each return pulse until the threat energy is reduced to Safe levels. A typical integrated circuit die having a plurality of input/output (I/O) conductive pads is illustrated in FIG. 3. Wires are bonded to the I/O pads and are connected to a corresponding electrical lead of a lead frame. Prior inte US 6,351,011 B grated circuit dies have Voltage Suppression components Such as diodes, thyristors or transistors formed on the die near the I/O pads during the processing of the die to protect oxide layers, Semiconductor junctions, and metal traces in the functional die area from the harmful effects of EOS transients. The assembly is typically encapsulated in a protective housing and the electrical leads of the lead frame which extend outwardly from the housing are formed in order to be connected to a circuit Substrate (e.g., a printed circuit board). The components used to protect the func tional area of the die are often relatively large, consuming costly die area which can otherwise be used for additional functions. In addition, the Overall encapsulated device is relatively large, consuming costly real estate on the circuit Substrate. SUMMARY OF THE INVENTION The present invention relates to an integrated circuit die and devices including Same that include a Voltage variable material to provide protection from EOS transients. Pursuant to the present invention, any Voltage variable material can be used. A number of advantages are provided by the present invention, where integrated circuit devices are Susceptible to high Voltages associated with EOS transients. In an embodiment, the present invention provides an integrated circuit including an electrically insulating Sub Strate having at least one microelectronic device formed thereon. An input/output pad and a conductive member are formed on the substrate. A bond wire is electrically con nected between the input/output pad and an electrical lead. A voltage variable material is located between the bond wire and the conductive member, the Voltage variable material exhibits non-conductive behavior at normal circuit operating Voltages and electrically connects the bond wire to the conductive member when a Sufficient EOS transient is introduced into the circuit. In an embodiment, the conductive member is a guard rail. In an embodiment, the Voltage variable material fills an entire Space between the bond wire and the conductive member. In an embodiment, the integrated circuit includes at least two input/output pads. In yet another embodiment of the present invention, an electrical device includes an integrated circuit die, an elec trical connector connected to the die, and a conductive guard rail. The electrical device also includes a voltage variable material exhibiting non-conductive behavior at normal cir cuit operating Voltages and forming a conductive path between the electrical connector and the conductive guard rail when a Sufficient EOS transient is introduced into the circuit. In an embodiment, the electrical connector is an input/out pad. In an embodiment, the electrical connector is a wire. In an embodiment, the Voltage variable material is Selec tively deposited on the guard rail, and the electrical connec tor is a wire juxtaposed to the guard rail. In an embodiment, the electrical connector is a wire and the wire is coated with the Voltage variable material. In a further embodiment of the present invention, an electrical device is provided that includes a ground pad, an integrated circuit die on the ground pad, an electrical lead, and a conductive island. The conductive island has first and Second electrical connectors, the first electrical connector is connected to the integrated circuit die and the Second

10 3 electrical connector is connected to the electrical lead. A Voltage variable material is disposed between the ground pad and the island. In an embodiment, the Voltage variable material com pletely fills the Space between the ground pad and the island. In an embodiment, the electrical device includes a plu rality of circuits. In an embodiment, the Voltage variable material is dis posed between the island and the electrical lead. In another embodiment of the present invention, an inte grated circuit is provided that includes a printed circuit board having an input/output pad and a Substrate having an upper Surface facing toward the printed circuit board. An input/output pad is located on the upper Surface of the Substrate and is electrically connected to the input/output pad of the printed circuit board. A ground pad is also located on the upper Surface of the Substrate. A voltage variable material is located between the ground pad and the input/ output pad of the upper Surface. In an embodiment, the ground pad is located in juxtapo Sition to the input/output pad. In an embodiment, the voltage variable material fills the entire Space between the ground pad and the input/output pad. In an embodiment, the printed circuit board further includes a ground pad adjacent the input/output pad of the printed circuit board, and the Voltage variable material electrically connects the input/output pad of the printed circuit board to the ground pad of the printed circuit board in response to an EOS transient energy. In an embodiment, the Voltage variable material fills an entire space between the input/output pad and the ground pad of the printed circuit board. In yet a further embodiment of the present invention, an integrated circuit is provided that includes an integrated circuit die, an insulating layer on the integrated circuit die, and a first electrical connector. A Second electrical connector is connected to the first electrical connector and connected to the integrated circuit die. A conductive member is located between a portion of the insulating layer and the integrated circuit die. A Voltage variable material is interposed between the portion of the insulating layer and the integrated circuit die, the Voltage variable material electrically connecting the Second electrical connector to the conductive member when an EOS transient is introduced into the circuit. In an embodiment, the conductive member is on the die. In an embodiment, the conductive member is on the insulating layer. In an embodiment, the insulating layer further includes a first side and the conductive member is located on the first Side. In an embodiment, the conductive member is a ground rail. In an embodiment, the conductive member is a power rail. Additional features and advantages of the present inven tion are described in, and will be apparent from, the detailed description of the presently preferred embodiments set forth below and the figures. BRIEF DESCRIPTION OF THE DRAWINGS Reference is made to the attached drawings, wherein elements having the same reference numeral represent like elements throughout and wherein: FIG. 1 graphically illustrates a typical current waveform of an EOS transient. US 6,351,011 B1 1O FIG. 2 graphically illustrates the electrical resistance versus d.c. voltage relationship of typical EOS materials. FIG. 3 illustrates a typical integrated circuit die. FIG. 4 illustrates a top view of an integrated circuit die according to one embodiment of the present invention. FIG. 5 illustrates a cross-sectional view along line A-A of the integrated circuit die shown in FIG. 4 having a layer of Voltage variable material deposited over the top Surface of the die. FIG. 6 illustrates a top view of an integrated circuit die according to another embodiment of the present invention. FIG. 7 illustrates a cross-sectional view along line A-A of the integrated circuit die shown in FIG. 6 having a layer of Voltage variable material deposited over the top Surface of the die. FIG. 8 illustrates an integrated circuit die according to the present invention electrically connected to a lead frame assembly. FIG. 9 illustrates the integrated circuit die of FIG. 8 encapsulated in a protective housing. FIGS illustrate alternative embodiments wherein a Voltage variable material connects a conductive guard rail in a first plane to an I/O pad in a Second plane. FIG. 13 illustrates a cross-sectional view of the integrated circuit die of FIG. 8 according to another embodiment of the present invention. FIG. 14 illustrates a cross-sectional view of an integrated circuit die according to another embodiment of the present invention. FIG. illustrates a cross-sectional view of an integrated circuit die according to another embodiment of the present invention encapsulated in a protective housing. FIG. 16 illustrates a cross-sectional view of a flip-chip integrated circuit mounted on a printed circuit board accord ing to the present invention. FIG. 17 illustrates a cross-sectional view of a chip scale packaging according to the present invention. DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS The present invention relates to integrated circuits and devices including Same. The products of the present inven tion include a Voltage variable material for protection against EOS transients. Pursuant to the invention, any Volt age variable material can be used. By way of example, and not limitation, examples of EOS materials and methods for making EOS materials that can be used in the present invention, the disclosures of which are incorporated herein by reference, are as follows. U.S. patent application Ser. No. 09/136,507 discloses compositions for providing protection against EOS. The compositions include a matrix formed of a mixture of an insulating binder, conductive particles having an average particle Size of less than 10 microns, and Semiconductive particles having an average particle size of less than 10 microns. The compositions utilizing relatively Small particle sized conductive and Semiconductive fillers exhibit clamp ing voltages in a range of about 30 volts to about 2,000 volts or greater. U.S. Pat. No. 2,273,704, issued to Grisdale, discloses granular composites which exhibit non-linear current Volt age relationships. These mixtures are comprised of granules of conductive and Semiconductive granules that are coated with a thin insulative layer and are compressed and bonded together to provide a coherent body.

11 S U.S. Pat. No. 2,796,505, issued to Bocciarelli, discloses a non-linear Voltage regulating element. The element is com prised of conductor particles having insulative oxide Surface coatings that are bound in a matrix. The particles are irregular in shape and make point contact with one another. U.S. Pat. No. 4,726,991, issued to Hyatt et al., discloses an EOS protection material comprised of a mixture of conductive and Semiconductive particles, all of whose Sur faces are coated with an insulative oxide film. These par ticles are bound together in an insulative binder. The coated particles are preferably in point contact with each other and conduct preferentially in a quantum mechanical tunneling mode. U.S. Pat. No. 5,476,714, issued to Hyatt, discloses EOS composite materials comprised of mixtures of conductor and semiconductor particles in the 10 to 100 micron range with a minimum proportion of 100 angstrom range insulative particles, bonded together in a insulative binder. This inven tion includes a grading of particle sizes Such that the composition causes the particles to take a preferential rela tionship to each other. U.S. Pat. No. 5, , issued to Childers, discloses foldback Switching materials which provide protection from transient overvoltages. These materials are comprised of mixtures of conductive particles in the 10 to 200 micron range. Semiconductor and insulative particles are also employed in these compositions. The Spacing between con ductive particles is at least 1000 angstroms. By way of further example, and not limitation, additional EOS polymer composite materials that can be used in the present invention are also disclosed in U.S. Pat. Nos. 4,331, 948, 4,726,991, 4,977,357,4992,333, 5,142,263, 5,189,387, 5,294,374, 5,476,714, 5,669,381, and 5,781,395, the teach ings of which are Specifically incorporated herein by refer CCC. Referring now to the drawings, FIG. 3 illustrates a con ventional integrated circuit die 10. The die 10 is typically comprised of a Silicon wafer having a functional die area 20 and a plurality of conductive input/output ( I/O ) pads. The functional area 20 of the die 10 has a circuit integrated therein. It should be generally understood by those having skill in the art that the integrated circuit can be created by various processes; e.g., by doping the Silicon, or depositing resistive and conductive films on the wafer and imposing patterns to form an electrical network. The present invention is concerned with protecting the integrated circuit from extremely high energies associated with EOS tran Sients. With reference to FIG. 4, the integrated circuit die 10 of the present invention includes a plurality of conductive I/O pads disposed on the surface of the die 10. The conduc tive I/O pads are electrically connected to the integrated circuit, i.e., the functional die area 20. A first conductive guard rail 30 is disposed on the die 10. Preferably, the guard rail 30 is disposed on the die 10 adjacent to the I/O pads and is comprised of a metallized trace. A gap a is formed between the guard rail 30 and each one of the I/O pads on the Surface of the die 10. In the embodiment illustrated, a Voltage variable material 35 is disposed on the surface of the die 10, filling the gaps a between the conductive guard rail 30 and each one of the plurality of I/O pads. As noted above, any voltage variable material, or EOS material, can be used pursuant to the present invention. Moreover, it should be noted that the material does not have to entirely fill the gaps a. The Voltage variable material 35 is in electrical contact, and US 6,351,011 B preferably in direct contact with, the conductive rail 30 and the I/O pads. At normal operating voltages (i.e., relatively low voltages), the voltage variable material 35 exhibits a relatively high electrical resistance. Thus, energies associ ated with the normal operation of the integrated circuit are not applied between the first conductive rail 30 and the I/O pads. However, upon application of an Eog transient energy (i.e., relatively high voltages), the voltage variable material 35 switches to a relatively low electrical resistance and electrically connects the I/O pads to the conductive guard rail 30. As a result, the voltage variable material 35 creates a conductive path away from the functional area of the die 20 for the EOS transient energy to follow. The conductive guard rail 30 can be connected to a ground rail or a +/- power Supply rail. As shown in FIG. 8, a plurality of electrical leads 40 are electrically connected to a respective one of the plurality of conductive I/O pads. Typically, the electrical leads 40 are wire bonded to the I/O pads. In a preferred embodiment, the Voltage variable material 35 is applied to the entire surface of the die 10 completely covering the guard ring 30, the plurality of 1/O pads and the functional die area 20 (as shown in the cross-sectional view of FIG. 5). However, the voltage variable material 35 can be applied in any manner or configuration as long as the material 35 connects the I/O pads to the conductive guard rail 30. For example, the material 35 can be applied as two Separate Strips, each Strip connecting the I/O pads located on opposite sides of the die 10 to the guard rail 30, or each I/O pad could be connected to the guard rail 30 with a separate body of voltage variable material 35. In another example, the Voltage variable material may be Selectively deposited between the I/O pads and the guard rail 30. The present invention also contemplates arrangements wherein the I/O pads and the conductive guard rail 30 are connected to the die 10 in different planes. For example, the voltage variable material 35 can be interposed between the I/O pads and the conductive guard rail 30 (see FIG. 12), or the Voltage variable material 35 can butt up against the ends of the I/O pads and the conductive guard rail 30 with an insulating layer 100 separating the I/O pads and the conductive guard rail 30 (see FIG. 10), or the voltage variable material 35 can be disposed on one of either the I/O pads or the conductive guard rail 30 and butt up against the end of the other one of the I/O pads or the conductive guard rail 30 with an insulating layer 100 separating the I/O pads and the conductive guard rail 30 (see FIG. 11). When an EOS transient is discharged to one of the electrical leads 40, a Voltage is applied to the corresponding I/O pad. This applied voltage from the EOS transient is much higher than the Voltage Supplied by the power Supply rail. The much higher Voltage causes the Voltage variable material 35 to rapidly Switch (e.g., a matter of nanoseconds) from a high resistance State to a low resistance State, collapsing the Voltage across the gap a between the I/O pad and the guard rail 30. As a result, the sensitive integrated circuit Structures in the functional die area 20 are protected from the harmful affects of the EOS transient energy. To achieve protection across a wider range of Voltages, the voltage variable material 35 could be used in combina tion with one or more discrete Voltage Suppression devices also electrically connected to the I/O pads. As mentioned above, Such devices may include a diode, thyristor or transistor. Additionally, the embodiment shown in FIG. 8 can utilize a bond wire 45 to establish a conductive path to the guard

12 7 rail 30 in the event of an EOS transient discharge. As shown in FIGS. 8 and 13, the bond wire 45 extends from each of the I/O pads to the lead frame to electrically connect the I/O pads to the lead frame. In an embodiment, the voltage variable material 35 is generally disposed on the die 20. The guard rail 30, the I/O pads and a portion of the bond wire 45 are in contact with the voltage variable material 35. A conductive path is established between the bond wire 45 and the conductive guard rail 30 that is connected to ground. Generally, this conductive path is desirable due to spacing and field line interaction between the wire bond 45 and the conductive guard rail 30. Of course, this concept is Susceptible to other embodi ments. Additional embodiments include coating the bond wire 45 with the voltage variable material 35 and laying the coated bond wire 45 on, or near, the conductive guard rail 30. Also, the voltage variable material 35 can be selectively deposited on the conductive guard rail 30 with the bond wire 45 injuxtaposition to the voltage variable material 35. Thus, when an EOS transient Voltage occurs a conductive path is created between the bond wire 45 and the guard rail 30. A preferred embodiment is shown in FIGS. 6 and 7, wherein a Second conductive guard rail 50 is disposed on the surface of the integrated circuit die 10. In this embodiment, the guard rails are formed adjacent to and on opposite sides of the I/O pads. In this sandwich configuration, the first conductive guard rail 30 is electrically connected to a positive power Supply rail and the Second conductive guard rail 50 is electrically connected to the negative power Supply rail. (Alternatively, the first conductive guard rail 30 can be connected to the negative power Supply rail and the Second conductive guard rail 50 connected to ground.) A gap a is formed between each of the first and second guard rails and the I/O pads. The voltage variable material 35 provides a path between the I/O pads and the first and second conductive guard rails or rings At normal operating Voltages, this path is not conductive. However, at the higher voltages associated with EOS transients, the path becomes conductive, thus, leading the EOS transient energy away from the functional die area 20. Preferably, the voltage variable material 35 is applied to the Surface of the integrated circuit die 10 and covers at least the I/O pads and the conductive guard rails In a more preferred embodiment, the Voltage variable material 35 is applied to the entire Surface of the integrated circuit die 10. It should be understood by those having skill in the art that many different configurations of guard rails can be used depending on the size and shape of the die 10 and the size and complexity of the electrical components form ing the integrated circuit. Similar to the application described above, a bond wire 45 can be utilized with the voltage variable material 35 to create a conductive path to either one of the conductive guard rails 30, 50 when higher voltages associated with EOS transients are present. In FIG. 14, another embodiment of the invention is illustrated. In this embodiment the device includes a con ductive island 80, an integrated circuit die 20 and a lead frame. Generally, the island 80 is made of a metallization. The island 80 is electrically connected to the lead frame via a bond wire 45. The island 80 is also connected to the die 20 via a bond wire 45a. A gap a is formed between the island 80 and ground. The voltage variable material 35 is disposed on the gap a between the island 80 and ground. This can be accom plished by generally filling the gap between the island 80 US 6,351,011 B and ground. AS discussed earlier, the gap a can be either completely filled or selectively deposited with the voltage variable material 35. In addition, the voltage variable mate rial 35 can cover the island 80 as well as the gap a. In the event of EOS transient energy causing higher Voltages, a conductive path is created between the island 80 and ground. An advantage of this embodiment is that the location of the lead frame is not critical due to the inclusion of the island 80. In fact, the lead frame can be located anywhere on the Substrate. AS Such, this embodiment provides for additional design flexibility of the integrated circuit device. AS discussed above, a wide range of Voltage variable materials 35 can be used in the present invention. Although the Scope of the present invention is not limited to any particular material, a Voltage variable material 35 exhibiting a high impedance at normal circuit operating Voltages is preferred. In another preferred embodiment, illustrated in FIG. 9, a protective housing 55 covers the integrated circuit die 10. The protective housing 55, preferably formed from an electrically insulating material, encapsulates the integrated circuit die 10 and physically connects the plurality of electrical leads 40 to the integrated circuit die 10. The electrical leads 40 project outwardly from the protective housing 55 and are adapted for electrically connecting the device 70 to a source of power. Additionally, FIG. shows another protective housing 82 that can be used for hermetic packaging applications. Generally, the device is encapsulated by a ceramic dish 84 that is built around the lead frame. A lid 86 covers the ceramic dish 84. The material of the lid 86 can be, for example, a metal or glass. The lid 86 and dish 84 are hermetically Sealed through various methods, Such as firing or braising the lid 86 and dish 84 together. Another embodiment of the invention utilizes the chip Scale packaging known as a flip-chip. FIG. 16 illustrates a flip-chip 105 mounted on a printed circuit board 110. The flip-chip 105 has a number of I/O pads 1. Next to each of the I/O pads 1 is a ground pad 130. The ground pads 130 are also located at a surface 132 of the flip-chip 105. The printed circuit board 110 also includes a number of I/O pads 140 and a number of ground pads 145 next to each of the I/O pads 140 on a surface 0 of the printed circuit board 110. In this example, the I/O pads 1 are electrically connected to the I/O pads 130 via solder balls or bumps 5. Of course, other Similar types of electrical connectors can be used. In FIG. 16, the voltage variable material 135 is used as an underfill that is interposed between the flip-chip 105 and the printed circuit board 110. Thus, in addition to the conductive characteristics of the Voltage variable material as discussed above, the Voltage variable material is also capable of providing mechanical under Strength to the device as well as protecting the electronic connections during the circuit board washing processes. When an EOS transient voltage occurs a conductive path is created between the I/O pads 1 or 140 and the respective ground pads 130, 145. In this embodiment, the conductive path occurs at the Surface 132 of the flip-chip 105 or the surface 0 of the printed circuit board 110. By maintaining a conductive path at the Surface, Stresses in the chip and/or printed circuit board caused by the EOS transients, Such as heat and radiation, are significantly reduced. Additionally, the voltage variable material 135 can be applied to the surface 132 of the flip-chip 105 only. In this application, the Voltage variable material 135 creates a conductive path between the I/O pad 1 of the flip-chip 105 and the respective ground pad 130 during EOS transient Voltages.

13 9 Alternatively, the voltage variable material 135 can be applied to the surface 0 of the printed circuit board 110. AS Such, the conductive path created by the Voltage variable material 135 is created at the surface 0 of the printed circuit board 110. Additionally, the voltage variable-material 135 can be disposed within a gap 136 that is created between the I/O pad 1 and the ground pad 130 or the I/O pad 140 and the ground pad 145. FIG. 17 illustrates a chip scale packaging 160 having a ball grid array 162. In this application, an integrated circuit die 164 includes a ground pin or rail 166, and a bond ribbon pad 168. A bond ribbon 170 includes a first end 172 and a Second end 174. The second end 174 is connected to the bond ribbon pad 168. The first end 172 of the bond ribbon 170 is connected to the solder ball 162. For example, the bond ribbon 170 is positioned between the solder ball 162 and a first side 175 of an insulating layer 176, e.g., apoly imide tape layer. A second side 177 of the insulating layer 176 faces toward the integrated circuit die 164. Similar to the flip-chip application described above, the voltage variable material 135 can be applied to the present chip scale packaging 160 as an underfill 135. In this application, the Voltage variable material 135 is interposed between the second side 177 of the insulating layer 176 and the integrated circuit die 164. When the EOS transient Voltage occurs, a conductive path is created between the bond ribbon 170 and the ground pin or rail 166. Additionally, the voltage variable material 135 does not have to completely underfill the space between the die 164 and the insulating layer. For example, the Voltage variable material can be applied in Area. A near the bond ribbon 170 and the ground rail 166. Further, the voltage variable mate rial 135 can be applied to the bond ribbon 170 or the ground rail 166 by many of the earlier methods described herein, e.g., coating the bond ribbon or Selectively depositing the Voltage variable material on the guard rail. In another embodiment of the invention, the ground rail 166 is located on the insulating layer 176. For example, the ground rail 166 can be on the first side 175 or on an end 180 of the insulating layer 176. Alternatively, the ground rail 166 can be a +/- power Supply rail. The electrical devices of the present invention: (1) protect against high EOS transient energies; and (2) may eliminate the need for on-die Voltage SuppreSSor components for certain applications and permit the use of Smaller on-die Voltage Suppressor components for other applications. In addition, utilizing a Voltage variable material on an inte grated circuit die in the manner disclosed herein consumes less die area than traditional Semiconductor Voltage Suppres Sion components while having the capability of protecting against comparable EOS transient energies. It should be understood that various changes and modi fications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the Spirit and Scope of the present invention and without diminishing its attended advantages. It is therefore intended that Such changes and modifications be covered by the appended claims. What is claimed is: 1. An integrated circuit comprising: an electrically insulating Substrate having at least one microelectronic device formed thereon; an input/output pad located on the Substrate; a conductive member located on the Substrate; US 6,351,011 B1 1O an electrical lead; a bond wire electrically connected between the input/ output pad and the electrical lead; and a voltage variable material located between the bond wire and the conductive member, the Voltage variable mate rial exhibiting non-conductive behavior at normal cir cuit operating Voltages and electrically connecting the bond wire to the conductive member when a Sufficient EOS transient is introduced into the circuit. 2. The integrated circuit of claim 1, wherein the conduc tive member is a guard rail. 3. The integrated circuit of claim 1, wherein the Voltage variable material fills an entire space between the bond wire and the conductive member. 4. The integrated circuit of claim 1, wherein the integrated circuit includes at least two input/output pads. 5. An electrical device comprising: an integrated circuit die; an electrical connector connected to the die; a conductive guard rail, and a Voltage variable material exhibiting non-conductive behavior at normal circuit operating Voltages and form ing a conductive path between the electrical connector and the conductive guard rail when a sufficient EOS transient is introduced into the circuit. 6. The electrical device of claim 5, wherein the electrical connector is an input/output pad. 7. The electrical device of claim 5, wherein the electrical connector is a wire. 8. The electrical device of claim 5, wherein the voltage variable material is Selectively deposited on the guard rail, and the electrical connector is a wire juxtaposed to the guard rail. 9. The electrical device of claim 5, wherein the electrical connector is a wire and the wire is coated with the Voltage variable material. 10. An electrical device comprising: a ground pad; an integrated circuit die on the ground pad; at least one electrical lead; a conductive island having first and Second electrical connectors, the first electrical connector connected to the integrated circuit die and the Second electrical connector connected to the at least one electrical lead; and a Voltage variable material disposed between the ground pad and the island. 11. The electrical device of claim 10, wherein the voltage variable material completely fills the Space between the ground pad and the island. 12. The electrical device of claim 10, wherein the elec trical device includes a plurality of circuits. 13. The electrical device of claim 10, wherein the voltage variable material is disposed between the island and the electrical lead. 14. An integrated circuit comprising: a printed circuit board having an input/output pad; a Substrate having an upper Surface facing toward the printed circuit board; an input/output pad on the upper Surface of the Substrate electrically connected to the input/output pad of the printed circuit board; a ground pad on the upper Surface of the Substrate, and a Voltage variable material located between the ground pad and the input/output pad of the upper Surface.

14 11. The integrated circuit of claim 14, wherein the ground pad is located in juxtaposition to the input/output pad. 16. The integrated circuit of claim 14, wherein the voltage variable material fills the entire Space between the ground pad and the input/output pad. 17. The integrated circuit of claim 14, wherein the printed circuit board further includes a ground pad adjacent the input/output pad of the printed circuit board, and the Voltage variable material electrically connects the input/output pad of the printed circuit board to the ground pad of the printed circuit board in response to an EOS transient energy. 18. An integrated circuit comprising: a printed circuit board having an input/output pad; a Substrate having an upper Surface facing toward the printed circuit board; an input/output pad on the upper Surface of the Substrate electrically connected to the input/output pad of the printed circuit board; a ground pad on the printed circuit board, the ground pad adjacent the input/output pad of the printed circuit board; and a voltage variable material located between the ground pad and the input/output pad of the printed circuit board. 19. The integrated circuit of claim 18, wherein the ground pad is located adjacent to the input/output pad of the printed circuit board. 20. The integrated circuit of claim 18, wherein the voltage variable material fills the entire Space between the ground pad and the input/output pad of the printed circuit board. US 6,351,011 B An integrated circuit comprising: an integrated circuit die; an insulating layer on the integrated circuit die; a first electrical connector; a Second electrical connector connected to the first elec trical connector and connected to the integrated circuit die, a conductive member located between a portion of the insulating layer and the integrated circuit die; and a Voltage variable material interposed between the portion of the insulating layer and the integrated circuit die, the Voltage variable material electrically connecting the Second electrical connector to the conductive member when a Sufficient EOS transient is introduced into the circuit. 22. The integrated circuit of claim 21, wherein the con ductive member is on the die. 23. The integrated circuit of claim 21, wherein the con ductive member is on the insulating layer. 24. The integrated circuit of claim 21, wherein the insu lating layer further includes a first Side and the conductive member is located on the first side.. The integrated circuit of claim 21, wherein the con ductive member is ground rail. 26. The integrated circuit of claim 21, wherein the con ductive member is a power rail.