(51) Int Cl.: H05K 1/11 ( ) H01L 23/538 ( )

Transcription

1 (19) (11) EP B1 (12) EUROPEAN PATENT SPECIFICATION (4) Date of publication and mention of the grant of the patent: Bulletin 2007/28 (21) Application number: (22) Date of filing: (1) Int Cl.: H0K 1/11 ( ) H01L 23/38 ( ) (86) International application number: PCT/EP2003/ (87) International publication number: WO 2004/ ( Gazette 2004/09) (4) IMPROVED STRUCTURE OF STACKED VIAS IN MULTIPLE LAYER ELECTRONIC DEVICE CARRIERS VERBESSERTE STRUKTUR GESTAPELTER KONTAKTLÖCHER IN MEHRSCHICHTIGEN ELEKTRONISCHEN BAUELEMENTETRÄGERN STRUCTURE AMELIOREE DE TROUS D INTERCONNEXION EMPILES DANS DES SUPPORTS DE DISPOSITIFS ELECTRONIQUES (84) Designated Contracting States: AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR (30) Priority: EP (43) Date of publication of application: Bulletin 200/07 (73) Proprietors: International Business Machines Corporation Armonk, NY 04 (US) Compagnie IBM France Courbevoie (FR) Designated Contracting States: MC (72) Inventors: CASTRIOTTA, Michele I-743 Manfredonia (IT) OGGIONI, Stefano I-2014 Besana Brianza (IT) ROGIANI, Gianluca I Milano (IT) SPREAFICO, Mauro I Sesto San Giovanni (IT) VIERO, Giorgio I Stezzano (IT) (74) Representative: Therias, Philippe Compagnie IBM FRANCE, Département de Propriété Intellectuelle 066 La Gaude (FR) (6) References cited: EP-A EP-A EP-A US-A US-A US-A US-B EP B1 Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). Printed by Jouve, 7001 PARIS (FR)

2 1 EP B1 2 Description Field of the Invention [0001] The present invention relates generally to the structure and manufacture of electronic printed circuit boards and chip carriers and more specifically to a particular structure of stacked vias in multiple layers high density electronic device carriers. Background of the Invention [0002] Several types of electronic components are implemented with a circuit, which is integrated in a chip of semiconductor material. The chip is typically mounted on a carrier, so as to protect the chip from mechanical stresses, and is then encapsulated in a package. The chip carrier includes an insulating substrate with conductive tracks ; each track is bonded to a corresponding terminal of the chip, and ends with a contact pad, typically for connection to a printed circuit board. Generally, chip carriers comprise several conductive layers wherein tracks transmitting signals and current are designed according to requirements depending upon both logical and electrical constraints as well as chip carrier manufacture constraints. Connections between layers are often done using vias or plated through holes. [0003] Likewise, printed circuit board generally comprises several conductive layers formed in an insulating material, linked with vias or plated through holes, that are adapted to transmit signals between several electronic devices or between electronic devices and connectors. [0004] US Patent,633,32 discloses a semiconductor apparatus including a semiconductor element and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base. The thin-film multilayer interconnection layer has insulating layers and interconnection patterns. The insulating layers and the interconnection patterns are alternately layered. Each of the insulating layers includes a first insulating layer part and a second insulating layer part. A surface of the second insulating layer part is more flat than that of the first insulating layer part, and each of the interconnection patterns is arranged on the surface of the second insulating layer part. [000] European Patent 0,47,83 discloses a multilayer interconnection substrate wherein first to third power interconnections are provided by first to third interconnection layers. A first insulating layer is provided between the first and second interconnection layers, and a second insulating layer is provided between the second and third interconnection layers. A plurality of first via holes are provided in the first insulating layer and connect the first and second power interconnection layers, and a plurality of second via holes are provided in the second insulating layer with positions shifted from those of the first via holes and connect the second and third power interconnection layers. A ceramic or glass ceramic substrate supports the layers. The structure has lower distribution resistance. [0006] When switching speeds of devices goes above 1 GHz clock rate, there is a need to no longer consider electrical signal transmission as a simple point to point transmission on a track but rather as the propagation of an electromagnetic wave supported by a current on a circuit trace. Such traces on electronic device carriers (chip carriers and printed circuit boards), also called transmission lines, represent a system comprising at least two conductive paths with specific properties (relation between transmission line width, distances between transmission lines, dielectric thickness between transmission lines and reference planes). These transmission lines comprise a conductive signal track or trace and another track and/or conductive plane, formed in close proximity and connected to a reference voltage or ground, for shielding the signal track from electromagnetic interference. The wave propagates along a transmission line defined by the signal track and an underlying reference voltage or ground plane, forming a complete loop path for the signal current. When the chip works at a high frequency, e.g. more than 1 GHz, the influence of the electronic device carrier may severely affects the performance of the electronic system as a whole. [0007] Particularly, any discontinuity (or transition) in the transmission line, such as any change in structure, material properties and design features, represent a change in the electrical impedance of the media and this generates a reflected wave. Moreover, the system includes stray structures (capacitors, inductors and resistors), which ant as low pass filters for the transmitted signal. As a consequence, the integrity of the electromagnetic wave propagated along the transmission line is not preserved. [0008] The transmitted signal, switching between a low voltage (logic value 0) and a high voltage (logic value 1), generates a square-shaped wave. Due to all discontinuities in the transmission line, this wave undergoes degradation and is generally received as a pseudo-sinusoidal wave. The quality of the transmitted wave can be visualized lay a so-called "eye diagram", which plots the value of the received signal as a function of the phase of a clock signal controlling the electronic device. The above described discontinuities in the transmission line reduce the opening of the eye diagram ; therefore, it is quite difficult to understand if a switching transition has actually taken place or if the shift of a signal baseline is due to a background noise. [0009] These drawbacks are particular acute in modern electronic systems working with a reduced level of a power supply voltage (down to 1.2 V). In this case, there is a very low margin to discriminate between the logic value 0 (0V) and the logic value 1 (1.2V). [00] Moreover, the continuous trend towards miniaturization of electronic devices requires a reduction in the dimensions of chip carrier and printed circuit board conductive tracks. However, the impedance of the transmis- 2

3 3 EP B1 4 sion line must be maintained at a desired value which optimizes the performance of the electronic device (typically 0Ω). Therefore, it is necessary to use a very thin dielectric layer between the conductive tracks and the ground plane (since the impedance is inversely proportional to the track width and directly proportional to the dielectric layer thickness). The short distance between the conductive tracks and the ground plane increases the value of a corresponding stray capacitance ; as a consequence, the bandwidth of the transmission line is strongly reduced. [0011] Therefore, as the quality of the transmission in the electronic device carrier, i.e. chip carrier or printed circuit board, is degraded it can cause the electronic device to operate at a frequency far lower than the working frequency which is afforded by the chip. [0012] Such phenomena may be reduced by using stacked vias so as to minimize the number of transition as illustrated on Figure 1. Figure 1a shows a cross-section part of a chip carrier 0 of Ball Grid Array (BGA) type comprising -a base or a core, three conductive lasers 1a, 1b and 1c, a surface layer 11 and dielectric layers 120. Generally, dielectric layer are made of epoxy while conductive layer are made of copper however, other materials are also used. Electronic device carrier 0 further comprises two solder balls referred to as 12-1 and 12-2 for connections and a blind plated through hole 130. As illustrated, vias are used to connect conductive layers, e.g. tracks 13 and 140 are connected thanks to vias 14, 10 and 1. However, as shown with black arrows, the transmission line from track 13 to track 140 comprises five transitions that may not preserve integrity of the electromagnetic wave propagated along the transmission line as mentioned above. Figure 1b shows a similar electronic device carrier 0 wherein vias 14, 10 and 1 are stacked so as to reduce the number of transitions along signal paths. Thus, the transmission line from track 13 to track 140 comprises only one transition as illustrated with black arrow. [0013] Stacking of vias implies manufacturing implications that may be -difficult to overcome with standard processes. Creating a buried via means to place a vertical connection between two different conductive layers with a dielectric placed between them. Processes to create this vertical connections are many such as mechanical drilling, laser and others. All of them start from one of conductive tracks present on one of the layers and need a receiving conductive pad in the other layer. Once the opening is achieved the receiving pad is exposed to a plating process that build the electrical conductive path along the aperture vertical walls establishing the continuity for an electrical signal between the two layers. The thickness of this metallization needs to be of a minimum value to compensate thermomechanical stresses and strains generated in the following manufacturing and operating conditions of the substrate. Plating of vias and blind vias conforms to vertical walls that have generally a reversed truncated cone shape. Dimensions of these vias are related to the technology used to create them, they usually have intrinsic plating limitations represented by the aspect ratio between the thickness of the dielectric to be drilled through over the selected diameter with the given drilling technology. The aspect ratio affects plating when the opening dimension, width over depth, reduces the flow of the plating solution within the via. Holes metallization operations in carrier manufacturing need to be accomplished in a reasonable time, with excellent uniformity along the vertical walls. Due to the extensive utilization of thin dielectric layers opening of the holes result larger than the depth of the holes. Plating of stacked vias requires to fill this large gap to achieve an acceptable receiving pad for the forthcoming stacked via extending the plating time. The longer time for plating is adversing the surface Copper circuitization conditions that results in an increased and higher thickness becoming no longer compatible with the fine pitch line to line requirements. Eventually a selective Copper etch-back operation is needed to re-ttlin the Copper on surface prior to etch the fine pitch circuitry. Manufacturing operations need to account for process tolerances that affect the minimum design dimensions of the stacked vias with further effect of their electrical impedance value. [0014] US Patent n, 78, 413 assigned to IBM Corporation disclosed a method of manufacturing a multiple layer circuit board with stacked vias of fine dimension and pitch. A base laminate with conductive pattern is coated with a dielectric which is photolithographically processed to create holes exposing selected regions of the underlying conductive pattern. The holes through the dielectric are plated to form via connections between the surface and the conductive pattern on the base laminate. The recess created by the via is filled with a. conductive and plateable polymer which upon curing forms a conductive plug. A second dielectric layer is deposited on the board structure and in succession photo-lithographically processed to expose the underlying plated via and plug. The hole in the second dielectric is plated and filled with conductive polymer so as to create a second via vertically aligned with and electrically connected to the underlying first via. The ability to form fine pitch stacked vias is particularly important for printed circuit board structures such as carriers of flip chip die, in that the fine pitch of the solder ball array of the flip chip needs to be expanded and/or disbursed through multiple board layers with minimum area and electrical degradation. [001] However, such kind of technology presents drawbacks for carrying high-speed signal in electronic device carriers, particularly in electronic device carriers dedicated to end customer telecommunication products. Firstly, it requires additional manufacturing steps that are not required in standard electronic device carrier manufacturing process and thus, increases their prices. Secondly, the transmission path along stacked vias is done through several conductive materials, e.g. copper and conductive polymer, that may disturb high-speed signals, e.g. generating signal reflection. Finally, the use of sev- 3

4 EP B1 6 eral conductive materials to stack vias induces mechanical and chemical constraints that may lead to unreliable electrical contacts between stacked vias and/or electronic device carrier fragility. Summary of the Invention [0016] Thus, it is a broad object of the invention to remedy the shortcomings of the prior art as described here above. [0017] It is another object of the invention to provide a stacked via structure adapted for carrying high speed signals. [0018] It is still another object of the invention to provide a stacked via structure adapted for carrying high intensity currents. [0019] It is a further object of the invention to provide a stacked via structure that reduces signal or current transmission line lengths. [0020] The accomplishment of these and other related objects is achieved by the stacked via structure in an electronic device carrier which is defined in claim 1. [0021] Further advantages of the present invention will become apparent to the ones skilled in the art upon examination of the drawings and detailed description. It is intended that any additional advantages be incorporated herein. Brief Description of the Drawings [0022] Figure 1 Figure 2 Figure 3 Figure 4 comprising figures 1a and 1b, illustrates cross-section views of an electronic device carrier showing electrical paths between conductive tracks when using non stacked vias (figure 1a) and stacked vias (figure 1b). depicts the 3D structure of stacked vias between three adjacent conductive layers of an electronic device carrier, according to the invention. comprising figures 3a, 3b, 3c and 3c, represents partial plan views of stacked vias, wherein figure 3a represents track design of a first conductive layer, figure 3b represents track design of a second conductive layer and figure 3c represents track design of a third conductive layer. Figure 3c illustrates another example of a track design of the third conductive layer. shows a perspective view of the part of an electronic device carrier comprising a core and three conductive Figures Figures 6 and 7 Figures 8 and 9 layers on each face to illustrate the use of the stacked via structure of the invention in conjunction with a core plated through hole and a solder ball. illustrate how vias have to be preferably disposed when three of them are used to connect conductive tracks of two adjacent conductive layers. illustrate examples of the shape of the conductive layer track on which vias are connected that may replace the annular ring of the preferred embodiment. represent diagrams illustrating the advantages provided by the stacked via structure of the invention in terms of electrical behavior by comparing the output of a design example for a known electronic device (curves a) with an electronic device including the stacked via structure of the invention (curves b). Detailed Description of the Preferred Embodiment [0023] According to the invention there is provided a stacked via structure that may be implemented in an electronic device carrier comprising several conductive layers. The electrical connection between two tracks belonging to two adjacent conductive layers is done through several vias, at least three and preferably four. The track portion to which vias are connected is designed so that it provides a symmetrical distribution of signal current across these vias. The shape of these tracks can be any geometrical solid metal shape, in a preferred embodiment, the shape of this track portion looks like an annular ring. Vias arranged between a second and a third conductive layers are not disposed at the same locations than vias arranged between a first and the second conductive layers, when considering z axis, to avoid manufacturing and electrical connection drawbacks as discussed above. [0024] With reference in particular to Figure 2, there is depicted the stacked via structure 200 of the invention, adapted to connect two conductive tracks belonging to two different conductive layers that are separated by a third conductive layer. The first conductive layer 1a comprises a first conductive track having the shape of an annular ring, referred to as 20a. Four vias 2-1 to 2-4 (generically referred to as 2) are connected to the annular ring 20a so as to provide an electrical connection with conductive track 20b having also the shape of an annular ring, belonging to conductive layer 1b, adjacent to conductive layer 1a. As mentioned above, conductive layers 1a and 1b are separated by a dielectric layer 120. Vias 2-1 to 2-4 are symmetrically 4

5 7 EP B1 8 arranged on conductive tracks 20a and 20b so that the electrical signal current flow is uniformly distributed among them. Similar structure is duplicated between conductive layers 1b and 1c. Four vias 21-1 to 21-4 (generically referred to as 21) are connected to the annular ring 20b so as to provide an electrical connection with conductive track 20c having also the shape of an annular ring, belonging to conductive layer 1c. Each vias 21 is connected to conductive track 20b such that the distances between this via and the two closest vias 2 are the same to obtain a uniform distribution of electrical signal current flow from vias 2-i to vias 21- j (i and j varying from 1. to 4). In the illustrated example of Figure 2, conductive tracks 20a, b and c are of the same Size and aligned along z axis, vias 2 are set at positions 0, 90, 180 and 270 considering the center of conductive tracks 20a, b and c with z axis and vias 21 are set at positions 9, 13, 22 and 31. [002] Considering now Figure 3 illustrating partial plan views of an electronic device carrier, there is shown a track design of three conductive layers 300a, b and c wherein the stacked via structure of the invention is implemented. On Figure 3a there is depicted a couple of coplanar tracks, referred to as 30-1 and 30-2, which are used to transmit a high frequency differential signal. Track 3 is arranged around signal tracks 30-1 and 30-2 and may be connected to the ground so as to shield the high frequency differential signal. In this example, tracks 30-1, 30-2 and 3 are formed in conductive layer 300a. One end of each tracks 30-1 and 30-2 looks like a partial annular ring, referred to as 31-1 and 31-2, respectively, where four vias and four vias are connected as illustrated. Now turning to Figure 3b, there is depicted two conductive tracks 32-1 and 32-2 having the shapes of annular rings. Conductive tracks 32-1 and 32-2 are formed in conductive layer 300b and connected to partial annular rings 31-1 and 31-2 thanks to vias and 320-2, respectively. Four vias and four vias are connected to conductive tracks 32-1 and 32-2, respectively, on the other side of conductive layer 300b when considering vias and As mentioned above, vias 32-1 and 32-2 are positioned such that the distances between a via of a side and the two closest vias of the other side connected to the same conductive track are the same, e.g. by forming an angle of 4 when four vias are used per side. On Figure 3c there is depicted a couple of coplanar tracks, referred to as 33-1 and 33-2, which are used to transmit the high frequency differential signal. Track 340 is arranged around signal tracks 33-1 and 33-2 and may be connected to the ground so as to shield the high frequency differential signal as mentioned by reference to Figure 3a. As illustrated, tracks 33-1, 33-2 and 340 are formed in conductive layer 300c. One end of each tracks 33-1 and 33-2 looks like a partial annular ring, referred to as 34-1 and 34-2, respectively, to which vias and are connected. Figure 3c shows an alternative example of the track design of the conductive layer 300c that now comprises two conductive tracks 34-1 and 34-2 having the shapes of disks to which vias and are connected respectively. In this example, conductive layer 300c is a surface layer and conductive tracks 34-1 and 34-2 are adapted to be connected to solder balls (not represented) so as to provide a connection with a chip or a printed circuit board. [0026] Figure 4-illustrates a complete conductive path that is adapted to transmit high frequency signal or high intensity current as well as any kind of other signals through an electronic device carrier. For sake of illustration, this electronic device carrier comprises a core 400 with no internal conductive layers, two additional conductive layers added to the core on each side, referred to as 40a-1, 40b-1, 40a-2 and 40b-2 and an external conductive layer 40c-1 and 40-c2 on each side, respectively. Conductive layer are separated by dielectric material 4 such as epoxy. Stacked via structures 41-1 and 41-2 according to the invention are arranged on each side of the core wherein a buried through hole 420 is done to connect these structures. One side of stacked via structure 41-1 is connected to buried through hole 420 and the other side is connected to a solder ball 42 that is adapted to be linked to a chip or a printed circuit board. Likewise, one side of stacked via structure 41-2 is connected to buried through hole 420 and the other side is connected, for the sake of illustration, to a conductive track 430 of the external conductive layer 400c- 2 to transmit the signal to another solder ball (not represented) or to another conductive path of the electronic device carrier (not represented). Tracks can be connected on any one of the given layers 40n-1 or 40m-2 (n and m varying from a to c in the illustrated embodiment) that creates the optimized conductive path. [0027] Figure 4 also illustrates the manufacturing steps of implementing the stacked via.. structure of the invention. Starting from the electronic device carrier core 400 that is covered with a copper foil, i.e. conductive layers 40a-1 and 40a-2, the core is drilled by mechanical drilling or laser drilling. The obtained hole 420 is then plated using an electroless copper plating operation. The plated hole gets filled with a resin matrix. At this point of the laminate manufacturing process a photomask is used in conjunction with photosensitive material to draw the conductive tracks, i.e. to protect the core with removable material where conductive track has to be implemented. After exposed photoresist is removed with unwanted copper foil, unexposed photoresist is also removed to obtain conductive tracks on the two surfaces of the core also defining the circular metal area or lands 43-1 on the top layer and 43-2 on the bottom layer, surrounding plated hole 420. On this circuitized substrate is then laminated or deposited a new layer of dielectric material 4, this can be in a form of a liquid dispense trough a courtain coating process followed by a curing process or through the lamination of a film. In this new dielectric layer openings can be created through an expose and develop process if the selected material has photosensitive properties

6 9 EP B1 or through laser drilling in the case of laminated films. These new holes represent the next layer interconnection step, i.e. connections from conductive layer 40a-1 to 40b-1 and from conductive layer 40a-2 to 40b-2. Using again an electroless Copper plating process the whole surface of the newly added dielectric layer gets plated including the newly created holes and shown for the upper layer in the laminate structure. Again a photomask is used in conjunction with photosensitive material to draw the conductive tracks. After exposed photoresist is removed with unwanted copper foil, unexposed photoresist is also removed to obtain conductive tracks on the two surfaces and defining the circular or annular structure on this dielectric layer, i.e. conductive tracks 44-1 and The vias at their bottom are in contact with the Copper land 43-1 of the top core layer 40a-1 while their top are in contact with the Copper land 44-1 of the conductive layer 46b-1 in positions indicated on Figure 4. Analogous schematization is applicable to the lower side of the core were vias of the added dielectric layer will be in contact with the underneath land 43-2 and the Copper land 44-2 of the conductive layer 40b-2. At this point the whole process is repeated as many times as it is necessary adding new dielectric layers and processing holes and holes plating, i.e. to create vias 40-1 and 40-2 and Copper lands 4-1 and 430. [0028] Now -turning to Figure, there is shown how vias have to be preferably disposed when three of them are used to connect conductive tracks of two adjacent conductive layers. As mentioned above, the vias must be disposed so as to distribute uniformly the electrical signal current flow among the vias. Figure comprises two annular rings 00-1 and 00-2 that are formed in two adjacent conductive layers, annular ring 00-1 being formed in the upper conductive layer. Thus, considering annular rings 00-1 and 00-2, the three vias 0-1, 0-2 and 0-3 that link these annular rings must be placed on lines forming an angle of α = 360 /n =120 according to z axis, n being the number of vias used to connect two adjacent conductive layer in the stacked via structure of the invention, i.e. n = 3 in this example. Furthermore, the distances d between the vias and the center of the annular rings 00-1 and 00-2 must be the same. Likewise, the three vias -1, -2 and -3 that connect annular ring 00-1 to a conductive track of an upper conductive layer and the three vias 1-1, 1-2 and 1-3 that connect annular ring 00-2 to a conductive track of a lower conductive layer have to be disposed according to the position of vias 0-1, 0-2 and 0-3. Vias -1, -2 and -3 must be placed on lines forming an angle of α = 120, perpendicular to z axis, these lines forming an angle of α/2 = 60 with the lines on which vias 0-1, 0-2 and 0-3 are disposed. The distance d between the vias and the center of the annular rings 00-1 and 00-2 must be the same but does not need to be the same as the distance d between vias 0-1, 0-2 and 0-3 and the center of the annular rings 00-1 and [0029] Figures 6 and 7 show examples of conductive tracks that may replace the above mentioned annular rings of the stacked via structure of the invention. Each figure comprises the conductive tracks of two adjacent conductive layers and an example of the position of the vias when four of them are used to connect to adjacent conductive tracks. These conductive tracks show a relative rotation of 4 on each of the given layers 00-n (n being-the number of the layers available on the different side of the core laminate structures). This configuration with inserted slots in the annular ring or a design with lobes avoid to establish loops for currents that will generate adverse condition to the propagation of the electromagnetic wave. [0030] With reference in particular to Figure 8, there is depicted a diagram representing the phase versus the frequency for a known electronic module wherein vias are not stacked as described by reference to Figure 1a (curve a) and for an electronic device comprising the stacked via structure of the invention (curve b). This diagram shows that even if mechanically these two structures are comparable allowing the vertical (Z) path transition of the conductive tracks, they shows a complete different electrical behaviour. This difference translates in different delays in the transmission of an incident electrical signal. In an application example using signal running at 1GHz (equal to a cycle time of- about 66 ps) the two structures show a difference delay of about 17 ps on the incident wave, as illustrated on Figure 9 wherein curve s corresponds to the input signal. Such a delay difference represents a quarter of the total cycle time allowing, in the case of stacked structure usage, a better signal management with a lower distortion effect on signal fronts. [0031] Naturally, in order to satisfy local and specific requirements, a person skilled in the art may apply to the solution described above many modifications and alterations all of which, however, are included within the scope of protection of the invention as defined by the following claims. Claims 1. A stacked vias structure (200) in an electronic device carrier to connect a first and a second conductive tracks (20a, 20c) belonging to a first and a second conductive layers (1a, 1c), said first and second conductive layers being separated by at least one third conductive layer (1b), a dielectric layer (120) being disposed between each of said conductive layers, said stacked via structure comprising : - a third conductive track (20b) belonging to said at least one third conductive layer, said third conductive track being aligned with at least one part of said first and second conductive tracks 6

7 11 EP B1 12 according to the axis (Z) perpendicular to said conductive layers ; - a first set of vias (2) disposed between said first conductive track (20a) and said third conductive track (20b); - a second set of vias (21) disposed between said second conductive track (20c) and said third conductive track (20b); wherein said third conductive track is connected to said first and second conductive track by means of said first and second set of vias, and wherein said first set of vias (2) and said second set of vias (21) each consists of an equal number n of vias, where n is greater than two, each via of said first set of vias (2) is placed at a first distance d from said axis (Z) on a respective one of a first set of lines radiating from said axis and forming a first angle α = 360/n between adjacent lines, each via of said second set of vias (21) is placed at a second distance d from said axis (Z) on a respective one of a second set of lines radiating from said axis and forming a first angle α = 360 /n between adjacent lines, and each of said first set of lines forms a second angle of α/2 with a corresponding one of said second set of lines. 2. The stacked via structure of claim 1 wherein the shape of at least one of said conductive tracks is a disk or an annular ring. 3. The stacked via structure of either claim 1 or claim 2 wherein said first set of vias (2) and said second set of vias (21) comprises four vias. 4. The stacked via structure of claim 3 wherein the angle formed by two adjacent vias of said first or second set of vias (214, 21) and the center of said third conductive track (20b) and said aligned parts of said first and second conductive tracks (20a, 20c) is equal to 90.. The stacked via structure of claim 4 wherein the angle formed between a via of said first set of vias (2), the closest via of said second set of vias (21) and the center of said third conductive track (20b) and said aligned parts of said first and second conductive tracks (20a, 20c) is equal to The stacked via structure of anyone of claims 1 to wherein said vias of said first or second set of vias (2, 21) are equidistant to the center of said third conductive track (20b) and said aligned parts of said first and second conductive tracks (20a, 20c) 7. The stacked via structure of anyone of claims 1 to 6 wherein said first or second conductive track (20a, c) adapted to be connected to a solder ball. 8. The stacked via structure of anyone of claims 1 to 7 wherein said first or second conductive track (20a, 20c) is adapted to be connected to a blind through hole. Patentansprüche 1. Gestapelte Kontaktlochstruktur (200) in einem Träger für elektronische Bauelemente, um eine erste und eine zweite Leiterbahn (20a, 20c) zu verbinden, die zu einer ersten und einer zweiten leitfähigen Schicht (1a, 1c) gehören, wobei die erste und zweite leitfähige Schicht durch mindestens eine dritte leitfähige Schicht (1b) getrennt sind und eine dielektrische Schicht (120) zwischen den jeweiligen leitfähigen Schichten angeordnet ist, wobei die gestapelte Kontaktlochstruktur das Folgende umfasst: - eine dritte Leiterbahn (20b), welche zu mindestens einer dritten leitfähigen Schicht gehört, wobei die dritte Leiterbahn an mindestens einem Teil der ersten und zweiten Leiterbahn gemäß der Achse (Z), die senkrecht auf den leitfähigen Schichten steht, ausgerichtet ist; - eine erste Gruppe von Kontaktlöchern (2), die zwischen der ersten Leiterbahn (20a) und der dritten Leiterbahn (20b) angeordnet sind; - eine zweite Gruppe von Kontaktlöchern (21), die zwischen der zweiten Leiterbahn (20c) und der dritten Leiterbahn (20b) angeordnet sind; wobei die dritte Leiterbahn mit der ersten und der zweiten Leiterbahn mittels der ersten und zweiten Gruppe von Kontaktlöchern verbunden ist, und wobei die erste Gruppe von Kontaktlöchern (2) und die zweite Gruppe von Kontaktlöchern (21) jeweils aus einer gleichen Anzahl n von Kontaktlöchern besteht, wobei n größer als zwei ist, jedes Kontaktloch der ersten Gruppe von Kontaktlöchern (2) in einem ersten Abstand d von der Achse (Z) auf einer entsprechenden einer ersten Gruppe von Linien angeordnet ist, die radial von der Achse abgehen und einen ersten Winkel α = 360 /n zwischen benachbarten Linien bilden, jedes Kontaktloch der zweiten Gruppe von Kontaktlöchern (21) in einem zweiten Abstand d von der Achse (Z) auf einer entsprechenden einer zweiten Gruppe von Linien angeordnet ist, die radial von der Achse abgehen und einen ersten Winkel α = 360 /n zwischen benachbarten Linien bilden, und jede der ersten Gruppe von Linien einen zweiten Winkel α/2 mit einer entsprechenden der zweiten Gruppe von Linien bildet. 2. Gestapelte Kontaktlochstruktur nach Anspruch 1, 7

8 13 EP B1 14 wobei mindestens eine der Leiterbahnen die Form einer Scheibe oder eines Rings aufweist. 3. Gestapelte Kontaktlochstruktur nach Anspruch 1 oder Anspruch 2, wobei die erste Gruppe von Kontaktlöchern (2) und die zweite Gruppe von Kontaktlöchern (21) vier Kontaktlöcher umfasst. 4. Gestapelte Kontaktlochstruktur nach Anspruch 3, wobei der Winkel, der von zwei benachbarten Kontaktlöchern der ersten oder zweiten Gruppe von Kontaktlöchern (2, 21) und dem Mittelpunkt der dritten Leiterbahn (20b) und den ausgerichteten Teilen der ersten und zweiten Leiterbahn (20a, 20c) gebildet wird, gleich 90 ist. 1 - une troisième piste conductrice (20b) appartenant à ladite au moins une troisième couche conductrice, ladite troisième piste conductrice étant alignée avec au moins une partie desdites première et seconde pistes conductrices conformément à l axe (z) perpendiculaire auxdites couches conductrices, - un premier ensemble de trous d interconnexion (2) disposés entre ladite première piste conductrice (20a) et ladite troisième piste conductrice (20b), - un second ensemble de trous d interconnexion (21) disposés entre ladite seconde piste conductrice (20c) et ladite troisième piste conductrice (20b),. Gestapelte Kontaktlochstruktur nach Anspruch 4, wobei der Winkel, der zwischen einem Kontaktloch der ersten Gruppe von Kontaktlöchern (2), dem nächstgelegenen Kontaktloch der zweiten Gruppe von Kontaktlöchern (21) und dem Mittelpunkt der dritten Leiterbahn (20b) und den ausgerichteten Teilen der ersten und zweiten Leiterbahn (20a, 20c) gebildet wird, gleich 4 ist. 6. Gestapelte Kontaktlochstruktur nach einem der Ansprüche 1 bis, wobei die Kontaktlöcher der ersten oder zweiten Gruppe von Kontaktlöchern (2, 21) den gleichen Abstand zum Mittelpunkt der dritten Leiterbahn (20b) und der ausgerichteten Teile der ersten und zweiten Leiterbahn (20a, 20c) aufweisen. 7. Gestapelte Kontaktlochstruktur nach einem der Ansprüche 1 bis 6, wobei die erste oder zweite Leiterbahn (20a, 20c) dafür geeignet ist, mit einer Lötkugel verbunden zu werden. 8. Gestapelte Kontaktlochstruktur nach einem der Ansprüche 1 bis 7, wobei die erste oder zweite Leiterbahn (20a, 20c) dafür geeignet ist, mit einem blinden Durchgangsloch verbunden zu werden. Revendications 1. Structure de trous d interconnexion empilés (200) dans un support de dispositif électronique destinée à connecter une première et une seconde pistes conductrices (20a, 20c) appartenant à une première et à une seconde couches conductrices (1a, 1c), lesdites première et seconde couches conductrices étant séparées par au moins une troisième couche conductrice (1b), une couche de diélectrique (120) étant disposée entre chacune desdites couches conductrices, ladite structure de trous d interconnexion empilés comprenant : où ladite troisième piste conductrice est connectée auxdites première et seconde pistes conductrices au moyen desdits premier et second ensembles de trous d interconnexion et où ledit premier ensemble de trous d interconnexion (2) et ledit second ensemble de trous d interconnexion (21) consistent chacun en un nombre égal n de trous d interconnexion, où n est supérieur à deux, chaque trou d interconnexion dudit premier ensemble de trous d interconnexion (2) est placé à une première distance d dudit axe (z) sur une ligne respective d un premier ensemble de lignes rayonnant depuis ledit axe et formant un premier angle α = 360 /n entre les lignes adjacentes, chaque trou d interconnexion dudit second ensemble de trous d interconnexion (21) est placé à une seconde distance d dudit axe (z) sur une ligne respective d un second ensemble de lignes rayonnant depuis ledit axe et formant un premier angle α = 360 /n entre les lignes adjacentes, et chaque ligne dudit premier ensemble de lignes forme un second angle de α/2 avec une ligne correspondante dudit second ensemble de lignes. 2. Structure de trous d interconnexion empilés selon la revendication 1, dans laquelle la forme d au moins l une desdites pistes conductrices est un disque ou une couronne annulaire. 3. Structure de trous d interconnexion empilés selon soit la revendication 1, soit la revendication 2, dans laquelle ledit premier ensemble de trous d interconnexion (2) et ledit second ensemble de trous d interconnexion (21) comprennent quatre trous d interconnexion. 4. Structure de trous d interconnexion empilés selon la revendication 3, dans laquelle l angle formé par deux trous d interconnexion adjacents dudit premier ou dudit second ensemble de trous d interconnexion (2, 21) et le centre de ladite troisième piste conductrice (20b) et desdites parties alignées desdites 8

9 1 EP B1 16 première et seconde pistes conductrices (20a, 20c) est égal à 90 C.. Structure de trous d interconnexion empilés selon la revendication 4, dans laquelle l angle formé entre un trou d interconnexion dudit premier ensemble de trous d interconnexion (2), le trou d interconnexion le plus proche dudit second ensemble de trous d interconnexion (21) et le centre de ladite troisième piste conductrice (20b) et desdites parties alignées desdites première et seconde pistes conductrices (20a, 20c) est égal à Structure de trous d interconnexion empilés selon l une quelconque des revendications 1 à, dans laquelle lesdits trous d interconnexion dudit premier ou dudit second ensemble de trous d interconnexion (2, 21) sont équidistants du centre de ladite troisième piste conductrice (20b) et desdites parties alignées desdites première et second pistes conductrices (20a, 20c) Structure de trous d interconnexion empilés selon l une quelconque des revendications 1 à 6, dans laquelle ladite première ou seconde piste conductrice (20a, 20c) est conçue pour être connectée à une bille de soudure Structure de trous d interconnexion empilés selon l une quelconque des revendications 1 à 7, dans laquelle ladite première ou ladite seconde piste conductrice (20a, 20c) est conçue pour être connectée à un trou traversant borgne

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16 EP B1 REFERENCES CITED IN THE DESCRIPTION This list of references cited by the applicant is for the reader s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard. Patent documents cited in the description US A [0004] EP A [000] US A [0014] 16