A Generic Analytical Model of Switching Characteristics for Efficiency-Oriented Design and Optimization of CMOS Integrated Buck Converters

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1 A Generic Analytical Model of Switching Characteristics for Efficiency-Oriented Design and Optimization of CMOS Integrated Buck Converters Rohit Modak and Maryam Shojaei Baghini VLSI Design Lab, Department of Electrical Engineering Indian Institute of Technology(IIT)-Bombay, Mumbai , India Abstract Power management and supply generation is an important issue in SOCs (System On Chips). Design of on-chip CMOS buck converters for maximum efficiency needs models which can predict different kinds of losses in the converters. In this paper a generic analytical model for switching times and accordingly I-V overlap losses for on-chip CMOS synchronous buck converters is presented. The model features the derivation of the delay on the basis of change in the stored charge during switching of internal capacitances. Therefore the proposed model needs only a few process parameters to estimate the delays and accordingly I-V overlap losses. Another feature of the presented model is that it s independent of the switch driver and is applicable to a wide range of input voltage and load conditions. The proposed model is implemented in MATLAB and verified against detailed CADENCE Spectre simulations for integrated buck converter design and optimization. Estimations from the model match detailed simulation results for the input voltage range of 2.8 V to 5 V and load current range of 65 ma to 200 ma, which are also presented in this paper. We demonstrate application of the proposed model for elaborative and efficient design space exploration for efficiency-oriented design of buck converters. I. INTRODUCTION DC-DC converters are extensively used in mobile devices like cellphones, PDAs and digital cameras. These converters provide regulated DC voltage by converting the battery output voltage to the required levels. As more and more devices are being accommodated on a single chip and the operating frequencies are increasing, it is imperative for the converters to be highly efficient. Generally the converters used in mobile and portable devices are low power output. The output current does not exceed a few hundred milliamperes. Among DC- DC converters, buck converters are very popular as these type of converters exhibit high conversion efficiency and voltage regulation [1] [3] compared to others. Fig. 1 shows the basic schematic of a typical buck converter. PWM (Pulse Width Modulation) block alternately switches PMOS and NMOS transistors, S1 and S2. As a result a periodic rectangular waveform is generated, which is applied to the low pass filter, composing inductor L and capacitor C. Duty cycle of switching depends upon the output voltage. Buck converter can either be implemented off-chip or can be integrated along with the other modules of SoC (system on chip). Integrating the switching devices and control circuitry on the same IC Fig. 1. Buck converter. (integrated circuit) along with the rest of the modules of SoC reduces the losses due to off-chip parasitics and interconnects. Thus, efficiency of an integrated converter is more compared to an off-chip converter [4]. A. Different Losses There are three major sources of power loss in power buck converters [5]. Similar losses exist in integrated CMOS buck converters. a) Conduction losses: These are due to the power dissipation in all components of the converter when they are ON and conduct the current. For example losses due to ON resistance of the transistors, diode forward voltage drop and parasitic resistance of inductor and capacitor. b) Switching losses: They constitute power dissipation which occurs during switching of components. Switching losses depend on the switching frequency. For example when a transistor switches from OFF to ON (triode region) there is a considerable power dissipation (IV) during the transition. This transient power dissipation is known as I-V overlap loss. Commonly-known FCV 2 loss originating from charging and discharging of capacitors (e.g gate capacitors) is another example of switching losses. c) Reverse recovery losses: It takes time for a diode operating in forward-bias region to switch to reverse bias. During this time diode will draw a reverse current to store the required amount of charge. In the buck converter shown in Fig. 1, the reverse current of the body diode of NMOS transistor is drawn from the PMOS transistor while it s turning on. This leads to power dissipation in the PMOS switch as

2 well as energy consumption to charge the body diode. Reverse recovery loss is in fact a part of switching loss. However to distinguish it from other switching losses due to charge and discharge of parasitic capacitances it is considered separately. Efficiency (η) of a buck converter is given by η = P out P out + P loss, (1) where P loss is total average dissipated power and P out is power delivered to the load. P loss is composed of P loss = P cond + P sw + P rr + P gate +P driver + P controller (2) In Eq. (2) P cond is the conduction power loss, P sw is the switching loss, P rr is the reverse recovery loss, P gate is the power dissipated because of charge/discharge of gate capacitors, P driver and P controller are the power dissipated in driver and controller respectively. In this design P driver + P controller is 10 mw. B. Design parameters To maximize the efficiency of a CMOS buck converter, circuit parameters should be optimized. One of the main design parametersis the size of switches. As size of the switch increases, conduction loss decreases whereas switching loss increases. Switching frequency has a strong impact over the converter efficiency and size of the passive components. The converter switching frequency is increasing so that the size of passive components can be reduced and stringent transient requirements of future microprocessors can be met[6]. For low power output buck converters operating at high frequencies, switching losses are significant. In order to prevent current shoot-through, in the synchronous buck architecture some dead time has to be ensured between switching ON of one switch and switching OFF of the other, particularly between turn-on of pull-up switch and turn-off of pull-down switch. Inductor current is supported by the body diode of NMOS switch during dead time, which in turn leads to conduction loss in the body diode. Therefore knowledge of switching times is critical in deciding the dead time. To achieve the maximum efficiency, design parameters like size of switches, dead time and switching frequency need to be optimized through an iterative optimization procedure over the entire range of input voltage and load current. This procedure requires a transistor level simulator to be invoked iteratively in the optimization loop to accurately quantify the losses. For each simulation it takes several hundred cycles for a buck converter to reach to its steady state. Apart from this aspect, simulation step size of a few nanoseconds or even less may be required for accurate analysis during switching on/off transitions. Available commercial circuit simulators are not fast enough for these long simulations as the transistor models (e.g BSIM3 or BSIM4 [7]) are too complex. Therefore an analytical model of various losses in a buck converter will be of great importance for the designer to reduce the design and optimization time. Analytical models for different losses in a buck converter have been reported in many research works. Fairly accurate model for conduction losses in the switches, parasitic series resistance of the inductor, capacitor and the body diode are reported [1], [8]. However, a comprehensive and general model for I-V overlap loss during switching transition is needed to accurately estimate the efficiency. Contribution of I-V overalp loss during switching transitions is significant in low power converters and they might even dominate the losses at low load conditions. Previous models of I-V overlap loss either rely on precharacterized discrete power MOSFETs as switches [9] and/or assume current mode drivers [10], [11]. However the trend is to implement the low power buck converters in standard CMOS technologies. In [4], an unknown optimum value of the width of the transistor switches is used to maximize the efficiency. However no expression for the switching times and different losses is given. In [6], the reported model is valid only for the switches driven by specific resonant gate driver and in [8] the proposed model is almost completely empirical. Another aspect of reported models is that the reverse recovery loss is excluded from the I-V overlap loss and is not verified with circuit simulations. Thus, an analytical model relating the technology parameters to the losses independent of driver would be very useful for the designer. It should be noted that I-V overlap loss occurs during the switching of both PMOS as well as NMOS switch. However PMOS loss is dominant as the voltage switched across NMOS is small. C. Our contribution and organization of the paper In this paper a generic analytical model for I-V overlap loss during switching of PMOS switch of an integrated synchronous buck converter based on a few process parameters in standard CMOS technologies is presented. The presented model is independent of the driver and is applicable to a wide range of input voltage and load conditions. The model predicts the switching times and I-V overlap losses in the PMOS switch and body diode, with an accuracy of ±10 %, with reduced design time. The accuracy achieved is good enough for initial design before detailed circuit optimization. The presented model is implemented in MATLAB. The program run time is much faster compared to the commercial circuit simulators. The model is verified using Cadence Spectre simulator. Losses are calculated in CADENCE using CALCULATOR tool. Application and effectiveness of the proposed model to the design and optimization of a buck converter in 0.35 µm CMOS process under different values of input voltage ranging from 2.8 V to 5 V, load current ranging from 65 ma to 200 ma and output voltage of 1.8 V is also demonstrated. The rest of the paper is organized as follows. In Section II, we discuss the analytical model for switching loss and switching time of PMOS transistor in synchronous buck converters. In Section III, we compare the results from the model and those from detailed circuit simulation. Application of the model in optimization of design parameters is discussed in Section IV. Concluding remarks are presented in Section V.

3 II. MODELING OF SWITCHING TIME AND I-V OVERLAP LOSSES This section presents the analytical model for I-V losses and switching times of the integrated PMOS switch in the buck converter independent of the switch driving characteristics. Notations- Through out this paper F sw denotes the frequency of PWM output voltage. V in and V f refer to supply voltage and forward bias voltage drop of the body diode of NMOS transistor, respectively. I p and I b are the peak and bottom values of the inductor current. t on and t off are the turn-on and turn-off times of PMOS switch. I o represents load current. Q rr denotesthe total change in the charge stored in the body diode of NMOS transistor while switching from forward bias to reverse bias. A. Switching loss Turn-on: Fig. 2 shows typical drain-source voltage and drain current waveforms of PMOS transistor during switch-on transition. The waveforms are real simulated waveforms for an integrated buck converter in 0.35 µm CMOS technology. The current rises above the inductor current because of the reverse recovery phenomenon in the body diode of the NMOS switch. It can be seen that drain voltage remains almost constant during the time till drain current of PMOS transistor is less than the bottom value of inductor current. This commonlyknown effect is attributed to the effect of total effective capacitance existing at the drain terminal of PMOS transistor. The current and voltage waveforms can be approximated with linear waveforms as shown in Fig. 3. The area of I-V overlap region can be evaluated in two parts, I-V overlap when I d is less than I b and that when I d is more than I b. The later one is due to reverse recovery. The area under I d values more than I b gives the reverse recovery charge. Power dissipation due to the current overshoot is called reverse recovery loss. Accordingly corresponding losses are simply derived as follows: Fig. 2. Typical current and voltage waveforms during PMOS turn-on. I d peaks to a high value due to reverse recovery in body diode of NMOS transistor. Fig. 3. Linear approximation of current and voltage waveforms during PMOS turn-on and turn-off. Fig. 4. Current and voltage waveforms of body diode during diode turn-off. ton P I VON = F sw V sd I d dt (3) P I VON = (V in + V f )I b F sw t on. (4) 2 Power dissipation in PMOS transistor due to reverse recovery of the NMOS body diode can be written as P rrpmos = Q rrf sw (V in + V f ). (5) 2 Thus, the total I-V overlap loss during PMOS turn-on is 0 P on = P I VON + P rrpmos. (6) From the linear approximation shown in Fig. 4 power dissipation in the body diode due to reverse recovery can be estimated to be P rrbd = Q rrf sw ( Vin 3 + av f ), (7) 1 + a where, a = T 1 T 0 T 2 T 1. Parameter a depends on the nature of reverse recovery of the diode (soft or snap recovery). For the technologyused, a = 1/3. This value of a was obtained easily by running one simulation for characterizing the body diode. Turn-off: Fig. 5 shows the simulated waveforms for drain and gate current and drain-source and gate voltage during

4 source, the gate current waveform is a rectangle. The net charge transferred to the gate of a switch can be written as Q = { Igpeak t off 2, for tapered buffer driver I g t off, constant current driver (12) where I gpeak is the peak gate current shown in Fig. 3. I gpeak is the driver specification. C g is the total gate capacitance. For our case of tapered buffer driver, Fig. 5. Current and voltage waveform during PMOS turn-off. I d drops sharply at the end as body diode of NMOS starts conducting. PMOS turn-off. These waveforms can be approximated to linear waveforms shown in Fig. 3. Turn-off losses are derived in a manner similar to loss derivation for PMOS turn-on. During PMOS turn-off, from Fig. 3 I d and V sd can be written as I d = I p + (I p I x )t t off (8) V sd = (V in + V f )t t off (9) P I VOF F = (V in + V f )(I p + 2I x )t off F sw 6 (10) I x = I p 2 Q t off, (11) where Q is the amount of change in the charge stored in the drain junction capacitance (C db ) of PMOS transistor. Q is calculated from the time PMOS transistor starts switching till onset of body diode conduction. Considering the model demonstrated in Fig. 3, only a few parameters need to be extracted for a given CMOS technology. Q rr and V f are transistor characteristics which can be easily obtained by transistor level simulations. For example for 0.35 µm CMOS processvaluesof Q rr and V f are obtainedto be88 pc and 0.61 V, respectively. I p is (I o + i) and I b is (I o i) where i is the inductor current ripple which is one of the design specifications. For the calculation of switching losses as stated earlier we need to know the switching times. The model for t on and t off proposed in this paper is based on principle of charge transfer. B. Turn-on time In this section we estimate the turn-on time of the switches based on generic charge transfer approach. For a switch driven by series of standard tapered inverters, the gate current (Fig. 2 and Fig. 5) can be approximated by a triangular waveform as shown in Fig. 3. For a switch driven by a constant current C. Turn-off time t on = 2C gv in I gpeak. (13) During turn off, the channel stops as the gate voltage rises above V in + V tp. However, it takes time for the large C db to charge to V in + V tp. This is shown in Fig. 3, where drain current of PMOS is nonzero even when the gate voltage has charged to V in. Therefore turn-off time, t off is mainly dependent on C db rather than C g. By applying principle of charge transfer, the net charge transferred can be expressed as: Q off Q on = 1 2 I pt off (14) Q on = C dbon I p R on (15) Q off = C dboff (V in + V f ) (16) t off = 2( Q off Q on I p ). (17) In Eq. (15) R on is the channel resistance of PMOS switch. Values of C db used to calculate the net transferred charge are evaluated at two extreme points namely when PMOS is ON (V sd = I d R on ) and when PMOS is off (V sd = V in + V tp ). III. VERIFICATION OF THE MODEL To verify the proposed model at different conditions, a CMOS buck converter was designed in 0.35 µm Mixed-Mode TSMC process as reference. The converter was then simulated using CADENCE Spectre simulator for different values of input voltage and load. The proposed model was implemented in MATLAB. The transistor switches and the tapered buffers used as driver were implemented using I/O devices available in 0.35 µm Mixed Mode TSMC process. Aspect ratio for PMOS was and that for NMOS was The specifications of the designed buck converter are shown in Table. I. The model proposed is verified over the entire load current and input voltage range specified in Table. I. To demonstrate validity of the model, figures 2, 5, 6, 7, 8 and 9 illustrate Spectre simulation results at different values of input voltage and load current. As shown in the figures turn-on and turnoff times from Eq. (13) and Eq. (17) match the corresponding values from Spectre simulations. Comparison of modeled and simulated switching times and I-V overlap losses is presented in tables II and III. Table IV compares the modeled and

5 TABLE I SYNCHRONOUS BUCK CONVERTER SPECIFICATIONS Technology 0.35 micron CMOS Switching frequency(f sw) 1 MHz V in 2.8 V-5 V Output Voltage(V o) 1.8 V Output current(i o) 65 ma-200 ma Filter Inductance 10 µh Filter Capacitance 22 µf Fig. 7. Simulated waveforms during PMOS turn-off at Vin = 3.3 V and Io = 100 ma. t off from simulation : 1.3 ns and that from model : 1.32 ns. Fig. 6. Simulated waveforms during PMOS turn-on at Vin = 3.3 V and Io = 100 ma. t on from simulation : 0.5 ns and that from model : 0.51 ns. simulated losses in the body diode due to reverse recovery. The proposed model is able to predict both the switching times and losses with an accuracy of ±10 %. IV. APPLICATION OF THE MODEL FOR OPTIMIZATION As the model provides fairly accurate estimates of losses and switching times, it can be utilized to derive and optimize the parameters like transistor widths, dead time and frequency over the defined input voltage and load current range. The MATLAB implementation of the model was used to study the variation in efficiency with switch sizes. Fig. 10 shows the variation of efficiency with switch sizing at I o of 65mA. It is clear from the result that at a particular load and line condition, there exists a region of values of W P and W N where efficiency peaks and remains same for slight variations. Thus, designer can optimize the widths depending upon the extent of variations of optimum widths with load and line conditions. The optimum width decreases as input voltage increases. Also, since we are able to reliably predict the switching times at different load and line conditions, the dead time can be adjusted. For the designed converter, across the TABLE IV LOSSES IN BODY DIODE DUE TO REVERSE RECOVERY AT I o=100 MILLIAMPERES Vin 3.3 V 5 V Io (ma) Spectre Model (Eq. (7)) Spectre Model (Eq. (7)) Fig. 8. Simulated waveforms during PMOS turn-on at Vin = 5 V and Io = 100 ma. t on from simulation : 0.4 ns and that from model : 0.39 ns. entire range of input voltage and load current, maximum value of the switching time which happens during turn-off is 2 ns. V. CONCLUSION An analytical model for switching times and I-V overlap loss of PMOS transistor of an integrated synchronous CMOS buck converter is presented in this paper. Reverse recovery losses due to body diode of NMOS are quantified. The model is verified using CADENCE Spectre simulations. I/O devices in 0.35 µm Mixed Mode TSMC process are used for the design of buck converter. Chain of tapered buffers is used for the driver. The proposed model is able to predict both the switching times and losses with an accuracy of ±10 %, permitting the design space exploration for efficiency-oriented design of buck converters. The effect of switch sizes on efficiency of buck converter is explored with the proposed model. Optimum switch size for maximum efficiency is shown to decrease with increase in input voltage. Design also permits optimization of dead time to maximize the efficiency.

6 TABLE II SWITCHING TIME AND LOSSES AT I o=100 MILLIAMPERES V in t on (ns) t off (ns) Ponp (mw) Poffp (mw) vline Spectre Model (Eq. (13)) Spectre Model (Eq. (17)) Spectre Model (Eq. (6)) Spectre Model (Eq. (10)) 2.8 V V V TABLE III SWITCHING TIME AND LOSSES AT V in =5 V I o(ma) t on (ns) t off (ns) Ponp (mw) Poffp (mw) Spectre Model (Eq. (13)) Spectre Model (Eq. (17)) Spectre Model (Eq. (6)) Spectre Model (Eq. (10)) Fig. 9. Simulated waveforms during PMOS turn-off at Vin = 5 V and Io = 100 ma. t off from simulation : 1.5 ns and that from model : 1.45 ns. Fig. 10. Effect of switch sizes on efficiency. W P and W N denote the width (in mm) of PMOS and NMOS respectively. REFERENCES [1] R. W. Erickson and D. Maksimović, Fundamentals Of Power Electronics. Springer, 2nd ed., [2] A. Stratakos, S. Sanders, and R. Brodersen, A low-voltage CMOS DC-DC converter for a portable battery-operated system, IEEE Power Electronics Specialists Conference, pp vol.1, Jun Fig. 11. Effect of load and line conditions on efficiency. [3] S. Reynolds, A DC-DC converter for short-channel CMOS technologies, IEEE Journal of Solid-State Circuits, vol. 32, pp , Jan [4] V. Kursun, S. G. Narendra, V. K. De and E. G. Friedman, Efficiency Analysis of a High Frequency Buck Converter for On-Chip Integration with a Dual-VDD Microprocessor, Proc. of European Solid-State Circuits Conference, pp , September [5] B. Arbetter, R. Erickson, and D. Maksimovic, DC-DC converter design for battery-operated systems, IEEE Power Electronics Specialists Conference, vol. 1, pp , Jun [6] Z. Zhang, W. Eberle, Z. Yang, Y.-F. Liu, and P. Sen, Optimal Design of Resonant Gate Driver for Buck Converter Based on a New Analytical Loss Model, IEEE Trans. on Power Electronics, vol. 23, pp , March [7] University of California Berkeley, BSIM Homepage. bsim3/. [8] G. Villar, E. Alarcon, F. Guinjoan, and A. Poveda, Efficiency-oriented switching frequency tuning for a buck switching power converter, IEEE International Symposium on Circuits and Systems, ISCAS, vol. 3, pp , May [9] J. Klein, Synchromous Buck MOSFET Loss Calculations with Excel Model. Fairchild Semiconductor, April [10] Y. Katayama, M. Edo, T. Denta, T. Kawashima, and T. Ninomiya, Optimum design method of CMOS IC for DC-DC converter that integrates power stage MOSFETs, IEEE Power Electronics Specialists Conference, vol. 6, pp , June [11] W. Eberle, Z. Zhang, Y.-F. Liu, and P. Sen, A simple switching loss model for buck voltage regulators with current source drive, Power Electronics Specialists Conference, PESC IEEE, pp , June 2008.