A new Design of Ultra-Low-Voltage Ultra-Low- Power CMOS Miler Operational Tranceconductance Amplifier Using Particle Swarm Optimization Algorithm

Transcription

1 International Journal of Engineering and Technology sciences (IJETS) 2(3): ISSN Academic Research Online Publisher Research Article A new Design of Ultra-Low-Voltage Ultra-Low- Power CMOS Miler Operational Tranceconductance Amplifier Using Particle Swarm Optimization Algorithm Gholamreza Karimi a, *, Morteza Gholami a a Electrical Engineering Department, Faculty of Engineering, Razi University, Kermanshah,67149, Iran. * Corresponding author. Tel: ; address:ghkarimi@razi.ac.ir A b s t r a c t Keywords: Operational Transconductance Amplifier, CMOS, Particle Swarm Optimization (PSO). Accepted:20 May2014 This paper presents a novel technique to design and optimize an ultra-low-voltage, ultra-low power CMOS Miler (OTA) using Particle Swarm Optimization (PSO). Advantages of this design are very small occupied area by transistors and low power consumption compare to other circuits. The values of width of transistors are taken as design parameters and total transistors area is taken as cost function (CF) to be minimized by PSO. The used topology was gate driven and DC level shifter that all transistors work in weak inversion. The designed circuit has been simulated at 0.35-µm process technology. A comparison between the optimized and previous design has been presented. The PSO generated results such as CF, which is 3000 µm 2 compare to previous work that was 14500µm 2. The simulation result shows that the power consumption is only 330nW and Unit gain frequency ) is eight times bigger than the previous designs while having a compact size and power supply of 0.5V. Academic Research Online Publisher. All rights reserved. 1. Introduction Today designing of circuit tends to low-voltage and consumes less power. But this approach needs to devote other specifications. On the other hand the size of circuit is crucial approach for designer. So finding trade-off between these situations is challenging work. In designing process some specifications like as power supply voltage, the frequency response and consumption must be considered [1-3]. Another problem is threshold voltage which depends on technology of circuit manufacturing and this cause some limitations in low voltage applications. On the other hand when the circuit operates in lower power supply, the speed of Circuit has been reduced. That means it works in lower frequency. The first step to design a low-voltage circuit is having sufficient knowledge about low-voltage topologies which are listed below:

2 1) The folded cascade Opamp used for moderately low supply voltages. Disadvantages are: some extra current, performance Limitation in sub 1V applications, 2) limited input common mode voltage. The complimentary input stage leads to increase the input common mode voltage range, but this topology needs more transistors and current. However, it is susceptible to a dead-zone, where neither NMOS nor PMOS differential pairs are in the active region. 3) The floating gate (FG) CMOS input stage has a rail-to-rail input common mode voltage range, at the price of limited low frequency applications and large die area. 4) The Bulk driven amplifier input stage has a rail-to-rail input common mode voltage range and substantial gain, but disadvantages are extra power dissipation and a large bulk bias dependent input capacitor [4]. Gate driven topology and DC level shifter were used in this study. All transistors work in weak inversion with folded cascaded structure. One of the disadvantages of operation transistor in weak inversion is low, and when the bulk driven topology was used, the problem became worse. Thus, designer must consider more limitations. In order to deal with these problems, we eliminate bulk driven topology and alternate gate driven instead. In practice, circuit design is governed by the design parameters so which most of these parameters trade with each other and this makes the design a multi- dimensional optimization problem. Therefore, choosing the optimized value of design parameters (transistors sizing), to fine-tune the design, is a challenging, very time-consuming and unexciting, depending on experience and intuition of designer s skill. As a result, to achieve a high performance circuits, optimizing the sizes of the analogue components is an crucial issue.in process of CMOS circuit designing W/L ratios (channel length L, channel width W) are parameters which are selected to get desire specification and satisfy constrains. When circuit complexity increases, the designer face larger variation of parameters to optimize and this makes the choosing of size of transistors harder. The design parameters, as mentioned above, form the design space which is to be explored in order to obtain an optimal solution point. In order to overcome this problem we use two procedures: first step is defining constrains and earning rang of transistors size that provides all defined limitations. Then using Particle Swarm Optimization to get final aim.the final aim is total space occupied by transistors. Particle swarm optimization (PSO) is a population based stochastic optimization technique developed by Eberhart and Kennedy in 1995, inspired by social behavior of bird flocking or fish schooling [9]. In this paper, section 2 presents the PSO algorithm; section 3 explains the designed OTA. The design of the OTA circuit using PSO is discussed in Section 4. Section 5 provides simulation result and conclusion is drawn in Section Particle Swarm Optimization Particle swarm optimization (PSO) was originally designed and introduced by Eberhart and Kennedy [9]. PSO has a successful performance in solving many optimization problems [16-18]. Particle swarm optimization (PSO) algorithm is a population based algorithm for finding the optimal solution. 269 P a g e

3 Owing to its implementation simplicity and fewer adjustable parameters than the other global optimization algorithms, PSO is an efficient approach to solving complex and large-scale problems. Therefore, the PSO has been developed through simulation of simplified social models. The method is based on researches about swarms such as fish schooling and a flock of birds, where it is based on a simple concept. Consequently, the required computation time is short, and it requires few memories. A vector in multi-dimensional search space represents each individual within the swarm. A vector, which determines the next movement of the particle, is assigned to the previous mentioned vector and is called the velocity vector. The process to update the velocity of a particle is determined by PSO. The velocity of each particle updates based on the current velocity, global best position explored by swarm and the best position which it has explored so far [7-8]. PSO needs simple mathematical operators which are, plus, minus and multiply. The searching space is D-dimensional, so works on a population of solution candidates referred to as particles. The size of the swarm is the total number of particles. Any particle has a position and a velocity. The movement of the particles is controlled by updating the position and velocity vectors in an effort to find an optimum solution. N is number of particles, initially position value of each particle is chosen randomly. The position vector of the i th particle with feature number D is defined as [5]: [ ] And the velocity vector is defined as: [ ] For each iteration, the velocity and position vectors of the i th particle in the search space are updated as follows [7]: ( ) ( ) Figure1 shows PSO Flow Chart [6]: Where d=1,2,,d, and i=1,2,,n. D is number of particle and K is number of iteration [9]. The constants, termed as cognition and social components, respectively, are the acceleration constants which changes the velocity of a particle towards pbest and gbest. The velocities of the particles determine the tension in the swarm. A swarm of particles can be used locally or globally in a search space. In the local version of the PSO, gbest is replaced with pbest and the entire process is the same [10]. rand 1 and rand 2 are random number between zero and one. W is inertia weight. 270 P a g e

4 Start Initialize particles with random position and velocity vectors. Loop until all particles exhaust For each particle's position(p) evaluate fitness If fitness (p) better than fitness (p best) than p best=p Set best of p bests as c Best Loop until max iteration Update particles velocity (1) and position (2) Stop, giving c Best, optimal solution Fig. 1: Flowchart of the general PSO algorithm. 3. OTA with DC Shifter Structure As mentioned as, CMOS technology continues to evolve; the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant, making matters worse. This trends in reducing the supply voltage means that analog designers face challenges such as reduced input common mode range, output swing and linearity[4].the IC design is more experimental and less systematic and selection topology depend on circuit application. Operation region of transistor is weak inversion via folded cascade topology. The operational transconduntance amplifier (OTA) which we chose for optimizing and increasing performance have some specification that will be expressed below. The drain current equation in the sub threshold region can be expressed as [10,11],when refer to(4), where is the characteristic current and the parameter is the thermal voltage and is given by, that in room temperature is about 26mV. The parameter n is the sub-threshold swing parameter. All 271 P a g e

5 these parameters can be obtained by using he models EKV [3], BSIM3v3 [12], and ACM [13] are given as follows: ( ) ( ) [ ] (5) If V DS >3 the transistor works in saturation region [3].For the weak inversion region, the trancoductance g m is again obtained by taking the derivation of versus in (4). (6) Fig.2: Composite transistor: (a) schematic and (b) symbol. Another characterization of this OTA is the composite transistor [14]. This component is important in weak inversion application, which is illustrated in Figure 2. Both transistors are implemented in individual wells, thus the body effect terminated [14]. According to figure 2, we could conclude that the current and voltage are defended as (6) and (7) equations, as given by [3].The is given by (8). Expression (8) shows that does not depend on V GS and this is advantage of composite transistor. Figure 3 shows final circuit which used for optimizing. In this circuit V DD is defined as (9) refer to [14]. is less than threshold voltage and V DD can be less than PMOS threshold voltage. = = - (7) (8) ( ) (9) V DDmin V GS1 +V DS5(SAT) (10) In previous work the used topology was bulk driven. In order to improve performance of the circuit, we alternated this topology and used gate driven topology instead. This approach leads to higher because of increasing in transconductance. As it is known depend on 272 P a g e

6 transconductance of input pairs transistor. So consequence of increasing transconductance ( instead ) is higher. varies from 20% to 30% of for the same transistor in a CMOS process [2]. VDD Q10 Q5 Q8 Q9 Q7 Vin- Q2 Q1 Vin+ Cc Vout Iref Q3b Q4b Qc Q3a Q4a Q Fig.3: Improved Miller OTA circuit using common gate as DC shifting 4. Design OTA Using PSO To optimize and increase performance of the proposed OTA, two steps were done. At the first step, constrains were defined and all W/L ratios that provides all defined limitations were obtained. There are three types of constrains. One type is elementary definition and limitation that are listed in (10), another type is second constrains that are listed in(11) and last constrain is according to composite transistors overdrive voltage equation which is expressed in (12) as referred to[8]. At beginning we split elementary types to 1000 parts and then extract corresponding W/L ratios. To obtain the dimensions of the transistors and elements, we used Laker and Sansen method. [ ] [ ] ( ) ( ) ( ) ( ) ( ) 13) 273 P a g e

7 Another step is considering second constrains and eliminating extracted W/L ratios that don t satisfy these constrains. After that we specify max and min range of W/L ratios and use them as parameters in PSO and finally define CF as desired aim for PSO and obtain optimized size of transistors. The technology that is used in simulation is 0.35µm model parameter and use of BSIM3v3 (Y. Cheng and C. Hu1999) model to extract current parameter. The PSO is implemented by MATLAB Software.The vector size in first step was 1000*6 and for PSO algorithm was 5*5. Particle vector parameter for each step is expressed in (10) and (11). Where is slew rate (V/µs), is compensation capacitor, is unity gain bandwide, is power consumption. Update parameter, are chosen 1.7. was selected as 4pF and is 15pF.Numbers of iteration was 100. CF is total transistors size expressed as: (14) T is defined as total number of transistors.the target value CF is aimed to be smaller than 3000µm 2. All MOSFET length (L) values are chosen as 2µm.The proposed specifications and constrains of circuit are: <350nW- >80dB >100KH < < P.M( Phase margin) >55º V DD =0.5V 3<W/L<400 The design procedure is expressed in the flowchart as shown in Figure Simulation Result and Comparison The designed circuit has been simulated using HSPICE A at 0.35-µm process technology. PSO achieves to our aim after 50 epochs. Laker and Sansen [1] method was used to obtain the size of the transistors for the Miller OTA. Using this method, it is possible to calculate the dimensions of the transistors and elements. The power supply was chosen 500 mv. The simulation showed that the circuit closely follows calculated results by the algorithm. Table1 summarizes the comparison results between optimized and previous design. According to simulation result, the power consumption is 330nW, is 110KH and is 87dB. We used a transistor (Q C ) instead of R C and it leads to higher.the optimum sizes of transistors which were obtained by PSO are listed in Table1. Table2 expresses 274 P a g e

8 and compares specifications of optimized and previous design. Total occupied area by transistors in the same work was µm 2 and in this work is 3000 µm 2. (a) Fig.4: Flowchart of the design procedure. (b) Fig.5: (a) Input voltage (b) Output voltage The design scheme results less power consumption and higher compares with previous work. Input and output signals are shown in Figure 5. The input is a 38KHz sinusoidal signal of 100mV amplitude. Figure 6 presents the measured slew rate for a power supply of 500 mv. The design scheme results less power consumption and higher compares with previous work. Input and output signals are shown in Figure 5. The input is a 38KHz sinusoidal signal of 100mV amplitude. Figure 6 presents the measured slew rate for a power supply of 500 mv. 275 P a g e

9 Table 1: OTA parameters obtained by PSO and previous work Designed parameters I ref [8] 130nA This work 60nA (W/L) 1,2 (250µm/1µm) (114µm/2µm) (W/L) 3a, 4a (100µm/1µm) (34µm/2µm) (W/L) 3b,4b (400µm/1µm) (200µm/2µm) (W/L) 5 (200µm/9µm) (102µm/2µm) (W/L) 6 (400µm/9µm) 186µm/2µm) (W/L) 7 (W/L) 8,9 (800µm /9µm) (100µm /9µm) (382µm/2µm) (25µm/2µm) Fig.6: Slew-rate of optimized Miler OTA by PSO at 500-mV power supply. (W/L) 10 (200µm /9µm) (51µm/2µm) (W/L) C -- ((17µm/2µm) Table 2: Comparison between this work and previous works Parameters This work [8] [11] CMOS technology 0.35µm 0.35µm 0.25µm Power supply 0.5V 0.6V 0.9V Unit gain frequency 110KHz 13.02kHz 5.7KHz Signal swing 0 to 0.44V 0 to 0. 6V 0.01to 0.89V Open loop gain 87dB 73.5dB B 70dB Phase margin 60º 54º 62º Slew Rate V/µs V/ µs - Power consumption 330nW 550nW 450nW Cost Function (CF) 3000 µm µm 2-6. Conclusion This paper showed the application of particle swarm optimization (PSO) to size analog circuits. Advantages of this design are very small occupied area by transistors and low power consumption compare to other circuits. Topology is capable of running on a 500-mV power supply voltage and a power consumption of just 330nW, in a 0.35-µm n-well CMOS process. The threshold voltages for p- MOS transistors are 680 mv and 500 mv for n-mos transistors. 276 P a g e

10 The used design parameters were channel width of the transistors.in addition, we used a novel technique to guaranty all W/L ratios before use of PSO algorithm.the advantage of the optimized design procedure has also been demonstrated through results. Specifications of circuit improved using PSO algorithm especially total transistors area were chosen as cost function for PSO. In order to validate the procedure, the circuit has been implemented and simulated with HSPICE.A comparison with the previous work has been presented. PSO based on design scheme achieves all the design specifications and minimized cost function (CF). REFRENCES [1] R. Laker, W. M. C. Sansen.. Design of Analog Integrated Circuits and Systems. New York: McGraw Hill 1994; 898. [2] P. E. Allen, D. R. Holberg. CMOS Analog Circuits Design, 2nd ed. Oxford, U.K. Oxford University Press 2002; 784. [3] E. A. Vittoz, J. Fellrath. CMOS analog integrated circuits based on weak inversion operation, IEEE J. Solid-State Circuits 1977; 12(3): [4] Eliyahu Zamir. Low Voltage Standard CMOS Opamp Design Techniques. Technical report, 2002; [5] Revna Acar Vural, Ozan Der, TulayYildirim, Investigation of particle swarm optimization for switching characterization of inverter design.elsevier expert systems with application 2011; 38(5): [6] Joyjit Mukhopadhyay, Soumya andit. Modeling and Design of Nano scale CMOS Inverter for Symmetric Switching Characteristic. Vlsi Design Journal, 2012, ( 2012); [7] Clerc. M. The Particle. Swarm-Explosion. Stability and Convergence in a Multi-Dimensional Complex Space. IEEE transaction on Evolutionary Computation Journal, 2002, 6(1): [8] Luís H. C. Ferreira, Tales Cleber Pimentar, and Robson L. Moreno. An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input / Output Swing.IEEE Transaction on circuits and systems 2007; 54(10): [9] J. Kennedy, R. C. Eberhart. Particle swarm,optimization Proc. IEEE Int. Conf. on Neural Networks 1995; [10] B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, Designing 1V op amps using standard digital CMOS technology, IEEE Transaction. Circuits Systems.II, Analog Digit. Signal Process 1998; 45(7): [11] T. Stockstad, H. Yoshizawa. A 0.9 V 0.5A rail-to-rail CMOS operational amplifier, IEEE Journal on Solid-State Circuits 2002; 37(3): [12] Y. Cheng and C. Hu. MOSFET Modeling & BSIM3 User s Guide.Norwell, MA: Kluwer. 1999; P a g e

11 [13] A. I. A. Cunha, M. C. Schneider, andc. Galup-Montoro. An MOS transistor model for analog circuit design, IEEE Journal of Solid-State Circuits 1998; 33(10): [14] L. H. C. Ferreira, T. C. Pimenta, A weak inversion composite MOS transistor for ultra-lowvoltage and ultra-low-power applications, In Proc. 13 th Int. Conf.on Mixed Design Integrated. Circuits Systems, Gdynia, Poland 2006; [15] T. Stockstad, H. Yoshizawa, A 0.9 V 0.5.A rail-to- rail CMOS operational amplifier, IEEE Journal. of Solid-State Circuits. 2002; 37(3): [16] C. A. CoelloCoello, et al. Handling multiple objectives with particle swarm optimization, IEEE Transaction. on Evolutionary Computation 2004; 8(3): [17] Gh. Karimi, S. Haghiri. A high gain CMOS low noise amplifier for 3.6GHz applications using current-reused topology and noise canceling technique, International Journal of Engineering & Technology Sciences (IJETS) 2014; 2 (2): [18] M. M. Karkhanehchi, S.Naderi, F.Jafari, S.Majidifar. Design and Optimization of a Very Low Noise Amplifier using Particle Swarm Optimization Technique, International Journal of Engineering & Technology Sciences (IJETS), 2014; 2 (2): P a g e