IRDC3146EVAL IRU3146 EVALUATION BOARD USER GUIDE. INPUT/OUTPUT CONNECTIONS The following is the input/output connections: Dual Outputs.

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1 DCEVAL U EVALUATION OARD USER GUIDE INTRODUCTION The U IC is a Dual synchronous uck controller, providing a cost-effective, high performance and flexible solution. The U can be configured as a -independent or as a -phase controller. The -phase configuration is ideal for high current applications. The U features 80 out of phase operation which reduces the required input/output capacitance and results in a fewer number of capacitors needed. Other key features offered by this device include two independent programmable soft starts, programmable switching frequency up to 00KHz per phase, Hiccup current limit and an under voltage lockout function. The current limit is provided by sensing the lower MOSFET's on-resistance for optimum cost and performance. SPECIFICATION DATA This reference board is designed to demonstrate all the features of U and can be configured to two types of applications: ) Dual outputs application (Independent Outputs) ) -phase application (Single Output) This user guide contains the schematic and bill of materials for each of these applications, and the design guidelines are described in data sheet. The MOSFETs sockets on the evaluation board are dual layout for SOIC-8 and Direct FET footprint. INPUT/OUTPUT CONNECTIONS The following is the input/output connections: Inputs: JP: Vin and Gnd JU: and Gnd JU5: VCL/VCH/VCH Outputs: JP: Vout for Dual output JP5: Vout for Dual output JP: Vout for -phase application Scope Probe connections: J and J: Inductor point for L and L J and J: Outputs for Vout and Vout The connection points for dual output application are shown in Figure. Connect the power supply cables according to this figure, minimizing wire lengths to reduce losses in the wire. Test points J, J, J and J provide easy connection for oscilloscope voltage probe to monitor the inductor points for each PWM section and output voltages. Dual Outputs VIN = V VOUT =.5V IOUT = 0A VOUT =.8V IOUT = 0A VOUT = 50mV FS = 00KHz -Phase VIN = V VOUT =.8V IOUT = 5A VOUT = 50mV FS = 00KHz Rev..0 7/8/0

2 DCEVAL CONNECTION DIAGRAM Power Supply V LOAD 0-0A LOAD 0-0A Figure - Connection diagram of evaluation-board for U in Dual output configuration Rev..0 7/8/0

3 DCEVAL LAYOUT The PC is -layers FR board, the top layer is dedicated for power components, with two parallel control MOSFETs and two parallel Synchronous MOSFETs. These MOSFETs are dual layout for both SOIC-8 and DirectFET footprint. The input capacitors are all located close to MOSFETs. The two output inductors are located closed to MOSFETs and are symmetrical to the output connector for more accurate current sharing result. The two mid-layers are dedicated for Analog and Power ground, these two grounds are kept separated from each other and they are connected at a single point as shown in Figure. All the decoupling capacitors, charge pump capacitor and feedback components are located close to the IC. The feedback resistors are tied to the output voltage at the point of regulation. Figure - Top layer of evaluation-board for U. Rev..0 7/8/0

4 DCEVAL Figure - Mid layer of evaluation-board for U. Rev..0 7/8/0

5 5 A C D 5 D C A Title Number Revision Size Date: 8-Jul-00 Sheet of File: C:\Old_Drv\pcb\PC_last.ddb Drawn y: R R R C7 Q C C9 R7 C D VP VREF 7 GND 8 VSNS 5 VOUT PGOOD HICCUP 5 SYNC OCSET 9 F RT VSNS F COMP 7 SS 8 COMP VCH 0 DH PGND DL VCL DL 5 PGND DH 7 VCH 8 OCSET 9 SS 0 U U C8 C7 C8 C Q L JP C C0 R8 R R R5 C C C C5 R R Q R C R C9 R5 D AT5A R V GND R7 R8 R9 R0 R CA x C R7 R9 R8 Q Q5 Q L R C C R0 C8A C5 R U R R C R R5 R VDDQ F VP CA C0 VCL HICCUP Comp Comp RT SS SS SYNC PGOOD OCSET DH OCSET DL VP VREF F VOUT VOUT VDDQ R9 R0 JU JP PGND VOUT JP VOUT VOUT JP5 PGND VOUT R R F F DL DH VCH VOUT V N00 C7A N0 N0 N0 N50 Qgate QQgate N90 N00 Q5Qgate N50 N75 Qgate N0 N5 N5 N5 R5 JU D AT5A C7 C7C C7D C7E C8 C8C C8D C8E CD CC C C CC CD R R8 R7 JU5 N00 Q7 Q8 R9 R0 Q7gate Q8gate J J C uf J C uf J Q0 Q9 VSNS F VDDQ VSNS JU C5 R R C R R VOUT VSNS VSNS R5 C7F C8F CE CE General Schematic

6 5 A C D 5 D C A Title Number Revision Size Date: 8-Jul-00 Sheet of File: C:\Old_Drv\pcb\PC_last.ddb Drawn y: R R C7 Q C9 D VP VREF 7 GND 8 VSNS 5 VOUT PGOOD HICCUP 5 SYNC OCSET 9 F RT VSNS F COMP 7 SS 8 COMP VCH 0 HDrv PGND LDrv VCL LDrv 5 PGND HDrv 7 VCH 8 OCSET 9 SS 0 U U C8 C7 C8 C Q L JP C C0 R8 R R R5 C C C C5 C9 D AT5A V GND R8 R9 R0 CA x R7 R9 Q Q5 L C C8A U R R F CA C0 VCL Comp Comp RT SS SS SYNC PGOOD OCSET HDrv OCSET LDrv VP F VOUT VDDQ JU JP PGND VOUT JP5 PGND VOUT LDrv HDrv VCH VOUT V N00 C7A N0 N0 N50 Qgate QQgate Q5Qgate Qgate N5 N5 JU D AT5A C7 C7C C8 C8C CC C C CC CD J J C uf J C uf J F VSNS JU C5 R R C R R VOUT VSNS VSNS R5 CE Dual Outputs VSNS R

7 ILL OF MATERIAL For Dual Output Application, Vin=V, DCEVAL Ref Desig Description Value Qty Part# Manuf Q,Q Q,Q5 U D D,D L,L CA-E, CA-C C7-D, C8D-F MOSFET MOSFET Controller Diode Diode Inductor Cap,Poscap Cap,Poscap 0V,mOhm 0V, mohm Synchronous PWM Fast Switching Fast Switching.5µH,A,.9mΩ 7µF, V 0µF,.V,0mΩ 8 F78 F8 U AT5S AT5A ETQPFR5FA TPQC7M TP0M Sanyo Sanyo C,C5,C C7,C8 C,C,C5,C,C7,C8,C9,C0,C C C Cap,Ceramic 0.µF, Y5V, 5V Cap.Ceramic µf, X7R, 5V Cap,Ceramic µf, Y5V, V Cap,Ceramic 0nF, X7R, 50V Cap,Ceramic 5nF, X7R, 50V 9 ECJ-VFE0Z ECJ-YE05K ECJ-VFC05Z ECJ-VH0K ECJ-VH5K R R5 R8 R,R9 R7,R R9,R,R,R R,R R5 R R,,7,0,,,5,8,0,5 5.5KΩ.9K K 5.K, %.5K, % kω, %.K,% 50k,% 00Ω Short, 0Ω 0 Any R,,9,,9,,,7,0,,,,,8, Open R,7,8,5,,0 C,,CA,CC-E, C7E-F,C8A-D, C9,C0,,,,,5, Q,Q,Q7,Q8,Q9,Q0 J,J,J,J JP,JP,JP5 JU,JU,JU,JU5 umpon Capacitor Capacitor Transistor Scope Probe Terminal Jumper Open Open Open Open -Pos terminal ED97-ND S0-0-ND SJ-7A lack Tektronix Digi-Key Digi-Key M Rev..0 7/8/0 7

8 DCEVAL TYPICAL OPERATING WAVEFORMS Figure -.5V Switching Waveforms at no Load Figure 5-.5V Switching Waveforms at 0A Load Rev /8/0

9 DCEVAL Figure -.8V Switching Waveforms at no Load Figure 7-.8V Switching Waveforms at 0A Load Rev..0 7/8/0 9

10 DCEVAL Figure 8- Power Up Waveforms Figure 9- Power Up Waveforms (Internal Regulator) Rev /8/0

11 DCEVAL Figure 9- Shut Down, SS pulls Low Figure 0- Shut Down, SS pulls Low Rev..0 7/8/0

12 DCEVAL Figure - Short Circuit Condition (Hiccup Mode) for.5v Output Figure - Short Circuit Condition (Hiccup Mode) for.8v Output Rev..0 7/8/0

13 DCEVAL Figure - Load Transient Response Step Load for.5v (0-0A) Step Load for.8v (0-7A) F78/8_V_.8V_.5V_0_5A Room Temp % Efficiency V out.5v out Iout Figure - Efficiency for.5v and.8v outputs at room temperature no air flow. 7A Rev..0 7/8/0

14 5 A C D 5 D C A Title Number Revision Size Date: 8-Jul-00 Sheet of File: C:\Old_Drv\pcb\PC_last.ddb Drawn y: R R C7 Q C C9 C D VP VREF 7 GND 8 VSNS 5 VOUT PGOOD HICCUP 5 SYNC OCSET 9 F RT VSNS F COMP 7 SS 8 COMP VCH 0 HDrv PGND LDrv VCL LDrv 5 PGND HDrv 7 VCH 8 OCSET 9 SS 0 U U C8 C7 C8 C Q L JP C C0 R8 R R R5 C C C C5 R C D AT5A V GND R8 R9 R0 CA x R7 R9 Q Q5 L R C C C8A U CA C0 VCL Comp Comp RT SS SS SYNC PGOOD OCSET HDrv OCSET LDrv VP VREF F VOUT VOUT VDDQ JU JP PGND VOUT JP VOUT VOUT JP5 PGND VOUT LDrv HDrv VCH VOUT V N00 C7A N0 N0 N50 Qgate QQgate N00 Q5Qgate Qgate N5 N5 JU D AT5A C7 C7C C7D C7E C8 C8C C8D C8E CD CC C C CC CD J J C uf J C uf J F VDDQ VSNS JU C5 R R VSNS R5 CE CE -Phase, Single Output R

15 DCEVAL ILL OF MATERIAL For -Phase Application, Vin=V, Ref Desig Description Value Qty Part# Manuf Q,Q Q,Q5 U D D,D L,L C,C,CA-E, CA-E C7A-E, C8A-E C,C C7,C8 DirectFET DirectFET Controller Diode Diode Inductor Cap, Poscap Cap, Ceramic Cap, Ceramic Cap, Ceramic 0V,9mOhm 0V,mOhm Synchronous PWM Fast Switching Fast Switching 0.8µH,7A,.5mΩ 7µF, V 0µF,.V,0mOhm 0.µF, Y5V, 5V µf, X7R, 5V 0 F7 F8 U AT5S AT5A ETQPHROFA TPQC7M TP0M ECJ-VFE0Z ECJ-YE05K Sanyo Sanyo C,C,C5,C7,C8,C9,C0,C,C,C Cap, Ceramic µf, Y5V, V 0 ECJ-VFC05Z C0,C C,C R R5 R8 R,R9 R,R,R9,R R7,R R R,,7,,,8,0,5,0,,7, Cap, Ceramic Cap, Ceramic 00pF, X7R, 50V 5nF, X7R, 50V 5.K,%.8K,% K,% 5K, % K, %.K, % 00Ω Short, 0Ω ECJ-VCH00J ECU-VH5KG R,,7,8,9,5,,,8,,,0,,, Open 5 R,R,R9,R0,R5 C9,,5,,,9 C5 Q9,Q0 J,J,J,J JP,JP JU,JU,JU,JU,JU5 Capacitor Capacitor Transistor Scope Probe Terminal Jumper Open Open Short Open -Pos terminal ED97-ND S0-0-ND Tektronix Digi-Key Digi-Key Rev..0 7/8/0 WORLD HEADQUARTERS: Kansas St., El Segundo, California 905, USA Tel: (0) TAC Fax: (0) Visit us at for sales contact information Data and specifications subject to change without notice. 0/0 5