LY8271A 16Wx2(BTL) Stereo / 20Wx1(PBTL) Mono Class D Audio Amplifier With Built-in Step-up Converter

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1 FEATURES GENERAL DESCRIPTION Operation Voltage:.9V ~ V power supply. Adjustable boost converter output up to 4V. Differential or Single-end inputs. kinds of output type options: xbtl xpbtl mode. Output power capability: boost tov, 5 ) RLoad 4Ω 8Ω BTLx PBTL 6Wx/ THD+N=0% 0Wx/ THD+N=0% 0Wx/ THD+N=0% boost to 8V, 5 ) RLoad 4Ω 8Ω 8.5Wx/ 4.5Wx/ BTLx THD+N=0% THD+N=0% 8.5Wx/ PBTL -- THD+N=0% Short-Circuit protection with auto recovery. Over-Heat protection with auto recovery. Under voltage detection and Over voltage protection. Output DC detection for speaker protection. Internal oscillator. Filter-free operation. Power ON/OFF pop reduction. Green package available. 8-pin TSSOP 73mil package. (with thermal pad). -- The is a high efficiency class D audio power amplifier with built-in boost DC-DC converter. It can to work either in dual bridge PBTL mono application configuration. The device use advanced EMI suppression technology enables the use low cost ferrite-bead filters at the outputs while meeting EMC requirements. The outputs are also fully protected against short to PVDD or GND or output-to-output pin. The short-circuit protection and thermal protection include an auto-recovery feature. The device features a low noise and a low power consumption in shutdown mode. It also utilizes circuitry to reduce low noise during device turn-on. The device s output DC detection also prevents speaker damage from long-time current stress. APPLICATION Portable Media. Blue-tooth Speakers. Audio Docking system. Consumer Audio Equipment. PIN CONFIGURATION TSSOP8 pin configuration (TOP VIEW)

2 PIN DESCRIPTION SYMBOL Pin No. DESCRIPTION OUTNL Speaker output for Negative(-) L channel. PGND,4,5,7 Power switch ground pin. OUTPL 3 Speaker output for Positive(+) L channel. BSTPL 4 Bootstrap I/O for Positive(+) L channel. PVCCL 5 High-voltage power supply for left-channel. (right channel and left channel power supply inputs are connect internal.) BSTNL 6 Bootstrap I/O for Negative(-) L channel. SD 7 Shutdown signal for Device. (low = disabled, high = operational). Voltage compliance to AVCC. LINP 8 Positive(+) L channel audio input. LINN 9 Negative(-) L channel audio input. AVCC 0 Analog power supply. FB Receives the feedback voltage from an external resistive divider across the output. SW Must be connected an Inductor from VIN pin to SW pin for boost and rectifying switches. AGND 3 Analog ground pin. VCC 6 Use ceramic capacitor of more than.uf to GND. VIN 7 Must be closely decoupled to GND pin with 470uF or greater ceramic capacitor. EN 8 Boost enable pin (high=enable; low=disable). GVDD 9 5V regulated output. RINN 0 Negative(-) R channel audio input. RINP Positive(+) R channel audio input. PBTL Parallel BTL mode switch, voltage compliance to AVCC. (high for parallel BTL output.) BSTNR 3 Bootstrap I/O for Negative(-) R channel. PVCCR 4 High-voltage power supply for right-channel. (right channel and left channel power supply inputs are connect internal.) BSTPR 5 Bootstrap I/O for Positive(+) R channel. OUTPR 6 Speaker output for Positive(+) R channel. OUTNR 8 Speaker output for Negative(-) R channel. Thermal Pad Must be soldered to PCB s ground plane.

3 ORDERING INFORMATION Ordering Code Packing Type Tape& Reel Speaker Channels Stereo Pin/ Package TSSOP8 Output Power boost to V, 5 4Ω 8Ω 6Wx/ 0Wx/ THD+N=0% THD+N=0% 0Wx/ THD+N=0% boost to 8V, 5 4Ω 8.5Wx/ THD+N=0% 8.5Wx/ THD+N=0% 8Ω 4.5Wx/ <0% THD+N -- Input Type Single-End / Differential Output Type xbtl/ xpbtl APPLICATION CIRCUIT Figure. Application circuit for Stereo (BTL) mode and Single-Ended Input Note : These resistances must be connected to ground, resistance=kohm. 3

4 Figure. Application circuit for Mono (Parallel BTL) mode and Single-Ended Input Note : These resistances must be connected to ground, resistance=kohm. Note 3: Be noted that input should be applied on R-channel only for Mono application. 4

5 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. PARAMETER SYMBOL RATING UNIT Supply Voltage VIN 6 V PVCCL,PVCCR, AVCC (Class-D supply voltage) PVCC 6 V SD, PBTL pin Voltage 6 V EN, FB, VCC pin voltage 6 V Operating Temperature TA -40 to 85 (I grade) Storage Temperature TSTG -65 to 50 ESD Susceptibility VESD 000 V Junction Temperature TJMAX 50 Soldering Temperature (under 0 sec) TSOLDER 60 RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT Supply voltage VIN VIN.9 V Class-D supply voltage PVCC PVCCL, PVCCR, AVCC 5 4 V High-level input voltage VIH SD, PBTL, EN - V Low-level input voltage VIL SD, PBTL, EN V BOOST ELECTRICAL CHARACTERISTICS VIN=4.V, PVCC=8V, TA=5. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Input Supply Range VIN V Under Voltage Lockout VUVLO V UVLO Hysteresis V Operation Frequency FOSC VFB=0.5V khz Maximum Duty Cycle TDUTY % Reference Voltage VREF V Enable Boost Voltage VEN - - V Shutdown Voltage VSD V 5

6 ELECTRICAL CHARACTERISTICS (), VIN=4.V Condition: VIN=4.V, PVCC=8V, RL=8 (TA = 5 ). PARAMETER SYMBOL TEST CONDITION MIN. TYP. * MAX. UNIT Regulator output GVDD IGVDD=0.mA V Oscillator frequency fosc K Output offset voltage. VOS PVCC=8V VI=0V,(measured differential). -.5 mv Turn-on time ton SD=V ms Turn-off time toff SD=0.8V. - - us Quiescent Current IQ ma VIN=4.V, PVCC=8V. Shutdown Current ISD ua Thermal shutdown Shutdown temp TSD temperature Restore temp Supply ripple rejection Ksvr Vripple=00mVpp at k, Gain=0dB, inputs ac-grounded db Crosstalk Cs F=k, VO=Vrms, Gain=0dB db Output voltage noise Vn BTL mode, f=0 ~ 0k, Gain=0dB, a-weighted filter, RL= PBTL mode, f=0 ~ 0k, Gain=0dB, a-weighted filter, RL= uv BTL mode, Maximum output at THD+N<%, f=k, Gain=0dB, Signal-to-noise ratio SNR a-weighted. PBTL mode, Maximum output at db THD+N<%, f=k, Gain=0dB, a-weighted BTL mode, THD+N=%, f=k, PVCC=8V, RL= BTL mode, THD+N=0%, f=k, PVCC=8V, RL= Output power Po BTL mode, THD+N=%, f=k, PVCC=8V, RL=4. 7 BTL mode, THD+N=0%, f=k, PVCC=8V, RL= W PBTL mode, THD+N=%, f=k, PVCC=8V, RL=4-7 - PBTL mode, THD+N=0%, f=k, PVCC=8V, RL= BTL mode, PVCC=8V, RL=8 f=k, PO=3W Total harmonic distortion BTL mode, PVCC=8V, RL=4 f=k, THD+N + noise PO=5W % PBTL mode, PVCC=8V, RL=4 f=k, PO=6W (*) Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 5 6

7 TYPICAL PERFORMANCE CHARACTERISTICS, (VIN=4.V, PVCC=8V) Figure.3 THD + N (%) vs. Output power (VIN=4.V, PVCC=8V, BTL mode, RL=8Ω) RCH LCH % m 0m 50m 00m 00m 500m W Figure.4 THD + N (%) vs. Output power (VIN=4.V, PVCC=8V, BTL mode, RL=4Ω) RCH LCH % m 0m 50m 00m 00m 500m W Figure.5 THD + N (%) vs. Frequency (VIN=4.V, PVCC=8V, BTL mode, RL=8Ω) Po=W Po=W Po=3W % k k 5k 0k 0k 7

8 Figure.6 Crosstalk (VIN=4.V, PVCC=8V, BTL mode, RL=8Ω) TT TTTTTTT RCH LCH LCH RCH T d B k k 5k 0k 0k Figure.7 Noise (VIN=4.V, PVCC=8V, BTL mode, RL=8Ω) V 40u 30u 0u 0u 00u 90u 80u 70u 60u 50u 40u 30u 0u 0u RCH LCH k k 5k 0k 0k Figure.8 DR (VIN=4.V, PVCC=8V, BTL mode, RL=8Ω) d B V k 4k 6k 8k 0k k 4k 6k 8k 0k 8

9 Figure.9 Efficiency (Booster to PVCC=8V, BTL mode, RL=8Ω) Efficiency (%) Vin=3.7V 0 Vin=4.V Vin=5V Output Power (W)*CH Figure.0 THD + N (%) vs. Output power (VIN=4.V, PVCC=8V, PBTL mode, RL=4Ω) % m 0m 50m 00m 00m 500m W 60u Figure. Noise (VIN=4.V, PVCC=8V, PBTL mode, RL=4Ω) 40u 0u 00u V 80u 60u 40u 0u k k 5k 0k 0k 9

10 Figure. DR (VIN=4.V, PVCC=8V, PBTL mode, RL=4Ω) d B V k 4k 6k 8k 0k k 4k 6k 8k 0k Figure.3 Efficiency (Booster to PVCC=8V, PBTL mode, RL=4Ω) Efficiency (%) Vin=3.7V Vin=4.V Vin=5V Output Power (W)*CH 0

11 ELECTRICAL CHARACTERISTICS (), VIN=8.4V Condition: VIN=8.4V, PVCC=V, RL=8 (TA = 5 ). PARAMETER SYMBOL TEST CONDITION MIN. TYP. * MAX. UNIT BTL mode Quiescent Current IQ ma PBTL mode VIN=8.4V, PVCC=V BTL mode Shutdown Current ISD ua PBTL mode Supply ripple rejection Ksvr Vripple=00mVpp at k, Gain=0dB, inputs ac-grounded db Crosstalk Cs BTL mode, f=k, VO=Vrms, Gain=0dB db Output voltage noise Vn BTL mode, f=0 ~ 0k, Gain=0dB, a-weighted filter, RL= PBTL mode, f=0 ~ 0k, Gain=0dB, a-weighted filter, RL=8-9 - uv BTL mode, Maximum output at THD+N<%, f=k, Gain=0dB, Signal-to-noise ratio SNR a-weighted PBTL mode, Maximum output at db THD+N<%, f=k, Gain=0dB, a-weighted BTL mode, THD+N=%, f=k, PVCC=V, RL=8-8 - BTL mode, THD+N=0%, f=k, PVCC=V, RL=8-0 - Output power Po BTL mode, THD+N=%, f=k, PVCC=V, RL=4 3 BTL mode, THD+N=0%, f=k, PVCC=V, RL=4-6 - W PBTL mode, THD+N=%, f=k, PVCC=V, RL=4-6 - PBTL mode, THD+N=0%, f=k, PVCC=V, RL=4-0 - BTL mode, PVCC=V, RL=8 f=k, PO=5W Total harmonic distortion THD+N BTL mode, PVCC=V, RL=4 f=k, + noise PO=8W % PBTL mode, PVCC=V, RL=4 f=k, PO=0W (*) Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 5

12 TYPICAL PERFORMANCE CHARACTERISTICS, (VIN=8.4V, PVCC=V) Figure.4 THD + N (%) vs. Output power (VIN=8.4V, PVCC=V, BTL mode, RL=8Ω) RCH LCH % m 0m 50m 00m 00m 500m W Figure.5 THD + N (%) vs. Output power (VIN=8.4V, PVCC=V, BTL mode, RL=4Ω) RCH LCH % m 0m 50m 00m 00m 500m W Figure.6 THD + N (%) vs. Frequency (VIN=8.4V, PVCC=V, BTL mode, RL=8Ω) Po=W Po=3W Po=5W % k k 5k 0k 0k

13 Figure.7 Crosstalk (VIN=8.4V, PVCC=V, BTL mode, RL=8Ω) T TT RCH LCH LCH RCH d B k k 5k 0k 0k Figure.8 Noise (VIN=8.4V, PVCC=V, BTL mode, RL=8Ω) V 40u 30u 0u RCH LCH 0u 00u 90u 80u 70u 60u 50u 40u 30u 0u 0u k k 5k 0k 0k Figure.9 Efficiency (Booster to PVCC=V, BTL mode, RL=8Ω) Efficiency (%) Vin=6V 0 Vin=7.4V Vin=8.4V Output Power (W)*CH 3

14 Figure.0 THD + N (%) vs. Output power (VIN=8.4V, PVCC=V, PBTL mode, RL=4Ω) % m 0m 50m 00m 00m 500m W 40u 30u 0u 0u 00u 90u 80u Figure. Noise (VIN=8.4V, PVCC=V, PBTL mode, RL=4Ω) V 70u 60u 50u 40u 30u 0u 0u k k 5k 0k 0k Figure. DR (VIN=8.4V, PVCC=V, PBTL mode, RL=4Ω) d B V k 4k 6k 8k 0k k 4k 6k 8k 0k 4

15 APPLICATION INFORMATION Input Capacitors (Ci) The performance at low frequency (bass) is affected by the corner frequency (fc) of the high-pass filter composed of input resistor (Rin) and input capacitor (Cin), determined in equation (). Typically, a 0. F or F ceramic capacitor is suggested for Cin. The resistance of input resistors is different at different gain setting. Figure.3 f c π R in C in Shutdown Control Pulling SD pin low will let operate in low-current state for power conservation. The outputs will enter mute once SD pin is pulled low, and regulator will also disable to save power. If let SD pin floating, the chip will enter shutdown mode because of the internal pull low resistor. For the best power-off performance, place the chip in the shutdown mode in advance of removing the power supply. Thermal Protection The has a built-in over-heat protection circuit, it will turn off all power output when the chip temperature over 50, (There is a ±5 C tolerance on this trip point from device to device.) the chip will return to normal operation automatically after the temperature cool down to 0. The variation of protected temperature is about 0%. Short Protection To protect loudspeaker drivers from over-current damage, has built-in short-circuit protection circuit. When the wires connected to loudspeakers are shorted to each other or shorted to PGND or to PVCC, overload detectors may activate. Once one of right and left channel overload detectors are active, the amplifier outputs will enter a Hi-Z state and the protection latch is engaged. The short circuit protection latch can have auto-recovery function. The latch state will be released after 40msec, and the short protection latch will re-cycle if output overload is detected again. Under Voltage Detection When the PVCC voltage is lower than 4V loudspeaker drivers of right/left channel will be disabled and kept at low state. Otherwise, return to normal operation. GVDD Supply The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the control pin voltage divider circuit. Add a μf capacitor to ground at this pin. BST Capacitors The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 0.uF ceramic capacitor, rated for at least 5V up, must be connected from each output to its corresponding bootstrap input. Specifically, all 0.uF capacitor must be connected from OUT to BST pin. 5

16 Ferrite Bead Selection If the traces from the to speaker are short, the ferrite bead filters can reduce the high frequency emissions to meet FCC requirements. A ferrite bead that has very low impedance at low frequency and high impedance at high frequency (above M) is recommended. The impedance of the ferrite bead can be used along with a small capacitor with a value around 000pF to reduce the frequency spectrum of the signal to an acceptable level. Figure.4 Typical Ferrite Bead Filter Output LC Filter Selection If the traces from the to speaker are not short, it is recommended to add the output LC filter to eliminate the high frequency emissions. Figure. 5 shows the typical output filter for 8 speaker with a cut-off frequency of 7 k, Figure. 6 shows the typical output filter for 4 speaker with a cut-off frequency of 7 k. Figure.5 Typical LC Output Filter for 8 Speaker Figure.6 Typical LC Output Filter for 4 Speaker Power Supply Decoupling Capacitor (CS) Because of the power loss on the trace between the device and decoupling capacitor, the decoupling capacitor should be placed close to VIN, PVCC and PGND to reduce any parasitic resistor or inductor. A low ESR ceramic capacitor, typically 000pF, is suggested for high frequency noise rejection. For mid-frequency noise filtering, place a capacitor typically 0. F or F as close as possible to the device VIN, PVCC leads works best. For low frequency noise filtering, a 00 F or greater capacitor (tantalum or electrolytic type) is suggested. Figure.7 Recommended Booster Power Supply Decoupling Capacitors 6

17 PBTL (Mono) Function provides the application of parallel BTL operation with two outputs of each channel connected directly. If the PBTL pin is tied high, the positive and negative outputs of left and right channel are synchronized and in phase. Apply the input signal to the RIGHT channel input in PBTL mode and let the LEFT channel input grounded, and place the speaker between the LEFT and RIGHT outputs. The output swing is doubled of that in normal mode. See the application circuit example for PBTL (Mono) mode operation. For normal BTL (Stereo) operation, connect the PBTL pin to ground. BOOST COVERTER APPLICATION INFORMATION Detailed Description is a high efficiency stereo class-d audio amplifier with built-in boost dc-dc converter. The constant switching frequency is 500k and operates with pulse width modulation (PWM). The control loop architecture is peak current mode control; therefore slope compensation circuit is added to the current signal to allow stable operation for duty cycles larger than 50%. Over Voltage Protection The has output over-voltage protections. The thresholds output OVP circuit minimum 8% x VOUT, respectively. Once the output voltage is higher than the threshold, the NMOS driver is turned off. When the output voltage drops lower than the threshold, the NMOS will be turned on again. Over Current Protection The cycle-by-cycle limits the peak inductor current to protect NMOS driver. The NMOS driver will turn off when switching current reaches OCP level. Over Temperature Protection The will turn off the power MOSFET automatically when the internal junction temperature is over 50 C. The power MOSFET wake up when the junction temperature drops 30 C under the OTP threshold temperature. Soft Star Soft start circuitry is integrated into to avoid inrush current during power on. After the IC is enabled, the output of error amplifier is clamped by the internal soft-start function, which causes PWM pulse width increasing slowly and thus reducing input surge current. Inductor Selection Inductance value is decided based on different condition. 3.3uH to 0µH inductor value is recommended for general application circuit. There are three important inductor specifications, DC resistance, saturation current and core loss. Low DC resistance has better power efficiency. Capacitor Selection The output capacitor is required to maintain the DC voltage. Low ESR capacitors are preferred to reduce the output voltage ripple. Ceramic capacitor of X5R and X7R are recommended, which have low equivalent series resistance (ESR) and wider operation temperature range. Diode Selection Schottky diodes with fast recovery times and low forward voltages are recommended. Ensure the diode average and peak current rating exceed the average output current and peak inductor current. In addition, the diode s reverse breakdown voltage must exceed the output voltage. 7

18 Output Voltage Setting The output voltage of can be adjusted by a resistive divider according to the following formula: V OUT V R R * 0.6* R R REF The resistive divider senses the fraction of the output voltage as shown in Figure.8 Using large feedback resistor can increase efficiency, but too large value affects the device s output accuracy because of leakage current going into device s FB pin. The recommended value for R is therefore in the range of 0~0KΩ. Figure.8 The resistive divider senses the fraction of the output voltage PCB Layout Because the is a class-d amplifier that switches at a high frequency, the layout of the PCB should be optimized according to the following guidelines for the best possible performance., Thermal pad The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability., Decoupling capacitors The high-frequency 0.uF decoupling capacitors should be placed as close to the VIN PVCC pins and VCC pin terminals as possible. Large (00uF or greater) bulk power-supply decoupling capacitors should be placed near the device on the PVCC and VCC terminals. 3, Grounding The AVCC pin decoupling capacitor should each be grounded to analog ground (PGND). The PVCC decoupling capacitors should each be grounded to power ground (PGND). Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the. 4, Output filter The reconstruction filter should be placed as close to the output terminals as possible for the best EMI performance. The capacitors should be grounded to power ground. 5, The input resistors need to be very close to the device input pins so noise does not couple on the high impedance nodes between the input resistors and the input amplifier of the device. 6, Making the high current traces going to VIN, PVCC, GND, VO+ and VO- pins of the device should be as wide as possible to minimize trace resistance. If these traces are too thin, the device s performance and output power will decrease. The input traces do not need to be wide, but do need to run side-by-side to enable common-mode noise cancellation. 8

19 PACKAGE OUTLINE DIMENSION TSSOP 8 Pin Package Outline Dimension 9