Synchronous DC/DC Converters in High-Current Processor Power Delivery Systems

Transcription

1 Synchronous DC/DC Converters in High-Current Processor Power Delivery Systems Synchronous DC/DC Converters in High-Current Processor Power Delivery Systems Shamala A. Chickamenahalli, Yuan-Liang Li, and David G. Figueroa Intel Corporation 5000 W. Chandler Blvd Mailstop CH5-157 Chandler, Arizona Phone: Fax: Abstract Best performance of power delivery systems is detrimental to the successful operation of GHz range microprocessors. The location of the power sources in close proximity of the processor module has been possible due to improved packaging technologies. With the advances in MOSFET technologies, switching a DC/DC converter at several MHz has become rather common. Likewise, current capabilities of these switching power devices have been significantly enhanced. With this, simultaneous reduction in the size of the converters has been achieved while also achieving increased performance. Reduction in the ripple currents of basic DC/DC converters that are an integral part of voltage regulator modules (VRMs) has been attempted. Configuring several individual DC/DC converters in interleaved fashion has enabled researchers to handle the ripple currents through the VRM phase inductors. Also, multiple phases of these converters are required in order to meet the increasing transient power requirements of the load. In this paper, the application of a multiple-phase, full synchronous DC/DC converter when connected to a microprocessor power delivery system is addressed. Performance evaluation of the complete power delivery system based on a single and four-phase DC/DC converter is achieved. Advantages and disadvantages of each design are noted. Comparison is also made for various load representations. The load representations considered include a piecewise linear current source, and a first and second-order polynomial voltage controlled current source. Differences in the output characteristics with a simple DC source and its replacement with an actual VRM are also highlighted in this work. The contributions of the paper include setting guidelines in determining appropriate use of ideal or realistic power sources for power model analysis. The assessment of validity of these sources and their effects on the transient performance are key elements of this work. The paper is concluded providing thoughts on future directions. Key words: 1. Introduction and Background Processor Power Delivery, VRM, Decoupling Capacitors, and Voltage Regulation. Voltage regulator modules (VRM) that are an integral part of the power processing stages beyond the silver box have undergone tremendous growth. These advances have been possible due to the technological advances in MOSFET and other device technologies, processes and improvements in their switching frequencies. The reduction in sizes of devices has also lead to several levels in the integration of control and power circuits. Several VRM topologies applicable for microprocessors have been studied 1-3. A buck converter with a synchronous rectifier has been the best candidate for the VRMs of microprocessor power International Microelectronics And Packaging Society 303

2 Intl. Journal of Microcircuits and Electronic Packaging supplies for a long time 4. Studies on topologies of synchronous buck converters fed from 12V is reported in Reference 5. Analysis when the VRM is fed from a 5V input is also available in Reference 3. On the other hand, the operating voltage of microprocessor CPUs has constantly declined and may be below 1V in the near future 6. The current levels may exceed 100A at the output of a VRM 6. Of the noticeable breakthroughs in this direction is the rigorous need to enhance the switching frequencies of VRMs from the current few hundred s of khz to several MHz. Adopting more than one phase for conducting the increased currents is another recent approach. Increasing the number of phases drastically reduces VRM filter element sizes and reduces VRM response time. Due to multiple phases conducting over any cycle, the ripple current is also reduced at the output of the VRM. Studies relating performance while paralleling several VRM phases have been reported 7-9. Experimental work has predicted the efficiency attainable in these configurations 7. However, achieving these VRM efficiencies in the 90% range still remains a constant challenge. Application of a switching power converter in the power supply scheme of a typical Microprocessor is the subject of this paper. A multi-phase VRM model and its design considerations are given in Section 3. Power model performance when fed with a simple voltage source and an actual four-phase switching VRM is discussed in Section IV. Comparison is made of the effect of different die load representations. Also, responses of a singlephase VRM and a four-phase VRM are studied. The input voltage of 12 V is chosen in the analysis. 2. Lumped Model of A Processor Power Delivery System Figure 1 represents the lumped power model of a typical microprocessor. The various loops represent stages of package and i in 1 S L f a a interconnect. The model elements actually are interconnect element parameters and their parasitics. The first and second level IL I 0 I s2 L V in O of decoupling is provided by the capacitors C pkg and C int. The die C V S f S2 2 V 0 A can be represented in several ways. A voltage controlled current D source representation G is shown in this case. The battery in series with an inductor and a capacitor across the combination Current Feedback serves as a simple source to the power model. A switching Voltage fs Switching Feedback Control Feedback power supply marked Powerpod in Figure 1 replaces this simple frequency and Drive Circuits source when the case is that of a realistic switching power source. Eref The integral component of the switching supply is the voltage regulator module (VRM). The VRM attaches to the rest of the Figure 2(a). Schematic of a synchronous-rectifier based power delivery system via a connector. The processor voltage buck converter. V cc is monitored across the nodes 3 and 2 as shown. The die voltage across nodes 6 and 7 is monitored to determine if the circuit meets transient droop voltage specifications. The circuit model when fed with a simple source is passive, whereas, with the VRM as the input stage, the circuit becomes an active circuit that involves feedback control (voltage across points marked volt- age feedback point in Figure 1) and suitable timing strategies for the switches. In the next section, a brief description of a VRM along with its design considerations is provided. RVRML LVRM VRM CVRM Lesl Resr Power pod 1 REsr CHF LEsl Redgeu Ledgeu Lintu Vdd monitor Vss monitor Redgel Ledgel Lintl Rintl 3 2 Voltage feedback point Rintlu Interposer Voltage feedback point CInt Linte Resre Rpkgu Lpkgu Rdieu Ldieu Rpkgl Lpkgl Rdiel Ldiel Package Cpkg Rpkge Epkge 4 Cdie Rdie die Figure 1. Lumped power model schematic of an Intel microprocessor. 3. VRM Model Figure 2 (a) represents the equivalent circuit of a buck type VRM model 1-3 The main switch S enables the step down of the. 1 input voltage. L f and C f constitute the low pass output filter elements. The duty ratio D of the converter is the ratio of the input voltage V in and the output voltage V 0. Switch S 2 conducts at all other times when the main switch S 1 is off. Thus, the current I L in the inductor L f varies between values of I max and I min as shown in Figure 2(b). The two switches are switched at a rate that is termed as the VRM switching frequency f s. The switch S 2 can be a fast diode or a MOSFET. When the switch S 2 consists of a MOSFET instead of a diode, the configuration represents a synchronous rectifier topology. E ref is the voltage whose value is to be maintained across the monitor points as V cc. It serves as one of the inputs to a comparator inside the controller that implements both VRM voltage and current feedback. 6 G International Microelectronics And Packaging Society

3 Synchronous DC/DC Converters in High-Current Processor Power Delivery Systems V 0 il I max I min il δv 0 V 0av g Figure 2(b). Voltage across VRM bulk capacitor C f and the current in inductor L f Multi-Phase VRM Figure 3 shows the block diagram of a four-phase VRM without the control and driver circuitry. The advantages of multi-phase VRMs were mentioned earlier in terms of reduced cost, size and improved response time. A multi-phase VRM consists of several phases in which each phase conducts for an equal part of each cycle. Within each phase, the two switches conduct in the same manner as described in the basic converter. Each phase consists of a per-phase inductor. However, a single bank of bulk capacitors is used at the output point where all the phases combine. i0 Both the VRM inductance and the bulk capacitance values vary inversely with the switching frequency. A comparison of the inductances and the capacitances of the VRM for a single and four-phase design is made in Table 1. It can be observed from Equation (1) and Table 1 that it is advantageous only if both the switching frequency and the number of phases are increased such that the reduction in VRM element size is really achieved. Equally important to the design of the VRM is the cost attributed by the VRM bulk capacitors. It is usual that the available capacitors have higher ESRs for higher capacitance values. At any time, the maximum value of the ESR calculated per Equation (1) should not be exceeded in order that the design considerations are met. This requirement is invariably met using several legs of identical capacitors matching the effective ESR to less than the maximum. Alternatively, a graded response from the VRM is obtained using several legs of capacitors of varying capacitance. Table 1. Comparison of VRM inductance and capacitances. Single-phase Four-phase Ten-phase Phase 1 Motherboard and packaging stages VRM Switching frequency 250kHz 1MHz/ph 1MHz/ph VRM inductance 275nH 200nH/ph 530nH/ph Bulk Capacitance 16mF 1056µF 420µF Vin Phase 2 Phase 3 Phase 4 C f The magnitude of the current that a VRM has to supply also determines its transient requirement. The initial rate of application of the load current is effectively met by the interconnect and package stages. The minimum theoretical response time of the VRM is given by Equation (2), of the form, I L f tresponse = (2) V Figure 3. Four-phase VRM block diagram. where I is the change in converter output current, V is the change in the voltage across the inductor and L f is the inductor 3.2. VRM Design Considerations value 4. As an example, if V in =12V, V o =1.5V, and the current in a 50nH inductor varies between 50A and 75A, then V=12- The magnitude of the current a VRM has to supply (I L ), the 1.5=10.5V, I o =75-50=25A. The theoretical response time of magnitude of current change in the inductor ( Ι L ), voltage at which the VRM in such a case is 120ns. the current is supplied, voltage regulation ( V 0 ) at any load, and the amount of voltage ripple (δv 0 ) allowed determine the VRM inductor and capacitor values. The frequency at which the VRM is to be switched and the number of phases are additional inputs in 4. Simulation Results a multi-phase design. The VRM is most commonly designed with a 5% voltage regulation and 1-% ripple voltage specification. The VRM phase current ripple is considered to be 20-50% of its average value. Based on these considerations, the VRM inductance, formance. The simulations are carried out on Orcad Pspice A/D. Extensive simulations are done to study the power model per- the minimum bulk capacitor, and the maximum ESR are given by First, a study with the power model when fed with a simple voltage source is presented. Then, the droop study is repeated with Equation (1), V D) Lf = 0(1 I δv L Cf = ES = 0 the complex VRM model replacing the simple VRM. Comparison is made of the data when a single-phase and a four-phase ma fs I 8f V L sδ 0 I L (1) International Microelectronics And Packaging Society 305

4 Intl. Journal of Microcircuits and Electronic Packaging VRM supply the circuit. Different die load representations are also studied Comparison of Simple and Actual VRM Models: A simple VRM model consists of an ideal battery in series with a small resistance and an inductance and a bulk capacitor across the combination. A transient current load is applied at the die in order to study the voltage droop characteristics. The waveform of the voltage V die across the die of Figure 1 for both the simple source and a four-phase VRM as sources is illustrated in the bottom traces of Figure 4(a). The top trace is of the voltage V cc measured after the power POD connector in Figure 1. The voltage droop target for both cases is 10% below V cc. Three distinct droops are expected in the waveforms corresponding to the package-die, interposer-package, and VRM-interposer loops. In the waveforms that pertain to the complex VRM case, the VRM feedback control loop responds and the voltage begins to rise to the required V cc value after the third droop. Whereas in the simple source case, the voltage continuously decreases as there is no control and hence a third droop is not seen. The first droop voltages are 1.133V and 1.130V, the second droop voltages are 1.164V and 1.163V, and third droop voltage for the case with VRM is 1.158V. This means that for the first and second voltage droops, no significant difference between using a simple VRM model and a four-phase VRM. A comparison of the transient response of the VRM that feeds the power model of Figure 1 is illustrated in Figure 4(b), where the current supplied at the die and the current in the connector which is the sum of all VRM phase currents are shown. The current drawn from a simple VRM is comparatively lower than that drawn from a four-phase VRM model due to large amounts of bulk capacitors used in the simple VRM case. 1.25V VRM model 4.2. Comparison with Single and Four-Phase VRM Models as Sources A 250kHz single-phase and 1MHz/ph, four-phase VRMs, whose design values were provided in Table 1, were tied as inputs to the lumped power model. The waveforms of the voltages across the die and after the power POD connector are shown in Figure 5(a). The currents at the output of the VRM and at the die are shown in Figure 5(b). As can be observed, the response time of the four-phase model is much smaller than that of the singlephase model due to its much smaller inductance per phase and the much lesser bulk capacitance. A similar observation can be made on the current response. The single-phase VRM provides a slow and flat transient response to the load than the four-phase VRM. In other words, VRM switching frequency and the number of VRM phases do determine the response characteristics of the VRM. Also, a comparison of the droop voltages obtainable in the four and single-phase cases, in addition to that with a simple VRM are shown in Table 2 in which the ideal case entries are from the previous section. From the second droop data in Table 2, one can observe that the slower single-phase VRM design is not as effective as the faster four-phase VRM design for this power delivery system. This comparison also signifies currently achieved industry VRM frequencies V 1.240V 1.200V 1.160V Vcc with 4-phase VRM Vcc with single-phase VRM Die voltage with single-phase VRM Die voltage with 4-phase VRM 1.121V ms ms ms ms ms v(21,39) v(26) Simple model 1.20V Die voltage with VRM V Die voltage with simple 100 with 4-phase 1.10V m m m m m m m v(26) v(21,39) with single-phase 110A A Die Current With VRM With Simple 80A I(G_G1) I(L_Ledge) Tim A m m m m m m I(G_G1) I(L_Ledge) Figure 4. Waveforms of voltage and currents with simple source and VRM source (a) Voltage across die and after POD connector (b) Current transient at the die and the total VRM output current. Figure 5. Waveforms of voltage and currents with single and four-phase VRM source (a) Voltage across die and after POD connector (b) Current transient at the die and the total VRM output current. International Microelectronics And Packaging Society

5 Synchronous DC/DC Converters in High-Current Processor Power Delivery Systems Table 2. Effect of single and four-phase designs on droop characteristics. 5. Conclusion and Future Directions Case Droop1(V) Droop2 (V) Droop3(V) Ideal voltage source 1.133V 1.164V NA Single-phase VRM 1.130V 1.158V 1.154V Four-phase VRM 1.130V 1.163V 1.158V 4.3. Comparison with Different Die Load Representations The effect of different die representations is investigated when the lumped model was fed with an actual VRM. The droop voltage values and obtained currents at the die and at the edge connector with a single and double order voltage controlled current source G representation of the die and with an ideal piecewise linear current source I pwl are represented in Figure 6. The voltage across the die nodes 6 and 7 and a piecewise linear voltage source across nodes 10 and 0 constitute the elements of the second order polynomial G source. As can be observed from the droop waveforms, the difference between a single-order polynomial and the piecewise linear case is not great as compared to the double-order polynomial case. It can be concluded that a piecewise linear representation predicts more pessimistic droops than the other two as the current achieved from a piecewise linear representation is comparatively higher than that achieved from the other two representations. 1.25V 1.20V 1.15V Vcc Die voltage With double-order polynomial With single-order polynomial With Piecewise linear source 1.10V m m m m m m1.0020m v(26) v(21,39) 119.2A 100.0A Piecewise linear Application of a synchronous rectifier type of buck converter in a typical microprocessor has been discussed in this publication. A lumped power model of the processor is considered in the study. A simple VRM and a four-phase complex VRM as sources and their transient responses are compared. The simulations yield no significant difference in the first and second voltage droops when using a simple and a four-phase VRM. With an actual VRM, due to the voltage feedback, the voltage begins to rise towards V cc value after the third droop. Whereas with a simple VRM, it continuously decreases as there is no control, and hence, a third droop is not seen. The current drawn from a simple VRM is comparatively lower than that from a four-phase VRM model due to the large bulk capacitance used. A singlephase VRM provides a slow and flat transient response to the load than the four-phase VRM. Also, a comparison of the second droop voltages indicates that a 250kHz single-phase VRM design is not as effective as the 1Mhz/phase four-phase VRM design for this power delivery system. As far as different die representations, a double polynomial representation is close to a real system than a piecewise linear or a single-order polynomial load representation since it takes the actual voltage available at the die into consideration than the other two in driving the load current. Hence, a piecewise linear representation predicts the most pessimistic droop of the three as it draws the highest current, a current which is not realistic. The outcome of this work is that for first and second droop analysis analysts can use a simple VRM so that results can be obtained instantaneously. However, if the effect of power supply is in perspective, the analysis must include the VRM and its feedback control loop behavior. These distinctions are very essential in conducting sensitivity simulations and also to have an actual idea of the times required for analysis. Also, the studies can serve in identifying bottlenecks in the model stages. As a future direction, comparison between lumped and distributed model performances will be attempted so that similar guideline can be established for future simulation and analysis. Improved techniques for prediction of accurate lumped models from distributed package and interconnect power models will be attempted in parallel. 80.0A econd-order polynomial Single-order polynomial Acknowledgments 60.4A m m m m m m I(G_G1) I(I_1) I(L_Ledge) Figure 6. Waveforms of voltage and currents with different die representations (a) Voltage across die and after POD connector (b) Current transient at the die and the total VRM output current. The authors would like to thank their Manager, PR Patel for his support of this work. The authors would also like to thank their colleagues Michael T. Zhang, James Dinh, and Ed Stanford for useful discussions. International Microelectronics And Packaging Society 307

6 Intl. Journal of Microcircuits and Electronic Packaging About the authors Shamala A. Chickamenahalli (S 93-M 95) received her B.E and M.Tech Degrees in Electrical Engineering from Bangalore University and Indian Institute of Technology, Khargapur, India, in 1983, and 1986, respectively. She obtained her Ph.D. in Electrical Engineering from the University of Kentucky, in May From 1986 to 1988, she worked as a senior engineer at Kirloskar Electric Co., India, and from 1988 to 90, as a Scientist at a defense research laboratory in India. She was an Assistant Professor from August 1994 to May 1999 at Wayne State University, Detroit, Michigan where she taught and carried out DSP based digital control for automotive applications. Currently, she is a senior packaging engineer at Intel Corporation, Arizona, where she concentrates on voltage regulator and power delivery schemes for microprocessors. Her areas of research interests include modeling, analysis, and simulation studies of novel low power converter topologies. Yuan-Liang Li received the Ph.D. Degree in Electrical and Computer Engineering, from the University of Illinois at Urbana-Champaign, in He worked for U.S. Army Research Laboratory, Champaign, Illinois, from 1991 to In 1996, he joined Intel Corporation, ATD, DPD, Electrical Analysis & Design, Chandler, Arizona, where he is currently the leader of Signal Integrity, Power Delivery, and EMI teams. His professional interests include electromagnetic modeling, simulation, and measurement of interconnects. Dr. Li is an Adjunct Associate Professor of Electrical and Computer Engineering Department, the University of Arizona, Tucson. 3. Pit-Leong Wong, F.C. Lee, Xunwei Zhou, Jiabin Chen, and Xingzhu Zhang, VRM Transient Study and Output Filter Design for Future Processors, Proceedings of the 1998 Applied Power Electronics Conference and Exposition, APEC 98, pp , Todd M. Sherman, Powering Today s New Generation Microprocessors, Application Note, Cherry Semiconductor Corporation. 5. Xunwei Zhou, Bo Yang, L. Amoroso, F. C. Lee, and Pit-Leong Wong., A Novel High-Input-Voltage, High Efficiency and Fast Transient Voltage Regulator Module-Push-Pull Forward Converter, Proceedings of the Applied Power Electronics Conference and Exposition, APEC 99, Vol. 1, pp , Edward Stanford, Device Requirements for Future CPU Voltage Regulators, Japan Switching Power Symposium, Xunwei Zhou, Xu Peng, and F. C. Lee, A High Power Density, High Efficiency and Fast Transient Voltage Regulator Module with a Novel Current Sensing and Current Sharing Technique, Proceedings of the Applied Power Electronics Conference and Exposition, APEC 99, Vol. 1, pp , M. M. Jovanovic, David E. Crow, and Fang-Yi Lieu, A Novel, Low-Cost Implementation of Democratic Load-Current Sharing of Paralleled Converter Modules, IEEE Transactions on Power Electronics, Vol. 11, No. 4, pp , July D. K. W. Cheng, X. C. Liu, Y. S. Lee, and Hom Hung, Parallel Operation of DC-DC Converters with Synchronous Rectifiers, Proceedings of the 1998 Power Electronics Specialists Conference, PESC 98 Record, pp (Vol. 2) pp (Vol. 1), David G. Figueroa received B.S. Degree in Electrical Engineering from the University of Texas at El Paso, in He joined Intel Corporation, Chandler, Arizona, in 1996, where he has worked on the electrical modeling and characterization of interconnects and discrete components. His interests include power delivery, signal integrity, and the experimental characterization of interconnects and discrete components. References 1. Michael T. Zhang, M. Jovanovic, and F. C. Lee, Design Considerations for Low-Voltage On-Board DC/DC Modules For Next Generations of Data Processing Circuits, IEEE Transactions on Power Electronics, Vol. 11, No. 2, pp , March Xunwei Zhou, Xingzhu Zhang, Jiangang Liu, Pit-Leong Wong, Jiabin Chen, Ho-Pu Wu, Luca Amoroso, F.C. Lee and Dan Y. Chen, Investigation of Candidate VRM Topologies for Future Microprocessors, Proceedings of the 1998 Applied Power Electronics Conference and Exposition, APEC 98, pp , International Microelectronics And Packaging Society