Three-Phase AC Side Voltage-Doubling High Power Density Voltage Source Converter with Intrinsic Buck-Boost Cell and Common Mode Voltage Suppression

Transcription

1 /TPEL , IEEE Transactons on Power Electroncs Three-Phase AC Sde Voltage-Doublng Hgh Power Densty Voltage Source Converter wth Intrnsc Buck-Boost Cell and Common Mode Voltage Suppresson Peng L, Gran Phlp Adam Member IEEE, Yhua Hu Member IEEE, Derrck Hollday and Barry Wllams Abstract The three-phase two-level voltage source converter (VSC) s wdely employed n power conversons between AC and DC for ts four-quadrant operaton and control flexblty. However, t suffers from the low output voltage range wth a peak value of half DC-lnk per phase, whch necesstates the use of ether hgh DC-lnk voltage or bulky step-up transformer to enable the medum voltage operaton. Addtonally, the hgh common mode (CM) voltage between AC loads neutral ponts and ground may reduce the servce lfe and relablty of electrc machnery. In ths paper, a three-phase AC sde voltage-doublng VSC topology wth ntrnsc Buck-Boost cell s analyzed. By ths confguraton, the AC sde voltage s doubled wth the phase peak value equal to DC-lnk. That s, only half of the DC sde capactor bank s needed to generate the same output voltage. The proposed converter uses ts buck-boost cell as a vrtual voltage source to synthesze negatve half of the output voltage by modulatng ts output AC phase voltage around the negatve bus (whch s the real zero when grounded). Ths permts the average CM voltage to be suppressed to zero, and loads connected to converter AC sde not to wthstand any DC voltage stress (reducng the nsulaton requrement). Modelng and control desgn for both rectfer and nverter modes of ths converter n synchronous reference frame have been nvestgated to ensure a four-quadrant three-phase back-to-back system. Expermental results have verfed the feasblty and the effectveness of the proposed confguraton and the desgned control strateges. Index Terms AC sde voltage-doublng, Common mode voltage suppresson, Intrnsc Buck-Boost Cell, Three-phase Back-to-Back system, Four-quadrant operaton. P I. INTRODUCTION ower electroncs based energy converson systems have acheved deep penetraton n low, medum and hgh voltage applcatons such as power transmsson and reactve power compensaton, grd nterfacng of renewable energy, machne drves, etc. Snce tradtonal AC grds stll domnate n power systems, AC power converson nvolvng Manuscrpt receved on August 1, 014; revsed on September 3, 014; accepted on October 4, 014. Ths work was supported by EPSRC Underpnnng Power Electroncs 01: Converters Theme research programme (EP/K035096/1). P. L, G.P. Adam, Y. Hu, D. Hollday, B. Wllams are wth Department of Electroncs and Electrcal Engneerng, Unversty of Strathclyde, Glasgow, G1 1XW, UK. (e-mal: peng.l@strath.ac.uk, gran.adam@eee.strath.ac.uk, yhua.hu@strath.ac.uk, derrck.hollday@eee.strath.ac.uk, barry.wllams@ eee.strath.ac.uk). ampltude regulaton, phase and frequency control, actve power and reactve power management for utlty/mcro-grd applcatons has always drawn many attentons of both academa and ndustry. The back-to-back (BB) VSC confguraton s wdely used among varous AC converson solutons for ts superorty on control smplcty, voltage utlzaton over the Matrx Converter and dynamc performance over other current source converter based solutons [1, ]. Ths s because t offers fourquadrant operaton ablty, decouplng of the two connected AC sdes and ndependent control of actve/reactve power. Nowadays, VSC together wth ts BB confguraton have overstepped the tradtonal power tracton area and spread nto the utlty applcatons, such as PV (photovoltac) grd connecton, wnd energy nterfacng, flexble AC and hgh voltage DC transmsson systems (FACTS and HVDC) [3-9]. Fg. 1 Three-phase two-level voltage source converter. The three-phase two-level converter depcted n Fg. 1 s wdely accepted for AC-DC and DC-AC power converson systems n research and ndustry. However, n ths topology, the peak value of AC sde voltage per phase cannot exceed half of DC lnk voltage wth tradtonal Snusodal Pulse Wdth Modulaton (SPWM). Although the Trplen Snusodal Pulse Wdth Modulaton (TSPWM), Space Vector Modulaton (SVM) and Selectve Harmonc Elmnaton (SHE) methods have been developed to extend the fundamental voltage output range n AC sde, the ncrease s not obvous (15.5% for TSPWM/SVM, and slghtly larger for optmzed SHE) [10]. In addton, three-phase balanced condtons should be guaranteed to nsure ths extenson n voltage utlzaton, otherwse, low order harmoncs wll be observed n the lneto-lne voltages and lne currents. Ths s because zero sequence components wll emerge n phase voltage when t goes beyond the envelopes of the postve and negatve DClnk, whch can only be neutralzed under three-phase balanced stuaton. Therefore, operaton n medum and hgh voltage applcatons requres hgh DC-lnk voltage (mnmum of twce peak fundamental voltage) or the bulky step-up (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE

2 /TPEL , IEEE Transactons on Power Electroncs transformer for voltage matchng, whch n turn ncreases the system cost, sze and weght. The CM voltage between AC and DC sdes s nherent for all brdge type solutons. The three-phase two-level VSC n Fg. 1 may mpose DC voltage stress on the AC sde loads dependng on the adopted groundng arrangement [11, 1]. When the negatve termnal s grounded, the output phase voltage relatve to real ground vares around half DC-lnk, and ths requres the AC loads to be able to wthstand DC voltage stress [13]. Furthermore, the voltage fluctuaton around half DC-lnk on the load neutral pont may exacerbate the bearng voltage problem n machne drves such as wnd turbne nterfacng. The splt DC-lnk capactor wth parallel balancng resstors can be employed to address the problem of DC voltage stress and reduce the mpact of the CM voltage. However, ths soluton s less attractve as t ntroduces addtonal loss and cost. A certan case under the spotlght recently s the transformerless PV ntegraton area where many efforts have been made to dmnsh ths CM component across the parastc capactor between the PV arrays and ground. The H5, H6 and HERIC schemes are canddates to suppress the CM leakage current [14]. However, the CM voltage component stll exsts and keeps constant n these stuatons. The vrtual DC bus concept [15] and HA4S converter [16] have been advanced to elmnate the CM voltage by drect connecton between ground termnals. Unfortunately, the solutons above are n sngle-phase applcaton and orgnate from the H-brdge topology. Thus, t s dffcult to transplant these derved converters drectly nto three-phase condton. In ths paper, a three-phase AC sde voltage-doublng (ACVD) converter wth ntrnsc Buck-Boost cells (IBBCs) has been proposed, whch can generate the AC phase voltage wth a maxmum peak value equal to full DC-lnk voltage, doublng the output range of the tradtonal three-phase twolevel VSC. On the other hand, the DC-lnk can be halved when the same output voltage s demanded. Consequently, ether the lne transformers or the DC capactor bank can be reduced to form a compact and cost-effcent system. In addton, the dv/dt problem can be largely releved by the reduced DC-lnk voltage. Snce the proposed topology nherts a real ground fxed at negatve bus, ts output phase voltage s modulated around ths ground. As a result, DC voltage stress exerted on the AC loads can be suppressed to zero, and ths wll suppress the magntude of CM voltage to an average of zero, as seen by the load neutral ponts. Hence, reduced bearng voltage/current can be expected. Further employment of ether composted hardware confguraton or optmzed modulaton strategy can elmnate the hgh frequency components of the CM voltage, whch s beyond the scope of ths paper [17-19]. The ACVD converter s capable of beng employed n PV ntegraton, wnd energy nterfacng and dstrbuted FACTS areas potentally. The rest of the paper s organzed as follows. Operatonal prncple of the proposed converter s descrbed n Secton II. Secton III analyses the voltage and current stresses on the power swtches and presents some desgn ssues for passve components. In Secton IV, modelng process of the three-phase ACVD-VSC for nverter and rectfer modes n synchronous reference frame (SRF) s establshed. Then, Secton V presents the desgn of the control strateges mnutely. Afterwards, expermental verfcatons are presented n Secton VI to confrm the valdty of the proposed converter. Fnally, conclusons drawn and hghlght of major fndngs are summarsed n Secton VII. II. OPERATIONAL PRINCIPLE OF THE ACVD CONVERTER The proposed three-phase ACVD-VSC s shown n Fg., where the IBBC s nserted nto each phase of two-level converter to acheve an extended output voltage range. The sngle-phase crcut under nverter mode depcted n Fg. clarfes the structure of the topology n detal. It can be seen that the IBBC conssts of L 1 and C 1, whle L and C make up the output stage flter. The two power swtches S 1 and S conduct complementarly. Furthermore, V s the nput voltage, and 1, v 1, and v represent the four state varables on the passve components L 1, C 1, L and C respectvely. Notce that v 1 should be reversed relatve to the nput voltage to ensure the magnetc reset of the flux lnked n L 1. Smlarly, 1 and are also n opposte drectons to keep the voltage balance on C 1. Fg. Proposed ACVD Converter: confguraton n three-phase (wthout flter); sngle-phase unt operated n nverter mode. Operaton of the proposed converter can be descrbed usng two modes as follow: Mode 1: S 1 s turned on. Output voltage v fed from V s generated relatve to ground. Also, ths mode creates a zero loop of nductor L 1 and capactor C 1 for chargng the buckboost capactor wth reversed polarty as V. Mode : When S s on, the IBBC capactor s employed as a vrtual voltage source to generate the negatve voltage on the output. The nner nductor L 1 s also charged to store energy to get ready for the energy transfer n the subsequent swtchng cycle. Fg. 3 Steady state waveforms of the proposed converter n a statonary operaton pont when v, are postve and 1 s negatve Fg. 3 demonstrates the steady state waveforms of the proposed converter n a fxed operaton pont wth the (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE

3 /TPEL , IEEE Transactons on Power Electroncs assumpton that v, are postve and 1 s negatve. The output voltage v always falls nsde the envelope combned by nput voltage and IBBC voltage, whch guarantees the energy balance n the nductance. Smlarly, the nductor currents 1 and wll charge and dscharge the capactors n each swtchng cycle to obtan the composed voltage outputs. In further, the four-quadrant operaton of the ACVD-VSC s nterpreted by Fg. 4. In Fg. 4 and Fg. 4, flows out of the converter to the load, accordngly 1 should ether dscharge C 1 or feed ts stored energy back to the DC-lnk. The alternatve stuaton where flows nto the converter from the load and 1 draws energy from the DC sde to delver t to C 1 can be seen n Fg. 4(c) and Fg. 4(d). Thus, t s concluded that the proposed converter s a qualfed canddate for the four-quadrant operatonal VSC applcatons. value of the swtchng functon u over one swtchng perod s equal to the duty cycle D, then equaton (1) s reduced to: D( V1 V ) V 0 D( I I1) I 0 (3) D( V V1 ) ( V1 V ) 0 I Io 0 After algebrac manpulaton of frst and thrd equatons n (3), voltage transfer rato of proposed converter s obtaned as: V 1 M (4) V D Fg. 5 shows the plot of M versus D and t s observed that a bpolar voltage output can be acheved when the duty cycle vares around 0.5. V DC V AC 0 ωt (c) (d) Fg. 4 Swtchng modes for the proposed converter to mplement fourquadrant operaton: S 1 turns on wth outflow load current; S turns on wth outflow load current, (c) S 1 turns on wth nflow load current, (d) S turns on wth nflow load current. Based on the above analyss, the dfferental equatons that descrbe the dynamcs of the proposed converter are nterpreted n (1), d1 L1 u( v1 V ) V dt dv1 C1 u( 1 ) dt (1) d L u( V v1 ) ( v1 v ) dt dv C o dt where u s the swtchng functon defned as follows, 1, S1 turns on u () 0, S turns on Consderng the case where swtchng frequency s suffcently hgh compared to fundamental frequency of the AC voltage beng syntheszed, the assumpton that all the state varables can be vewed as constant s vald. Therefore, the dervatve terms n (1) can be set to zero, and the average (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE -V DC (c) Fg. 5 Voltage output range and modulaton for the proposed converter:. voltage transfer rato vs. duty cycle;. AC sde output voltage range; (c). open loop modulaton strategy based on transfer rato. From Fg. 5, the maxmum modulaton ndex s 1pu for the peak value of phase voltage (V ), whch s twce of that n two-level converter (½V ). In addton, trplen harmonc njecton dea can further extend ths range to 1.55pu. Equvalently, the output lne-to-lne peak voltage can reach pu (V ) n that case. Due to ths large extenson n DC utlzaton, reduced DC-lnk voltage and dv/dt can be acheved. Notce that nner capactance can be sgnfcantly less than DC lnk because of the fluctuant voltage across t. Besdes, the asymmetry between the two voltage levels syntheszed durng 3

4 /TPEL , IEEE Transactons on Power Electroncs modes 1 and may potentally dstort the output voltage by even order harmoncs when the modulaton strategy n Fg. 5(c) s adopted, where A m s the modulaton ndex. Therefore, proper converter operaton wth snusodal output voltage and current requres countermeasures to be ncorporated n the modulaton strategy to neutralze the negatve mpact of the dstorton, whch wll be nvestgated n later sectons. From the above analyss based on sngle-phase stuaton, t can be found that the DC-lnk and AC sde share the common ground. Consequently, n the three-phase three-wre system, the average value of the CM voltage between DC-lnk ground and AC neutral pont must be zero for any balanced condton. III. PERFORMANCE EVALUATION OF VOLTAGE/CURRENT STRESS AND INTEGRATED MAGNETIC SOLUTION In ths secton, a bref analyss of the voltage/current stress of power swtches and some desgn ssues for the passve components are demonstrated. The addtonal IBBC may exert some extra voltage/current stress on the devces. So t s mportant to unvel the quanttatve relatonshp between the electrcal stresses of the semconductor swtches and the output power, based on whch the gudelnes of the devce selecton s provded. Besdes, the ntegrated magnetc technque can be employed to ntegrate the two nductors nto one magnetc core, compactng the nstallatons and reducng the core costs. A. Voltage Stress Analyss Accordng to (3), the voltage on C 1 and C are gven by (5) and (6) respectvely. The opposte polarty of V and V 1 offers the possblty to generate the bpolar voltage on C. V1 (1 1/ D) V (5) V ( 1/ D) V (6) Consequently, the reverse blocked voltage of the power swtches S 1 and S can be calculated by (7). V V V V D (7) RB 1 / In further, snce the maxmum output-nput voltage rato s A m, the voltage stress s then shown by (8). V ( M) V ( Amsn t) V (8) RB It s notced that the duty cycle D vares from n the maxmum output condton when A m reaches the peak value 1. The maxmum voltage stress on the power swtches of the proposed converter s two tmes of DC voltage plus peak of the output phase voltage. Compared wth the two-level topology, voltage stress wll ncrease by 50% n extreme condtons. However, ths ncrease n voltage stress s logcal, because the presented ACVD converter holds the same DC utlzaton as full-brdge converter but wth half number of swtches. In other words, t has same number of swtches as two-level topology but wth twce DC lnk voltage utlzaton. Ths attrbute s acheved by the ncorporaton of IBBC. The fluctuant voltage across C 1 makes small value AC capactor avalable but causes the ncrease n power swtches [0]. B. Current Stress Analyss After manpulaton of equaton (3) for the current state varables, equatons (9) and (10) are obtaned, and observe that currents 1 and are n opposte drecton, whch s necessary for the energy balance of the C 1. I (1 1/ D) I (9) 1 I V R I (10) / o The current of the IBBC nductor 1 should passes through ether S 1 or S to store and release energy alternatvely. From Fg. 4, the total current for the power swtches should be the sum of absolute value of the two current state varables. Snce I 1 and I are always n opposte drectons, the total current stress of each power swtch can be expressed as n (11). I I I I I (11) c 1 1 In general, the power swtch current can be n further clarfed as (1), where φ s the power factor angle, ω s the angular frequency of the output voltage and I om represents the maxmum value of the load current. Ic I1 I ( Iom / D) sn( t ) (1) Consderng (4), the equaton (1) then can be developed as follows: Ic ( Am sn t) Iom sn( t ) (13) It can be deduced that some second order harmonc current wll be ntroduced by the IBBC. The peak value of the power swtch current happens when equaton (13) reaches the maxmum. An approxmate margn of three tmes of the load current should be consdered n practcal desgn. Notce that the output current of ths converter s to be approxmately half of that n two-level topology wth the same DC-lnk and same power ratng snce output voltage can be doubled due to the ntroduced IBBC, whch makes the current stress not to be a problem for the proposed converter. C. Passve Devce Selecton Fg. 6. Equvalent model of the power path for nner capactor C 1 of ACVD converter: S s on, S 1 s off; S 1 s on, S s off. Snce L and C form the output flter of the proposed ACVD converter, L and C can be selected usng well establshed flter desgn method of the conventonal two-level VSC as llustrated n [1]. Whlst L 1 and C 1 are selected based on the swtchng model from AC pont of vew snce all the state varables are AC. The equvalent power paths for nner capactor C 1 s shown n Fg. 6. When S s on and S 1 s off, nner capactor C 1 s n seres wth output flter nductor L as n Fg. 6. In order to make the AC component of the voltage across C 1 follow up the output voltage and avod the large hgh frequency oscllaton on C 1, the resonant frequency of C 1 and L s placed n the nterval of fundamental and swtchng frequences (f 0 and f sw ). Wth L, C and f sw are all known; the geometrcal mean n (14) s used to calculate C 1 as: f 1/ ( C L ) f f (14) r 1 0 In the proposed ACVD converter, the nner nductor L 1 s employed as a buffer for energy transfer from DC-lnk to C 1 n the perods where the upper swtch of each phase leg s on. Addtonally, It has smlar functon as MMC arm nductance, sw (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 4

5 /TPEL , IEEE Transactons on Power Electroncs whch can lmt the nrush current from the capactor C1 when the upper swtch of each phase leg s on []. In Fg. 6, L 1 and C 1 are n seres. Large L 1 value wll cause large fundamental voltage drop and lmt the magntude of hgh frequency current rpple. In ths sense, the characterstc mpedance of L 1 and C 1 n (15) should be used as a compromse between the output power range and rpple current demand. z L / C (15) D. Potental Use of Magnetc Integraton The proposed converter s capable of formng a threephase four-wre system, where the DC ground and AC ground s connected drectly. Thus, each phase can be controlled ndependently. Ths confguraton can be employed n UPS and aero-space applcatons. However, the analyss below s only based on three-phase three-wre system. A. The Inverter Mode Fg. 7 Prncples of the ntegrated magnetc soluton. The IBBC ntroduces an extra nductor nto the proposed converter per phase. In order to mprove the power densty, the magnetc ntegraton technque s competent to ntegrate the IBBC nductor and output flterng nductor nto one magnetc core [3-5]. Fg. 7 nterprets the soluton for the magnetc ntegraton technque, where a three-leg EE type magnetc core s employed. Some ar gaps are nserted nto the two outer legs whle no ar gap exsts n the center leg. The IBBC nductor L 1 s wound around one outer leg and the flterng nductor L s reversely wound around another outer leg. In ths way, the magneto-motve force wll be dstrbuted mostly on the outer legs and the two nductors can be decoupled effectvely. Fg. 7 shows that the flux lnkage of the two nductors wll be n opposte drectons, so the average component of the total flux n the center leg s dmnshed and the cross secton area of the center leg s reduced. Therefore, the power densty and the effcency can be enhanced wth the proposed magnetc ntegraton method. Ths approach s restrcted to low and medum power stages at present due to the lmted wndow area of the commercal hgh magneto-conductvty core. IV. MODELING OF THREE-PHASE ACVD CONVERTER IN SYNCHRONOUS REFERENCE FRAME The Park transformaton based decouplng model for the three-phase two-level VSC s wdely employed to mplement ndependent control of actve and reactve power. Snce the reference becomes DC value n SRF, zero steady state errors are expected wth proportonal-ntegral (PI) controller. In ths secton, the modelng of the proposed ACVD-VSC n SRF s performed to establsh an nsght vew of the control desgn. In order to establsh a general law for the operatonal analyss and control desgn, resstve load condtons have been assumed here and n the upcomng control desgn secton. For proper desgn, the load current can be treated as a new state varable. Thus, the order of the state space equatons and transfer functons that descrbe the proposed converter wll ncrease. Besdes, extra measurements are necessary. However, the overall procedure stays the same. Fg. 8 Rearrangement for the proposed three-phase nverter. The rearrangement of the three-phase ACVD-VSC as an nverter s depcted n Fg. 8. From the nstantaneous value based state space equatons n (1) and assumptons n (16), the three-phase AC sde equatons can be expressed as n (17). L La Lb Lc C Ca Cb Cc (16) R Ra Rb Rc r r r r a b c a b va vb a b va vb d L b c vb vc r b c vb vc dt c a vc v a c a vc v a va vb a b va vb d RC vb vc R b c dt vb vc vc v a c a vc v a (17) ab vab ab vab d L bc vbc r bc vbc dt ca v ca ca v ca vab ab vab d RC vbc R bc vbc dt v ca ca v ca where {v a, v b, v c } represents the converter output phase voltage (measurng from poles O={O 1,O,O 3 } relatve to the ground), and V s the DC sde nput voltage. Addtonally, R and r are the load and flter reactor (L ) resstances respectvely. Wth the defnton of u n (), the extended three-phase swtchng functon can be denoted as n (18). The converter output voltage s then defned n (19). It s notced that the proposed converter exhbts some tme-varant behavour that makes the large sgnal modelng wth complete decouplng nfeasble. Thus, some approxmatons have been made to facltate the development of the fundamental average model whch s necessary for control desgn and smplcty of the analyss (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 5

6 /TPEL , IEEE Transactons on Power Electroncs 1, S1 turns on u ( a, b, c) (18) 0, S turns on va ua 1 ua 0 0 va1 vb ub V 0 1 ub 0 vb 1 (19) v c u c u c v c1 To synthesze snusodal output voltage based (5), the IBBC voltage s expected to contan both DC and AC components. Accordng to the prevous analyss shown by (13), second order harmonc current wll emerge n the IBBC nductor. Consequently, AC voltage of IBBC capactor contans both the fundamental and the second order harmonc. When neglectng the second order harmonc for smplcty, (0) s obtaned. After applcaton of the classcal average method to swtchng functon, equaton (19) s rearranged nto (1), whch can be smplfed as (), va1 V va v V v b1 b v c1 V v c (0) v a da da V v a vb db V 0 db 1 0 V vb (1) v d c c V vc v a 1/ da ma vb 1/ db V mb V () v 1/ d c c m c where {d a, d b, d c } s the duty rato for each phase, {m a, m b, m c } s the equvalent transfer rato and s the averagng operator over one swtchng cycle. Furthermore, by defnng {m ab, m bc, m ca }={m a -m b, m b -m c, m c -m a }, the swtchng averaged AC sde equatons can be derved as n (3). The Park transformaton wth the form n (4) s then appled to obtan the equvalent tme-nvarant system. The decouplng model of the proposed ACVD nverter n SRF can be fnally acheved and demonstrated n (5). ab m ab v ab ab d L bc mbc V r bc vbc dt m ca ca ca vca v ab ab v ab d 1 C vbc bc vbc dt R vca ca v ca (3) cost cos( t / 3) cos( t / 3) T snt sn( t / 3) sn( t / 3) (4) 3 1/ 1/ 1/ d 1 d v d 0 d r d V m d dt L 0 q v L m q q L q q (5) d v d 1 d 0 v d 1 v d dt v C 0 RC q q vq vq The prevous stated second order harmonc dstorton problem caused by the IBBC must be treated separately wth addtonal control loops to ensure the pure snusodal output voltage and current, whch wll be covered n later part. B. The Rectfer Mode Fg. 9 Rearrangement for the proposed three-phase rectfer. Fg. 9 shows the proposed ACVD-VSC when t s confgured as a rectfer. The AC sde and DC sde equatons are shown n (6), n whch {v gab, v gbc, v gca }={v ga -v gb, v gb -v gc, v gc -v ga } represents the AC nput voltage, v s the output voltage, and con n (7) s the total current feedng from the converter to the DC sde. Based on the prevous approxmaton, the second order current component n IBBC nductor s neglected temporarly. From (9) and by utlzng the swtchng average operator, equaton (7) s to be developed nto (8). After substtutng () and (8) nto (6), the standard form of the proposed rectfer model s gven as n (9). v v ab ab ab gab d L bc vbc r bc vgbc dt ca vca ca v gca dv v Cd con dt Rd (6) a a1 con ua ub uc b 1 ua 1 ub 1 uc b1 (7) c c1 a ab con ma mb mc b mab mbc mca bc (8) c ca ab m v ab gab ab d L bc mbc v r bc v gbc dt m ca ca ca vgca (9) ab dv v Cd mab mbc mca bc dt Rd ca Usng the Park transformaton to acheve (30), whch clarfes the model of the proposed ACVD rectfer n SRF (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 6

7 /TPEL , IEEE Transactons on Power Electroncs d 1 d v gd 0 d r d v m d dt L 0 L m q v gq q L q q (30) dv 1 d v md mq dt C d R q dcd Smlar wth the nverter mode, the o axs s omtted n (30) for three-phase three-wre rectfer mode. And second order harmonc dstorton may happen to the lne current f no suppresson measure s appled. Thus, the elmnatng control loop s necessary to calbrate the modulatng sgnal to obtan lne current wth low total harmonc dstorton (THD). C. The Second Order Dstorton The second order dstorton can be explaned by usng the classcal transfer functon method. Quas-statc analyss s employed n ths part to unvel the system gan schedulng along dfferent operatonal ponts. Takng the sngle-phase nverter n Fg. wth resstve load R o for example, the swtchng average large sgnal model s shown n (31). The Taylor Seres based lnearzaton method s employed for a fxed operaton pont to obtaned state space equaton and transfer functon for perturbatons near to ths selected state. In ths way, (31) can be lnearzed nto (3). Usng Laplace transformaton to obtan the transfer functon G vd, whch s shown n (33). d1 L1 d( v1 V ) V dt dv1 C1 d( 1 ) dt (31) d L d( V v1 ) ( v1 v ) dt dv v C dt Ro d1 L1 D0v1 ( V1 V ) d dt dv1 C1 (1 D0 ) D01 ( I I1) d dt (3) d L (1 D0 ) v1 ( V1 V ) d v dt dv v C dt Ro G v () s 1 vd 3 4 ds () D B1 s Bs B3s B4s A L (1 D )( I I ) V A L1C 1 D (1 D ) L D L B1 R B L C D L C (1 D ) L C L1C 1L B3 R B o L C L C o V A s A s (33) Assumng the DC nput voltage s 1p.u. and modulatng ndex s 1, when the operaton pont vares snusodally, t can be found that the loop gan K vd s not constant as that n the two-level converter, on the contrary a perodcal vbraton s observed manly focused on fundamental and second order components as shown n Fg. 10. Besdes, both the zeroes and poles wll drft due to the varaton of duty cycle. Accordngly, the proposed converter wll show some second order dstorton and a thmbleful of thrd order components as by-products when operated n open loop. It s clearly that for the proposed converter wth normal PI controller and snusodal reference, the output voltage wll wane n ampltude and perform some nclnaton due to the non-unform dstrbuton of the loop gan and the floatng poles/zeroes. Consequently, zero steady state error s dffcult to be acheved by nstantaneous value control especally under heavy load stuatons. Fg. 10 Loop gan schedulng along snusodal operaton ponts:. loop gan vs. transfer rato;. FFT analyss of the loop gan vbraton. The reason behnd ths phenomenon s that the proposed converter shows some nerta nsde and cannot be vewed as an deal amplfer to the modulatng sgnal due to ts tme varant features. Smlar stuaton happens when nvestgatng the transfer functon G d for the sngle-phase ACVD rectfer. Although szng of the passve components can relax ths problem by some extent, the desgn degree of freedom wll be constraned and the passve devce nstallaton wll be huge. As a result, software soluton s preferred to thoroughly fx ths ssue. The elmnaton technques for the dstorton problems wll be clarfed n next secton. V. DESIGN OF THE CONTROL STRATEGIES FOR INVERTER AND RECTIFIER MODES USING STATE SPACE In ths secton, the desgn processes of the controllers under both nverter and rectfer modes are to be facltated n state space. Based on the decouplng model of proposed converter n SRF, the PI controller s suffcent to acheve zero steady state error. The transfer functons can be nvestgated by usng the root locus analyss to determne the proportonal gan and ntegral rate for the close loop n each control layer. A. Control Desgn for Standalone Inverter Mode The proposed converter s operated as a standalone nverter n voltage control mode, where the man objectve to establsh stff AC voltage bus across the load wth pre-fned frequency. Based on the SRF model n (5) where the voltage vector s algned wth the d-axs, the decouplng control scheme summarzed n Fg. 11 s developed. The detaled transfer functon s derved as follows (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 7

8 /TPEL , IEEE Transactons on Power Electroncs In (34), snce the quadrature axs holds the same structure wth drect axs, the transfer functons can be equvalently acheved as n (38). q K sk d p G d q K s( r Kp ) s L (38) v v d q Kv skvp Gv vd vq Kv s(1/ R Kvp ) s C Consequently, the current controller reference and the modulatng sgnal nto the PWM module can be derved as (39), whch s n accordance wth Fg. 11. U v L d d d q U v L q q q d C v d d q C v q q d (39) The global state space equatons for the drect-quadrant decouplng control system can be acheved n (40). Fg. 11 Control structure n standalone nverter mode:. two layers decouplng control; overvew of the control dagram ncludng the second order elmnatng loop. Rewrte (5) nto (34) for smplfcaton, n whch terms {χ d, χ q } and {λ d, λ q } can be obtaned from the PI controllers n the close loop system. d d 1 d r d dt q L q L q (34) d vd 1 d 1 vd dt v q C q RC v q V m v L K ( ) K ( ) dt d d d q p d d d d q Vmq vq L d Kp ( q q ) K ( q q ) dt (35) C v K ( v v ) K ( v v ) dt d d q vp d d v d d C v K ( v v ) K ( v v ) dt q q d vp q q v q q From (34), (35) and the defnton n (36), the state space equatons for the drect axs current and voltage loop can be derved as n (37). F d ( d d ) dt Fv d ( vd vd ) dt K r K K d dt F K R 1 K K d v dt F p p d d L L L d d F d vp v vp d v d RC C C v d vd F vd (36) (37) Kp r K KvpKp KvKp CKp K vpkp L L L L L L 1 0 K K 0 0 C 0 K 0 vp v vp 1 d KvpR Kv d Kvp F 0 d RC C F d C v d v d d F 1 0 vd F v d dt vd q CKp Kp r K K vpkp KvK p q KvpK p vq 0 F q L L L L L F q L v q v q 0 0 C F Kvp K v 0 K vp vq Fv q KvpR 1 K K v vp RC C C (40) Recall that the outer loop of the control structure n Fg. 11 regulates the AC voltage at load and sets the reference currents ( d and q ) to the nner current loop. The nner current loop regulates the load current and prevents overloadng of the converter, and t also generates the frst verson modulatng sgnals {m ab, m bc, m ca }, whch wll be modfed to {m a, m b, m c } and then {d a, d b, d c } for the modulator to generate the gatng sgnals for the swtchng devces. Snce the proposed converter holds the same structure n the SRF for all frequences wth nω (where n=±1, ±, ±3 ) rotatonal rate under balanced condtons. Thus, the second order dstorton problem can be solved by addng an elmnatng loop n -ω SRF that forces ts d-q components to zero as shown n Fg. 11. Note that the decouplng control block for the elmnatng loop s the same as that of the fundamental voltage and current n Fg. 11. Low pass flters (LPFs) are employed to acheve the d-q components under each frequency. The output of the supplementary loop that suppresses the second harmonc s added to the fundamental voltage and current loop that responsble for the power transfer between converter AC and DC sdes. Based on the proposed desgn scheme, t s to be expected that the space vector modulaton (SVM) method s also applcable to the ACVD converter (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 8

9 /TPEL , IEEE Transactons on Power Electroncs B. Control Desgn for Rectfer and Grd-connected Inverter Modes For completeness, the control dagram for the proposed converter n rectfer/grd-connected nverter mode s depcted n Fg. 1, where the outer control layers that generate the reference currents for the nner current controllers are to be determned by the operaton crcumstance and control target. In rectfer mode, unt power factor should be of concerned, thus quadrature current command s set to zero, whle the drect current s decded by the DC voltage controller. In dstrbuted energy resource (DER) applcatons where energy management s necessary, the actve power (DC sde voltage) and reactve power control layer wll generate the references for d-axs and q-axs currents respectvely. If the DER nterfacng nverter s connected to local mcrogrd, then voltage support functon may be needed. In ths case, the AC voltage n the pont of common couplng (PCC) should be controlled n outer layer [6, 7]. Fg. 1 Control structure n rectfer/grd-connected nverter mode:. two layers decouplng control; overvew of the control dagram ncludng the second order elmnatng loop. Takng the rectfer mode for example, the transfer functons for the two layers controller can be derved as follows. Rearrangng (30) nto (41) for smplfcaton, n whch terms {γ d, γ q } and η can be obtaned from the PI controllers n the close loop system. d 1 r d d d dt q L q L q dv 1 v dt Cd RdCd (41) v m v L K ( ) K ( ) dt d d gd q p d d d d v m v L K ( ) K ( ) dt (4) q q gq d p q q q q d md m q Kvp ( v v ) Kv ( v v ) dt q From (41), (4) and the defnton n (43), the state space equatons for the drect current control loop and DC voltage regulaton loop can be derved n (44). F d ( d d ) dt (43) Fv ( v v ) dt Kp r K K p d d d L L L d F dt d F d (44) KvpRd 1 K K v vp d v v R v dcd C d Cd dt F v F v In (41), snce the quadrant axs has the same structure wth drect axs, the transfer functons can be equvalently acheved as n (45). G K sk d q p d q K s( r Kp ) s L v v vp Gv v Kv s(1/ Rd Kvp ) s Cd K sk (45) Snce the q-axs reference s to be zero, the actual value of quadrature current s very small. Based on ths approxmaton, the drect current controller reference and the modulatng sgnal nto the PWM module s then shown n (46), whch s n accordance wth Fg. 1. U v L d d gd q U v L q q gq d d (46) The global state space equatons for the d-q decouplng control of the proposed rectfer system are then clarfed n (47). K r K K K K 0 0 L L L L Kvp Kv F d Kp r K d q L L dt F q v F K R 1 K RdCd Cd p K vp p v p d d v vp d v KvpK p L K vp F d 0 q v F q 0 v F v Kvp C d 1 (47) The outer layer wth actve power controller, reactve power controller or DER DC voltage controller stuatons can be solved by the proposed state space approach smlarly. The overall control scheme ncludng the second order current elmnaton s demonstrated n Fg (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 9

10 /TPEL , IEEE Transactons on Power Electroncs VI. EXPERIMENTAL VERIFICATION In attempt to substantate the dscussons and analyss presented n prevous sectons, a.5kva prototype of the three-phase ACVD converter n Fg. s constructed wth the followng specfcatons: 00V DC-lnk voltage; AC sde phase voltage of 170V-3Φ (peak value); 10kHz swtchng frequency (f s ); 470μF DC capactance (C d ); mh IBBC nductance (L 1 ); 10 μf IBBC capactance (C 1 ); 5mH AC sde nductance (L ); and 10 μf AC sde capactance C. In ths case, the maxmum AC output phase voltage s 00V. Compared wth the 400V voltage stress for conventonal VSC, the IGBT voltage stresses n ACVD converter are fluctuant around 400V wth an AC component equal to output voltage (ths fluctuant voltage can sgnfcantly reduce the capactor sze). The AC sde capactor voltage and AC sde nductor current are equal to the output voltage and output current respectvely. In ths demonstraton, the Texas Instrument DSP TMS30F8335 s used for dgtal mplementaton of the modulaton and control systems n ths paper. Intally, ths prototype s operated n nverson mode to demonstrate ts ablty to cope wth dfferent power factors (unty, leadng and laggng power factors). The footprnt of the tested prototype s shown n Fg. 13. To demonstrate the effectveness of the ntegraton desgn of L 1 and L as dscussed n secton III, a low power ntegrated magnetc nductor s bult as shown n Fg. 13 and tested when one of ts phases s operated as a sngle-phase standalone nverter from 50V DC-lnk wthout ncorporaton of second harmonc compensaton loop. The voltage and current waveforms of the IBBC are shown n Fg. 14. The results n Fg. 14 have shown that the ntegrated desgn of the two nductors L 1 and L s able to work ndependently n one core wthout any notceable performance degradaton. Therefore, the magnetc ntegraton technque s to be an effectve soluton n confne space applcatons where compact hardware desgn s preferred. Observe that the open loop output voltage and ts spectrum n Fg. 15 exhbt certan amount of second order harmonc, whch s n lne wth the prevous analyss. In Fg. 15, the zero-crossng pont drfts by 0.4ms and 3.7% of second harmonc can be observed from Fg. 15. Ths dstorton s expected to be aggravated as the power ncreases, necesstatng the ncorporaton of the second order harmonc mtgaton mechansm wthn the converter control loop. Fg. 14 Voltage and current waveforms of the state varables (5ms/dv):. IBBC nductor current (5A/dv) and IBBC capactor voltage (0V/dv);. Voltage across the two wndngs n the ntegrated magnetc component (50V/dv). Fg. 13 Photographs of. prototype for the power crcut of the proposed (three-phase) and ts drvers and. ntegrated desgn of magnetc parts (L 1 and L ). Fg. 15 Open loop output voltage wth second order harmonc dstorton:. output voltage waveform (0V/dv, ms/dv);. dstrbuton of the base band harmoncs. In order to elmnate the second harmonc from the output voltage (thus, the output current), the control strategy depcted n Fg. 11 and nvolvng both fundamental regulaton (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 10

11 /TPEL , IEEE Transactons on Power Electroncs and harmonc elmnaton s adopted. Ths tme, the proposed converter s operated n a three-phase confguraton. synchronzed at double frequency of the PWM generator. In ths way, the extra samples can compensate the asymmetrc devaton from the actual value and elmnate the DC bas. Fg. 17 shows the output lne-to-lne voltage and threephase currents obtaned from standalone operaton of the proposed converter n nverson mode. The THD for the voltage and current waveforms n Fg. 17 that obtaned from the FFT analyss are both lower than 1%, whch are expected to meetng the IEEE and IEC harmonc standards. Besdes, the peak lne-to-lne voltage of 95V s acheved from 00V DClnk, whch s beyond the DC utlzaton of 0.866pu for conventonal two-level VSC. Ths confrms the clam made n ths paper regardng the extended output voltage range of the proposed converter. Fg. 16 ADC synchronzaton for asymmetrc rpple compensaton. Fg. 17 Output waveforms for Standalone nverter mode (ms/dv):. lne-to-lne voltage (100V/dv); lne current under Ω resstve load (5A/dv). Fg. 16 shows the ADC synchronzaton scheme employed to compensate the asymmetrc devaton from average value durng postve and negatve half cycles. r p and r n are the reference values wth 180 degree apart, whle S p and S n are the state varables accordngly. The ADC tme t sa wll cause some drft from the md-pont. Snce the voltage/current slopes n the postve half cycle and negatve half cycle are asymmetrc for the proposed ACVD converter, some DC bas wll appear when mcro-controller samples one pont (mult-tmes) per swtchng cycle. In another word, samplng process must strctly obey the Shannon prncple, whch demands the samplng speed to be at least two tmes of swtchng frequency. Consequently, the ADC module s suggested to be (c) Fg. 18 Phase voltage/current waveforms of the ACVD-VSC under dfferent load condtons (5ms/dv):. phase voltage (100V/dv) and phase current (10A/dv) wth Ω resstve load;. phase voltage (100V/dv) and phase current (5A/dv) wth Ω +100μF capactve load; (c). phase voltage (100V/dv) and phase current (10A/dv) wth 15Ω +30mH nductve load (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 11

12 /TPEL , IEEE Transactons on Power Electroncs Fg. 18-(c) are presented to demonstrate the operablty of the proposed ACVD converter as slanded nverter wth resstve, capactve and nductve loads. These plots have shown that ths converter s able to operate under these operatng condtons, wthout any notceable dffculty or deteroraton n ts performance. Fg. 19 presents the snapshot of the load neutral pont voltage relatve to ground whch s fxed at negatve DC bus. It s observed that the CM voltage has no DC component and holds b-polar nature that swtches around zero (real ground). Ths reduces the nsulaton requrement on the load connected to the AC sde of ths converter as prevously stated. The energy converson effcency of the proposed converter as standalone nverter wth resstve load s assessed compared wth two-level nverter wth the same DC-lnk voltage, modulaton ndex and power ratng. Fg. 19 has shown the effcency comparson between the two converters. It s seen that the overall effcency of the ACVD nverter s margnally lower than the two-level nverter. Ths s because the current stresses are nearly the same for the two converters n ths applcaton. Fg. 0 Grd voltage (100V/dv), phase current (5A/dv) and DC output voltage (100V/dv) for ACVD rectfer wth 47Ω load (5ms/dv). Based on the results obtaned for nverter and rectfer operatons demonstrated n ths secton, the bdrectonal operaton ablty of the proposed ACVD converter s proved. It can be summarzed that the proposed ACVD converter s qualfed as a four-quadrant voltage source converter under varous condtons wth extended AC voltage output range, hgh power densty (twce of the output of the two-level topology from the same nput DC lnk), and hgh converson effcency. Besdes, the CM voltage can be suppressed to zero DC component. Although extra current s generated from IBBC, the output power can be twce of that n two-level converter snce the AC output voltage can be doubled, whch means there s no apprecable degradaton on effcency performance for the ACVD-VSC. Fg. 19 CM voltage and effcency examnaton for proposed converter:. CM voltage between DC ground and AC neutral (100V/dv, 0μs/dv);. effcency performance for standalone nverter mode. The feasblty of proposed converter for unty power factor rectfer applcaton s also tested usng the same prototype n Fg. 13. The AC nput voltage s 150V-3Φ (peak value), and DC output voltage s regulated at 00V wth resstance of 47Ω. In ths demonstraton, the control system for rectfer operaton depcted n Fg. 1 s used. The DC output voltage, nput phase current and grd voltage waveforms are dsplayed n Fg. 0. It can be observed that the nput AC current s n phase wth grd voltage (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE VII. CONCLUSIONS In ths paper, the three-phase voltage source converter wth AC sde voltage-doublng and DC common mode voltage suppresson features s proposed. Due to the ntroduced IBBC, the DC-lnk utlzaton s extended to 1pu on the phase voltage (twce of that n two-level voltage source converter). Consequently, the szes of DC-lnk capactor and nterfacng transformer are greatly dmnshed. Due to the nherent ground on the negatve termnal of DC-lnk, the DC component n CM voltage seen from the AC sde neutral pont can be avoded. It has been shown that relance of the proposed converter on IBBC to synthesze negatve half of the output voltage ntroduces second order harmoncs n the AC sde voltage and current when operated n open loop. The d-q SRF models of the proposed converter when operated n slandng or as a grd connected converter are presented, whch are n further used to desgn the necessary control loops for fundamental power transfer and elmnaton of the second order harmonc dstortons observed durng open loop operaton. Ths paper also descrbed the converter operatng prncple and bref assessments of the voltage and current stresses on the semconductor swtches of the proposed converter. Expermental results have substantated the clamed attrbutes of the proposed ACVD-VSC, ncludng ts four-quadrant operaton. REFERENCES [1] T. Fredl, J. W. Kolar, J. Rodrguez, and P. W. Wheeler, "Comparatve Evaluaton of Three-Phase AC-AC Matrx Converter 1

13 /TPEL , IEEE Transactons on Power Electroncs and Voltage DC-Lnk Back-to-Back Converter Systems," Industral Electroncs, IEEE Transactons on, vol. 59, pp , 01. [] J. W. Kolar, T. Fredl, J. Rodrguez, and P. W. Wheeler, "Revew of Three-Phase PWM AC-AC Converter Topologes," Industral Electroncs, IEEE Transactons on, vol. 58, pp , 011. [3] X. Changlang, Z. Faqang, W. Zhqang, and H. Xangnng, "Equvalent Swtch Crcut Model and Proportonal Resonant Control for Trple Lne-Voltage Cascaded Voltage-Source Converter," Power Electroncs, IEEE Transactons on, vol. 8, pp , 013. [4] S. Rodrgues, R. T. Pnto, P. Bauer, and J. Perk, "Optmal Power Flow Control of VSC-Based Multtermnal DC Network for Offshore Wnd Integraton n the North Sea," Emergng and Selected Topcs n Power Electroncs, IEEE Journal of, vol. 1, pp , 013. [5] Z. Changzheng, D. Shaowu, and C. Qaofu, "A Novel Scheme Sutable for Hgh-Voltage and Large-Capacty Photovoltac Power Statons," Industral Electroncs, IEEE Transactons on, vol. 60, pp , 013. [6] J. Chvte-Zabalza, Rodr, x, M. A. guez Vdal, P. Izurza-Moreno, G. Calvo, et al., "A Large Power, Low-Swtchng-Frequency Voltage Source Converter for FACTS Applcatons Wth Low Effects on the Transmsson Lne," Power Electroncs, IEEE Transactons on, vol. 7, pp , 01. [7] G. P. Adam, K. H. Ahmed, S. J. Fnney, K. Bell, and B. W. Wllams, "New Breed of Network Fault-Tolerant Voltage-Source-Converter HVDC Transmsson System," Power Systems, IEEE Transactons on, vol. 8, pp , 013. [8] J. Beerten, S. Cole, and R. Belmans, "Modelng of Mult-Termnal VSC HVDC Systems Wth Dstrbuted DC Voltage Control," Power Systems, IEEE Transactons on, vol. 9, pp. 34-4, 014. [9] O. S. Senturk, L. Helle, S. Munk-Nelsen, P. Rodrguez, and R. Teodorescu, "Power Capablty Investgaton Based on Electrothermal Models of Press-Pack IGBT Three-Level NPC and ANPC VSCs for Multmegawatt Wnd Turbnes," Power Electroncs, IEEE Transactons on, vol. 7, pp , 01. [10] F. Wanmn, R. Xnbo, and W. Bn, "A Generalzed Formulaton of Quarter-Wave Symmetry SHE-PWM Problems for Multlevel Inverters," Power Electroncs, IEEE Transactons on, vol. 4, pp , 009. [11] U. T. Sham and H. Akag, "Identfcaton and Dscusson of the Orgn of a Shaft End-to-End Voltage n an Inverter-Drven Motor," Power Electroncs, IEEE Transactons on, vol. 5, pp , 010. [1] U. T. Sham and H. Akag, "Expermental Dscussons on a Shaft Endto-End Voltage Appearng n an Inverter-Drven Motor," Power Electroncs, IEEE Transactons on, vol. 4, pp , 009. [13] T. Maetan, S. Mormoto, K. Yamamoto, Y. Isomura, A. Watanabe, and K. Nakano, "Shaft voltage comparson between grounded and ungrounded brushless DC motors wth nsulated rotor drven by PWM nverter," n Electrcal Machnes and Systems (ICEMS), 01 15th Internatonal Conference on, 01, pp [14] Y. Bo, L. Wuhua, G. Yunje, C. Wenfeng, and H. Xangnng, "Improved Transformerless Inverter Wth Common-Mode Leakage Current Elmnaton for a Photovoltac Grd-Connected Power System," Power Electroncs, IEEE Transactons on, vol. 7, pp , 01. [15] G. Yunje, L. Wuhua, Z. Y, Y. Bo, L. Chushan, and H. Xangnng, "Transformerless Inverter Wth Vrtual DC Bus Concept for Cost- Effectve Grd-Connected PV Power Systems," Power Electroncs, IEEE Transactons on, vol. 8, pp , 013. [16] J. W. Shn, H. Shn, G. S. Seo, J. I. Ha, and B. H. Cho, "Low-Common Mode Voltage H-Brdge Converter wth Addtonal Swtch Legs," Power Electroncs, IEEE Transactons on, vol. 8, pp , 013. [17] H. Akag and T. Doumoto, "An approach to elmnatng hghfrequency shaft voltage and ground leakage current from an nverterdrven motor," Industry Applcatons, IEEE Transactons on, vol. 40, pp , 004. [18] Dura, x, M. J. n, J. Preto, and F. Barrero, "Space Vector PWM Wth Reduced Common-Mode Voltage for Fve-Phase Inducton Motor Drves Operatng n Overmodulaton Zone," Power Electroncs, IEEE Transactons on, vol. 8, pp , 013. [19] C. C. Hou, C. C. Shh, P. T. Cheng, and A. M. Hava, "Common-Mode Voltage Reducton Pulsewdth Modulaton Technques for Three- Phase Grd-Connected Converters," Power Electroncs, IEEE Transactons on, vol. 8, pp , 013. [0] Y. Otan, T. Isobe, and R. Shmada, "Control and desgn prncple of a soft-swtchng boost to ac converter wthout smoothng capactor usng a MERS pulse lnk concept," n Energy Converson Congress and Exposton (ECCE), 011 IEEE, 011, pp [1] W. Wemn, H. Yuanbn, and F. Blaabjerg, "An LLCL Power Flter for Sngle-Phase Grd-Ted Inverter," Power Electroncs, IEEE Transactons on, vol. 7, pp , 01. [] K. Ilves, A. Antonopoulos, S. Norrga, and H. P. Nee, "Steady-State Analyss of Interacton Between Harmonc Components of Arm and Lne Quanttes of Modular Multlevel Converters," Power Electroncs, IEEE Transactons on, vol. 7, pp , 01. [3] J. D. Van Wyk, F. C. Lee, L. Zhenxan, R. Chen, W. Shuo, and L. Bng, "Integratng actve, passve and EMI-flter functons n power electroncs systems:a case study of some technologes," Power Electroncs, IEEE Transactons on, vol. 0, pp , 005. [4] Z. Y, L. Wuhua, D. Yan, and H. Xangnng, "Analyss, Desgn, and Expermentaton of an Isolated ZVT Boost Converter Wth Coupled Inductors," Power Electroncs, IEEE Transactons on, vol. 6, pp , 011. [5] L. Wuhua, L. Peng, Y. Huan, and H. Xangnng, "Three-Level Forward-Flyback Phase-Shft ZVS Converter Wth Integrated Seres- Connected Coupled Inductors," Power Electroncs, IEEE Transactons on, vol. 7, pp , 01. [6] Q. Shafee, J. M. Guerrero, and J. C. Vasquez, "Dstrbuted Secondary Control for Islanded Mcrogrds - A Novel Approach," Power Electroncs, IEEE Transactons on, vol. 9, pp , 014. [7] Y. A. R. I. Mohamed, H. H. Zeneldn, M. M. A. Salama, and R. Seethapathy, "Seamless Formaton and Robust Control of Dstrbuted Generaton Mcrogrds va Drect Voltage Control and Optmzed Dynamc Power Sharng," Power Electroncs, IEEE Transactons on, vol. 7, pp , 01. Peng L receved the B.Sc. and M.Sc. degree n Appled Power Electroncs and Electrcal Engneerng from Zhejang Unversty, Hangzhou, Chna, n 009 and 01, respectvely. He s currently pursung the Ph.D. degree n Department of Electroncs and Electrcal Engneerng, Unversty of Strathclyde, Glasgow, UK. Hs research nterests nclude the appled power electroncs n AC and DC power networks. G.P. Adam (M 1) receved a frst class BSc and MSc from Sudan Unversty for Scence and Technology, Sudan n 1998 and 00 respectvely; and. a PhD n Power Electroncs from Unversty of Strathclyde n 007. He has been workng as a research fellow wth Insttute of Energy and Envronment, Unversty of Strathclyde n Glasgow, UK, snce 008. Hs research nterests are fault tolerant voltage source converters for HVDC systems; control of HVDC transmsson systems and mult-termnal HVDC networks; voltage source converter based FACTS devces; and grd ntegraton ssues of renewable energes. Dr Adam has authored and co-authored several techncal reports, and journal and conference papers n the area of multlevel converters and HVDC systems, and grd ntegraton of renewable power. Also, he s actvely contrbutng to revewng process for several IEEE and IET Transactons and Journals, and conferences. Dr Adam s an actve member of IEEE and IEEE Power Electroncs Socety. Yhua Hu (M 13) receved the B.S. degree n electrcal motor drves n 003, and the Ph.D. degree n power electroncs and drves n 011, both from Chna Unversty of Mnng and Technology, Jangsu, Chna. Between 011 and 013, he was wth the College of Electrcal Engneerng, Zhejang Unversty as a Postdoctoral Fellow. Between November 01 and February 013, he was an academc vstng scholar wth the School of Electrcal and Electronc Engneerng, Newcastle Unversty, Newcastle upon Tyne, UK (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 13

14 /TPEL , IEEE Transactons on Power Electroncs He s currently a research assocate wth the Department of Electronc & Electrcal Engneerng, Unversty of Strathclyde, Glasgow, UK. He has publshed more than 30 techncal papers n leadng journals and conference proceedngs. Hs research nterests nclude PV generaton system, DC- DC/DC-AC converters, and electrcal motor drves. Derrck Hollday has research nterests n the areas of power electroncs, electrcal machnes and drves. In 1995 he obtaned the degree of PhD from Herot Watt Unversty and, snce then, has held full-tme academc posts at the Unverstes of Brstol and Strathclyde. He has authored or co-authored over 70 academc journal and conference publcatons. He s currently leadng ndustrally funded research n the feld of power electroncs for HVDC applcatons, and s convestgator on research programmes n the felds of photovoltac systems and the nterface of renewable energy to HVDC systems. B.W. Wllams receved the M.Eng.Sc. degree from the Unversty of Adelade, Australa, n 1978, and the Ph.D. degree from Cambrdge Unversty, Cambrdge, U.K., n After seven years as a Lecturer at Imperal College, Unversty of London, U.K., he was apponted to a Char of Electrcal Engneerng at Herot-Watt Unversty, Ednburgh, U.K, n He s currently a Professor at Strathclyde Unversty, UK. Hs teachng covers power electroncs (n whch he has a free nternet text) and drve systems. Hs research actvtes nclude power semconductor modellng and protecton, converter topologes, soft swtchng technques, and applcaton of ASICs and mcroprocessors to ndustral electroncs (c) 013 IEEE. Translatons and content mnng are permtted for academc research only. Personal use s also permtted, but republcaton/redstrbuton requres IEEE 14