Design Of A Rceat Architecture For Detecting Multi- Bit Error In RFID

Transcription

1 Design Of A Rceat Architecture For Detecting Multi- Bit Error In RFID Indugula Anusha Devi 1, B. Bala Krishna 2,V N M Brahmanandam 3 1M.Tech student,2 Assistant Professor,3Assistant Professor V.S.Lakshmi Engineering College for Women, Kakinada,India id: anushaindugula@gmail.com Abstract: Radio Frequency Identification (RFID) plays an important role in Warehouse Management, especially during the automatic identification of items. Unfortunately, a warehouse environment has electromagnetic interferences causing read failures in the RFID system. Here, we will considering networking environment, the cyclic redundancy check is widely utilized to determine whether error have been introduced during transmission over physical links. Cyclic redundancy check is extensively used for encoding and decoding communication channel burst errors, where a transient fault causes several adjacent data errors. In this method, the transmitter divides of the message by an agreed-upon polynomial called the generator and concatenates the calculated residue to the message. The receiver divides what it receives by the generator again. A zero residue indicates error-free transmission and a nonzero residue is interpreted as an error. In this paper, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) or Radio Frequency Identification (RFID) Class 0 U HF tag. The RCEAT architecture consists of two main subsystems PreRCEAT and PostRCEAT. The proposed system is designed using Verilog HDL in FPGA SPARTAN 6 device, which has achieved a good validation. The system is simulated using Modelsim and synthesized using Xilinx Synthesis Technology. Key Terms: RFID, PreRCEAT, PostRCEAT, Base Band Processor I. Introduction In networking environment, Cyclic Redundancy Check (CRC) is required method for detecting error when the data is transmitted in high speed data transmission. In this method used periodic recursive codes to encode messages by adding a fixed length check value for the purpose of error detection in many networks in communications. CRCs are based on the theory of cyclic error-correcting codes. Cyclic codes are not only simple to implement but have the benefit of being particularly well suited for the detection of burst errors, contiguous sequences of erroneous data symbols in messages. This is important because burst errors are common transmission errors in many communication channels, including magnetic and optical storage devices. Cyclic redundancy check is commonly used in data communication and other fields such as data storage, data compression, as a vital method for dealing with data errors. Usually, the hardware implementation of CRC computations is based on the linear feedback shift registers (LFSRs), which handles the data in a serial way. Though, the serial calculation of the CRC codes cannot achieve a high throughput. In contrast, parallel CRC calculation can significantly increase the throughput of CRC computations. For example, the throughput of the 32-bit parallel calculation of CRC- 32 can achieve several gigabits per second. However, that is still not enough for high speed application such as Ethernet networks. A possible solution is to process more bits in parallel; Variants of CRCs are used in applications like CRC-16 BISYN protocols. CRC- 32 in Ethernet for error frame detection, CRC-8 in ATM, CRC- CCITT in X-25 protocol, disc storage, SDLC.We present here a novel collision resolution protocol which allows the reader to obtain the ID from each tag within its read range, while the computational and memory requirement for each tag is minimal. In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. The CRC calculation consists of an iterative process involving Exclusive-ORs and shift register which is executed much faster in hardware compare in software.in addition for reader to communicate with the multiple tags, an anti-collision technique is required. Page 1388

2 The technique is to coordinate the communication between the reader and the tags. The common deterministic anti- collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms. However this technique has longer identification time which dependents on the number of existing tag and the identification bit (ID) length. RFID(Radio-Frequency Identification) technology has drawn a swirl of attention in the past few years as it helps identify objects and people in a fast, accurate and inexpensive way. It has been applied into many areas, including passports, transportation payment, product tracing, automotive as well as animal identification etc. Nowadays the applications of RFID are increasing rapidly, including supply chain management, access control to buildings, public transportation, open-air events, airport baggage, and so on. To meet the market requirements, the preferred RFID system must exhibit features like low cost, long operation range and high data rate, requiring a small and low-voltage/low- power integrated circuits. II. RFID System The abbreviation RFID stands for radio frequency identification, in which the information is carried by radio waves. RFID is an automatic identification method, relying on storing and remotely retrieving data using devices called RFID tags or transponders. An RFID tag is an object that can be applied to or incorporated into a product or person for the purpose of identification and tracking using radio waves. Some tags can be read from several meters away and beyond the line of sight of the reader. RFID systems are composed of three key components. may be of any length. In practice, a 96 bit ID would suffice for most applications. Most RFID tags, on the whole contain at least two parts. One is an integrated circuit for storing and processing information, modulating and demodulating a (RF) signal, and other specialized functions. The second is an antenna for receiving and transmitting the signal. RFID tags consist of a small microchip attached to an antennae or other coupling element. The tag communicates via radio frequencies (RF) with a transceiver, or tag reader. The tag ID may be read automatically: without line of sight, through non-conducting material such as cardboard or paper, at a rate of several hundred reads per second and from a distance of several meters. Since tags typically are silicon-based microchips, functionality beyond simple identification may be incorporated into tag designs. This functionality might range from integrated sensors to read/write storage to encryption and access control support. To communicate, tags respond to queries generating signals that must not create interference with the readers, as arriving signals can be very weak and must be differentiated. Besides backscattering, load modulation techniques can be used to manipulate the reader's field. Typically, backscatter is used in the far field, whereas load modulation applies in the near field, within a few wavelengths from the reader. Typically, backscatter is used in the far field, whereas load modulation applies in the near field, within a few wavelengths from the reader. RFID systems operate according to one of two basic procedures: a.full Duplex or Half Duplex b.sequential Procedure A. Operating principle of RFID system Figure 1: RFID system components RFID transponders, or tags, carry object identifying data. This data may include the manufacturer, brand, model and a unique serial number. Collectively, this data is often referred to as the tag s identity, or ID. An ID An Interrogator receives information from a Tag by transmitting an unmodulated RF carrier and listening for a backscattered reply. Tags communicate information by backscatter-modulating the amplitude and/or phase of the RF carrier. The encoding format, selected in response to Interrogator commands, is either FM0 or Miller modulated subcarrier. The communications link between Interrogators and Tags is half-duplex, meaning that Tags shall not be required to demodulate Interrogator commands while backscattering. A Tag shall not respond using full-duplex communications to a mandatory or optional command. Page 1389

3 Figure 2 : Architecture of the RFID tag RFID tag chip consists of a power reception system, an RF analog module, an EEPROM and a baseband-processor, shown in figure.2.3. The figure 2.4 shown above is the block diagram of a UHF RFID tag system. The basebandprocessor is one of the major and most important parts of the tag chip, since it not only implements the slotted aloha random anti-collision algorithm and authorization scheme, but also executes read/write operation of EEPROM. As we know, the power consumption of analog circuit and EEPROM is very difficult to reduce. Even more, besides the power consumption, the efficiency of the RF front-end rectifier prefers lower output DC voltage. So it s very important to design a lowpower/low voltage baseband-processor to achieve maximum operation range. Figure 3: Block diagram of an RFID tag system B. Tag Identification A tag identification system consists of one reader and n tags. The reader is a powerful entity with abundant memory and computation power. On the other hand, the tags are limited in memory and computation power. There is a single communication channel between the reader and the tags. However, the tags are not able to exchange messages among each other. The reader can broadcast messages to the tags. Upon receiving a message, each tag can optionally send a response back to the reader. If only one tag responds, the reader receives the message. But if more than one tag respond, their messages would collide on the communication channel, and thus cannot be received by the reader. In this case, the reader detects a collision on the channel but nothing else. Each tag I 2 f1: ng has a unique ID string in f0; 1gk, where k is the length of the ID string. At the beginning, the reader does not know anything about the tags. Tag identification protocol species the algorithms for the reader and the tags, so that the reader can collect all the tag IDs. III. Working Principle of RFID Block Diagram The RCEAT architecture consists of two subsystem; PreRCEAT and PostRCEAT. In the PreRCEAT, the received messages are fed into the CRCremover module. These received messages will be separated into two; the received packet and the received CRC. These packet and CRC are sent to the CRC checker module for verification process. The CRC checker module recalculated the CRC of the received packet.cyclic Redundancy Check (CRC) is an errorchecking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. In networking systems a significant role of the Data Link layer is to convert the potentially unreliable physical link between two machines into an apparently very reliable link. This is achieved by including redundant information in each transmitted frame. Depending on the nature of the link and the data, one can include just enough redundancy to make it possible to detect errors and then arrange for the retransmission of damaged frames. The cyclic redundancy check or CRC is a widely used parity bit based error detection scheme in serial data transmission applications. This Page 1390

4 code is based on polynomial arithmetic. To compute the CRC of a message, another polynomial called the generator polynomial G(x) is chosen. The status-bit is removed from its packet and only the tag s ID will be output to the PostRCEAT In the PostRCEAT, the active tags are divided into a group of four for every Read cycle in order to reduce the number of iterations in the identification process. c The PostRCEAT reads all the ID bits at once regardless of its length. This is performed by vusing the word-by-word multiplexing. During the identification process the Fast- search module identifies the four tag s IDs simultaneously in one Read cycle which equal to a Tag clock cycle. The module firstly identifies the smallest ID bits until the largest one follows the Binary Tree with a maximum number of four leaves. IV. Simulation Results Figure 4: RFID BLOCK DIAGRAM To compute the CRC of a message, another polynomial called the generator polynomial G(x) is chosen. G(x) should have a degree greater than zero and less than that of the polynomial M(x).Another requirement for G(x) is a non-zero coefficient in the x0 term. This results in several possible options for the generator polynomial, and hence the need for standardization. In general, an n-bit CRC is calculated by representing the data stream as a polynomial M(x), multiplying M(x) by xn (where n is the degree of the polynomial G(x)), and dividing the result by a generator polynomial G(x). The resulting remainder is appended to the polynomial M(x) and transmitted. The complete transmitted polynomial is then divided by the same generator polynomial at the receiver end. If the result of this division has no remainder, there are no transmission errors. Mathematically, this can be represented. Then, this calculated CRC is compared with the received CRC. If the alues are same, means no error, the status- bit is set to its original value i.e. zero. Otherwise or there are errors in the packet, the status-bit is set to two. After that, this updated status-bit is appended to its respective packet. Finally, the packet with the updated status-bit is fed to the Status-checker module. The Status-checker module will check any errors in the incoming packets. If there are errors, then reset the slot of the respective packet to zero value. Otherwise; fill the slot of the packet with its respective ID. Verilog HDL codes for the RCEAT architecture have been successfully simulated and verified using the ModelSim XE II/Starter 6.4 tool. The following will discuss the Behavioral simulation waveforms for the selected ports in the RCEAT system as shown in Fig. 2. At the first Read cycle, for the received messages of 000C85844, A5, , and 0EA6095DF, the recalculated CRC of these messages are 5844, 50A5, 1231, and 95DF respectively. As a result, the calculated CRCs are equal to the received CRCs which are represented by the four bit of the least significant bit (LSB) of the messages. Since there are no errors in the received messages, the Statusbit of the packets are set to zero, which are represented by the sbit of the packets; 000C8, 00005, and 0EA60 respectively. Finally, the ID of these packets will be fed simultaneously to the PostRCEAT subsystem. Figure 5:Simulation results of crcremover Page 1391

5 Figure 9: simulation results of top module. Figure 6:simulation result of recalculated CRC Figure 10: FPGA Device V. Experimental Results Figure 7: Simulation results of fast search algorithm FPGA families power xc6slx45-3csg xc6slx4-3csg xc6slx75-3csg xc6slx9-3csg xc6slx16-3csg xc6slx45l-1lcsg Figure 8: Simulation result of parallel to serial conversion Table 1 Power Analysis Graph 1Comparison of Power for various logic families Page 1392

6 (CCNC), th IEEE, vol., no., pp.1-2, 9-12 Jan [2] Sangho, S. & Sin-Chong, P. (2008). Efficient RFID Anti-collision scheme with multi-collision reflected frame request th IEEE Consumer Communications and Networking Conference, p. 1-5, ISBN , Las Vegas, NV, United states, 1,2008, Inst. of Elec. and Elec. Eng. Computer Society, NJ , United States Table 2 Area Analysis [3] Song-sen, Y. et al, (2007). RFID Anti-collision algorithm Based on Bi-directional Binary Exponential Index. Proceedings of the IEEE International Conference on Automation and Logistics, pp , Jinan, China, August 2007, Inst. of Elec. and Elec. Eng. Computer Society, NJ [4] Myung, J. et al, (2006). Adapt ive Binary Splitting for Efficient RFID Tag Anti-Collision. IEEE Comm. Letters, vol. 10, no.3, (March 2006) page numbers ( ), ISSN: [5] J. Zhai and G. Wang, An anti-collision algorithm using two-functioned estimation for RFID tags, in Proc. ICCSA 05, LNCS 3483, pp , May 2005 Graph 2 Comparison of Area for various logic families VI. Conclusion A proposed Reliable and Cost Effective Anti-collision technique (RCEAT) is designed to achieve a reliable and cost effective identification technique of the tag. PreRCEAT checks error in the incoming packets using the CRC scheme. PostRCEAT identifies the error free packets using Binary Tree based technique. The result shows that the architecture has smaller cell area, power Consumption and number of gates. Therefore minimize the implementation and operating costs. References [1] Yan Sun; Min Sik Kim;, "A Pipelined CRC Calculation Using Lookup Tables," Consumer Communications and Networking Conference [6] EPC TM radio-frequency identification protocols class-1 generation 2 UHF RFID protocol for communications at 860MHz-960MHz Version 1.0.8, EPCglobal, Dec [7] Information technology automatic identification and data capture techniques - radio frequency identification for item management air interfacepart 6: parameters for air interface communications at MHz, \ISO/IEC FDIS , Nov [8] Vogt.,H. (2002). Multiple Object Identification with Passive RFID Tags IEEE International Conference on Systems, PP , ISSN: , Yasmine Hammamet, Tunisia, October 2002, Institute of Electrical and Electronics Engineers Inc., NJ [9] Engels, D. & Sarma S. (2001). The Reader Collision Problem, Technical Report MIT- AUTOID-WH007, Auto-ID Center, Nov Page 1393