CapSense Sigma-Delta Plus ADC Data Sheet

Transcription

1 1. CapSense Sigma-Delta Plus ADC User Module CapSense Sigma-Delta Plus ADC Data Sheet Copyright Cypress Semiconductor Corporation. All Rights Reserved. CSDADC PSoC Blocks API Memory (Bytes) Typical Pins (per Resources Digital Analog CT Analog SC Flash RAM External IO) CY8C24x94, CY8CLED04D03/04 Use of Flash, RAM, and pins varies by the number of sensors and configuration. PRS16-based user module with 1 sensor PRS8-based user module with 1 sensor Prescaler clock source with 1 sensor VC2 clock source user module with 1 sensor Each additional capsense button Static code and RAM increase when capacitive slider with 5 elements is used Each additional slider element Static code and RAM increase when slider diplexing is used Sliders*2 - For one or more fully configured, functional example projects that use this User Module go to Features and Overview Allows scanning CapSense sensors and measuring input voltages without using separate loadable configurationspsoc Express support Uses a Sinc N filter fully implemented in hardware to reduce CPU overhead and anti-alias requirements Supports a configuration that uses no digital blocks ADC features: Sigma-delta ADC with second order modulator Data in unsigned or signed 2 s complement formats Dynamically changed resolution to 10,12 and 14 bits Maximum sample rates of sps at 10 bit resolution, 7812 sps at 14-bit resolution Input range defined by internal and external reference options Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev. *B Revised February 12, 2009

2 Built-in Programmable Gain Amplifier with configurable gain and reference settings. CapSense features: Based on the robust CSD method Second order modulator provides superior SNR performance Scans 1 to 46 capacitive sensors Sensing possible with up to a 25-mm glass overlay Proximity detection to 30 cm with a wire-based sensor High immunity to AC mains noise, EMC noise, and power supply voltage changes Supports different combinations of independent and slide capacitive sensors Double slide sensor physical resolution using diplexing Increase slide sensor resolution using interpolation Touchpad support with two slide sensors Sensing support via high-resistive conductive materials (ITO films for example) Shield electrode support for reliable operation in the presence of water film or droplets Guided sensor and pin assignments using the CSDADC Wizard Integrated baseline update algorithm for handling temperature, humidity, and electrostatic discharge (ESD) events Easily adjustable operational parameters0 PC GUI application to support raw data monitoring and parameter optimization in real-time The CSDADC provides capacitance sensing using the switched capacitor technique with a sigma-delta modulator to convert the sensing switched capacitor current to digital code. Document Number: Rev. *B Page 2 of 74

3 V dd Clock source IMO CT Block R 2 VC1 4 SC Block BCAP Ph 1 Ph 2 PGA F 1 ACAP Sinc N filter Data R b C x C mod R 1 RefH Ref L F 2 V ss V ss AGND Capacitance Sensing Module IMO CT Block VC1 4 SC Block 1 SC Block 2 R 2 BCAP BCAP Analog Bus Mux PGA F 1 ACAP F 1 ACAP Sinc 2 filter Data PGA Reference R 1 RefH RefL F 2 RefH RefL F 2 Sigma-Delta ADC Module CSDADC Block Diagram Operation (Quick Start Guide) 1. Select and place user modules requiring dedicated pins (I2C and LCD for example), if used. Assign ports and pins as required. 2. Select and place the CSDADC User Module. 3. Right-click the CSDADC User Module to access the CSDADC Wizard. 4. Set sensor count, configuration, and pin assignments. 5. Set pins and global parameters. Read all parameter descriptions and follow requirements and guidelines. 6. Generate the application and switch to the Application Editor. 7. Adapt the sample code as required to implement independent sensors, sliding sensors, or a touchpad. 8. Connect the RS232 level translator or I2-USB bridge to the target board, and optimize the parameters using a GUI. 9. Change the CSDADC parameters and rebuild the application. Document Number: Rev. *B Page 3 of 74

4 10. Program the PSoC device and verify module operation.tune the CSDADC parameters to achieve a 5:1 SNR requirement as discussed in Signal-to-Noise Ratio Requirements for CapSense Applications AN2403. Functional Description The CSDADC provides a combination of capacitance sensing with ADC functionality for voltage measurement without using a separate loadable configurations. It saves code space by reusing modules common to both the CSD and ADC. You should use the CSDADC when you need both capacitance sensing and ADC functionality. Applications that require one or the other should use the CSD or the DELSIG ADC. A CSDADC implements capacitance sensing using the switched capacitor technique with a sigma-delta modulator (CSD) to convert the sensing switched capacitor current to a digital code. A CSDADC implements a sigma-delta ADC with a second order modulator and built-in preamplifier. Using a secondorder modulator produces a better SNR. This document provides basic information about the CSD and ADC operation. For detailed theory details, recomendations about setting CSD parameters, CSD use tips, and CSD troubleshooting please refer to the CSD, DELSIG, and PGA datasheets and associated application notes. If you have never used the CSD and ADC user modules before, you should read these documents before attempting to implement a solution with them. The following documents are recommended reading before you use the CSDADC User Module for the first time. CY8C24x94 Series PSoC Mixed Signal Array Technical Reference Manual, sections Two Column Limited Analog Digital Clocks IO Analog Multiplexer Understanding Switched Capacitor Analog Blocks AN2041 The following application notes are recommended after reading the CSDADC User Module documentation. Application notes can be found on the Cypress Semiconductor web site at CapSense Best Practices AN2394 Signal-to-Noise Ratio Requirements for CapSense Applications AN2403 Charting Tool to Debug CapSense Applications AN2397 EMC Design Considerations for PSoC CapSense Applications AN2318 Power Consumption and Sleep Considerations in Capacitive Sensing Applications AN2360 Layout Guidelines for PSoC CapSense AN2292 Software Implementation of a Universal Asynchronous Transmitter AN2399 Waterproof Capacitance Sensing AN2398 I2C-USB Bridge Usage - AN2352 The ADC Operation The CSDADC uses the DELSIG ADC with built-in PGA. The DELSIG User Module is an integrating converter, requiring from 64 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs invalidates the first two samples following the change. The DELSIG ADC is composed of three primary modules; a PGA, a second-order modulator, and a Sinc 2 Decimation Filter. Document Number: Rev. *B Page 4 of 74

5 CT Block SC Block 1 SC Block 2 VC1 4 R 2 BCAP BCAP Analog Bus Mux V IN PGA V OUT F 1 ACAP F 1 ACAP Sinc 2 filter Data RefH RefH PGA Reference R 1 RefL F 2 RefL F 2 V GND PGA Sigma-delta modulator Modulator bitstream filter The ADC block diagram Programmable Gain Amplifier The ADC is preceded by the programmable gain amplifier (PGA). This aplifier allows matching input signals range to the ADC signals range, giving better ADC dymamic range utilization. The PGA input comes from the analog bus, allowing it to be connected to external sources. It can be reconfigured to support internal signal sources as well. The PGA input signal can be referenced to the internal analog ground, V ss, or other selected references. The gain of the programmable gain amplifier is set by programming the selectable tap in a resistor array and the feedback tap in a continuous time analog PSoC block. You set the gain and reference in the device editor. The amplifier has the following transfer function. R 2 V OUT = ( V IN V GND ) V GND R 1 Equation 1 You can specify the reference as one of the following: A fixed value derived from an internal reference A value ratiometric to the supply voltage Analog ground An external input The input and output voltage ranges of the amplifier do not extend to the power supplies (i.e., they are not "rail-to-rail" opamps). The allowed input range is a combination of: Input limit Output limit Power supply voltage Analog ground value Selected gain Document Number: Rev. *B Page 5 of 74

6 Modulator The modulator is a 1-bit over-sampling circuit that represents the input voltage in terms of the density of 1 s and 0 s that it produces. The modulator output is reduced to the final sample rate by the low-pass decimation filter that converts multiple 1-bit samples into samples of higher resolution. In general, higher decimation rates (that is, higher oversample rates) can produce higher resolution results but other factors, such as the order of the modulator, also matter. A key benefit of Delta-Sigma converters is the noise shaping provided by the modulator. Normally, the quantization noise inherent in sampling a signal is more or less evenly distributed ( white ) in frequency between DC and one-half the sample frequency or Nyquist frequency. Simply put, the delta-sigma modulator shifts some of the quantization noise from lower into higher frequencies that are later attenuated by the decimation filter. A second-order modulator that requires two switched-capacitor analog PSoC blocks does a better job of noise shaping than the first-order modulator that only requires one analog PSoC block. At the highest decimation rate of 256X, a second-order modulator accounts for a 3.5- bit increase in the effective resolution compared to a first-order modulator. A second-order modulator is constructed by feeding the analog output of a first-order modulator into a similar PSoC block and modifying the feedback arrangement so that the 1-bit comparator output of the second block back into both blocks as illustrated above. Because the analog comparator buses run vertically in the columns of the analog PSoC block array, the blocks of a second order modulator must be positioned one above the other. The range of the DelSig ADC is established by ±V Ref. You set V Ref in the Global Resources window in PSoC Designer. For a fixed scale, V Ref is set to ±V Bandgap or for ±1.6 V Bandgap. For an adjustable scale, V Ref is set to ±Port 2[6]. For a supply ratiometric scale, V Ref is set to ±V DD /2. The complete list of options is given in the following table. Input Voltage Ranges for the Ref Mux Global Parameter Setting RefMux Setting Vdd = 5 Volts Vdd = 3.3 Volts (Vdd/2) ± BandGap 1.2 < V in < < V in < 2.95 (Vdd/2) ± (Vdd/2) 0 < V in < 5 0 < V in < 3.3 BandGap ± BandGap 0 < V in < < V in < 2.6 (1.6*BandGap) ± (1.6*BandGap) 0 < V in < 4.16 NA (2*BandGap) ± BandGap 1.3 < V in < 3.9 NA (2*BandGap) ± P2[6] (2.6 - V P2[6] ) < V in < (2.6 + V P2[6] ) NA P2[4] ± BandGap (V P2[4] - 1.3) < V in < (V P2[4] + 1.3) (V P2[4] - 1.3) < V in < (V P2[4] + 1.3) P2[4] ± P2[6] (V P2[4] -V P2[6] ) < V in < (V P2[4] +V P2[6] ) (V P2[4] -V P2[6] ) < V in < (V P2[4] +V P2[6] ) Sinc 2 Decimation Filter The response of the decimation filter is given by the following z-domain relation. Hz ( ) = 1 z n z 1 2, where n is the decimation level. Equation 2 The frequency domain transfer function plotted below normalizes the frequency so the output sample rate, F nom, equals1.0. The -3 db point occurs just above F nom and the zeros of the function occur at Document Number: Rev. *B Page 6 of 74

7 each integer multiple of F nom. Since the 1-bit sample rate is 64 to 256 higher than the nominal output rate, the Nyquist limit is 5 to 7 octaves above F nom, significantly reducing the requirements for an anti-alias filter. The 1-bit Nyquist frequency for a decimation rate of 256 is shown by the heavy vertical line at the right of the graph. Though higher decimation rates are possible, they contribute little additional benefit because of the noise floor of the device. In the case of the 12-bit topology, a second-order modulator with a decimation rate of 256, the resolution is limited by the signal-to-noise ratio. Sinc 2 Decimation Filter Magnitude Response, with -3 db Point and Nyquist Frequency The decimator operates in self-counting mode, without using additional timer block to form a decimation rate. The decimator implements the denominator of the transfer function by a double integrator operating at the 1-bit sample rate. The numerator is implemented by a double differentiator (second difference operator) that runs at the nominal output sample rate. Capacitance Physics Fundamentals Suppose there is a solitary conductive object that has a non-compensated charge, Q. This charge creates a static electric field outside the object. The potential ϕ is linearly proportional to the charge Q: Equation 3 Capacitance is the coefficient that links the object s potential ϕ with its charge Q. This coefficient depends only on the conductor s geometric dimensions. If the conductive object is covered with a dielectric, the object s capacitance depends on the dielectric characteristics and geometry. For example, for a solitary sphere with radius R covered with an isotropic material with a dielectric constant ε, the sphere s capacitance can be easy calculated with the following equation: C ϕ = = Q --- C 4πεε 0 R Equation 4 Document Number: Rev. *B Page 7 of 74

8 ε permittivity constant (8.85x F/m) ε relative permittivity of the dielectric material that covers the sphere For objects with arbitrary dimensions the capacitance calculation is difficult or impossible. In many cases, the capacitance is calculated using Equation 4 and some equivalent radius, R e. For example, for a rectangular box with orthogonal edge dimensions a, b, c, the equivalent radius R e can be defined as the arithmetic mean of its dimensions: a + b + c R e = Equation 5 This allows you to calculate the capacitance of an item based on its dimensions with suitable accuracy for practical evaluations. By substituting the a = 1.8m, b = 0.4m, c = 0.3m we can estimate the capacitance of the human body at 92 pf. This is very close to the 100 pf value used in the Human Body Model (HBM) for the electrostatic discharge (ESD) sensitivity testing. Any conductive object (even if it is not connected to any other objects) has its own capacitance that is determined by the object s geometry and dimensions. Humans, coils, metallic pens, and so on, all have their own capacitance. It is not necessary to connect a second capacitor terminal to anything (system ground, for example). But to use circuit theory for CapSense systems analysis, a second capacitor terminal can be connected to any net with a fixed potential (ground or power supply nets, for example). When other conductive, noncharged objects are located close to the conductive charged object, the electric field induces the charges on these objects to reduce the electric field intensity and increase the conductive object s capacitance. Two conductive items charged to equal but opposite charges form a capacitor. The most commonly used is a parallel plate capacitor. Its capacitance can be calculated using the following equation: C = εε 0 S d Equation 6 S plate area in square units d distance between plates Equation 6 is accurate only when the distance between plates is much less than the plate mechanical dimensions, therefore, electric field is considered located only between the plates. Capacitance can be easily calculated analytically only for simple electrode systems, such as plate, sphere, or cylinder capacitors. For arbitrary electrodes, system capacitance can be found by solving Poisson partial differential equation using numerical methods. Modern CAD field analysis tools (FELAB, ANSYS, and others) greatly simplify this work. The capacitance estimation is required in many real CapSense applications, where a complex electrodes/dielectrics combination is used and analytical equations do not provide sufficient for accuracy in practical use. In most CapSense applications, the sensing plate is covered by an insulation overlay. The overlay thickness and the dielectric constant value of the material determines the inter-capacitance between the sensing electrode and the human finger. For example, for a white goods application where the overlay is hardened glass with a dielectric constant of 7, the sensing zone diameter is 10 mm and the overlay thickness is 6 mm, we can estimate the sensor electrode-finger capacitance approximately (here the overlay thickness is on the same order as sensing zone diameter, so boundary effects have a noticeable influence) using Equation 6 to 1.0 pf. Taking into account that human capacitance is more than 100 pf, Document Number: Rev. *B Page 8 of 74

9 the sensing electrode-finger capacitance is a dominant factor in the capacitance sensing application s operation. Real application capacitance includes additional components that should be taken into account. Suppose we have an isolated PCB with a button sensing electrode. An example of this application can be a cell phone, a remote control, or other small device. The following main capacitance components are shown in the figure below: Finger-electrode capacitance, C fe. Values are pf, depending on electrode size and overlay thickness, and the dielectric constant of the electrode. Human capacitance, C h. Approximately pf. Board capacitance, C b. Value is pf for small boards without external connections (for example, a remote control) to more than 1000 pf when the device is connected to AC mains (for example, a mobile phone when attached to a charger or an externally powered stereo system). Board-human capacitance, C hb. Values are 1 20 pf depending on target board dimensions, insulation thickness, and hand locations. C x C fe Sensor PSoC C fe C hb C x = C hb C b C b C h C x <C fe C h A Touch Application Capacitance Model From the point of view of the PSoC device sensing touch capacitance, C x is a series of connections of the finger-electrode capacitance C fe with equivalent ground capacitance: C C x C h C = b hb C h C b C fe Equation 7 As can be seen from Equation 7, the equivalent touch capacitance C x is less than the finger-electrode capacitance C fe. This touch capacitance reduction is negligible in most CapSense applications, but needs to be taken into account for small, autonomous systems that can sometimes use external connections. Document Number: Rev. *B Page 9 of 74

10 The CapSense system should be able to detect small capacitance changes (C x = pf) and the presence of large parasitic capacitance ( pf). The parasitic capacitance components are the electrode s capacitance, capacitance between the sensing electrode and the ground plane, and the intercapacitance between neighboring traces on the PCB. The total capacitance that is measured by the CapSense system is the sum of parasitic C par and touch capacitances C x : C s = C x + C par Equation 8 Capacitance Measurement Operation The capacitance to code converter consists of four main parts: Sensing switched capacitor Second order sigma-delta modulator Modulator bit stream filter Clock source The decision logic is implemented in firmware. The firmware analyzes capacitance measurement, tracks the slow capacitance change due to environmental factors, and runs decision logic to detect button touches and calculate slider position. V dd Clock source IMO CT Block R 2 VC11 4 SC Block BCAP Sw 1 Ph 1 Ph 2 PGA F 1 ACAP Sinc N filter Data Sw 2 R b C x C mod R 1 RefH RefL F 2 V ss Sw. cap V ss Sw 3 AGND Sigma-delta modulator Modulator bitstream filter CSDADC Block Diagram Sensing Switched Capacitor The switches Sw 1 and Sw 2 operate in two nonoverlapping phases, Ph 1 and Ph 2. Break-before-make precharge switches are used for this. At phase Ph 1 (when clock signal is high) Sw 1 is on. At phase Ph 2 (when clock signal is low) Sw 2 is on. Sw1 and Sw2 are never on at the same time. Document Number: Rev. *B Page 10 of 74

11 V dd V dd Sw 1 Ph 1 = R c Sw 2 V Cmod V Cmod Ph 2 C s The Switched Capacitor is Equivalent to the Resistor Between the Power Supply and Modulator Input The sensing capacitor is charged to the supply voltage Vdd at phase Ph 1 and is discharged to the modulator capacitor C mod at phase Ph 2. The sensing switched capacitor is equivalent to the resistor R c with equivalent resistance value to: 1 R c = f s C s Equation 9 fs Sw1, Sw2 operation frequency. Refer to AN2041, Understanding Switched Capacitor Analog Blocks, for proof of the equation and valuable information about switched capacitor circuit operation. The current from the switched capacitor resistor flows to the sigma-delta modulator, charging the capacitor C mod. Sigma-Delta Modulator The modulator is formed by the modulation capacitor C mod, and a discharge resistor R b, PGA, the first order sigma-delta modulator, see figure below. The modulator capacitor voltage V Cmod is supplied to PGA, the PGA output is connected to first order sigma-delta modulator. The integrator output is passed to the syncronized comparator. The comparator output forms the modulator feedback loop, controlling both discharge resistor connection and reference voltage selection for the first order modulator. Combination of the first order sigma-delta modulator together with circuit Sw 3 C mod R b forms the second-order sigma-delta modulator. Document Number: Rev. *B Page 11 of 74

12 V dd CT Block R 2 VC1 4 SC Block BCAP R c V CMOD PGA V OUT F 1 ACAP Data R b C mod R 1 RefH RefL F 2 V ss AGND The Sigma-Delta Modulator with Equivalent Switched Capacitor Resistor R c The modulator math is not complex. The current via the switched capacitor resistor can be evaluated using the following equation: I c = C s f s ( V dd V Cmod ) Equation 10 The PGA output voltage relatively AGND ground is calculated by: V out = ( V Cmod V AGND ) K g Equation 11 K g the PGA gain. The sigma-delta modulator acts as voltage-to-duty cycle converter, the modulator duty cycle in the steady state can be calculated by the following equation: 1 d mod -- V out = V ref Equation 12 V ref = V RefH = V RefL By substituting Equation 11 to Equation 12 we can get the following modulator duty cycle dependance from modulator capacitor V Cmod voltage: 1 ( V d mod -- Cmod V AGND ) G PGA = V Ref Equation 13 Document Number: Rev. *B Page 12 of 74

13 The modulator output bit stream duty cycle d mod carries information about the sensing capacitor value. The averaged current via the bias resistor can be expressed as follows: I Rb = d mod V Cmod R b Equation 14 The sigma-delta modulator keeps these currents close to equal in average. By substituting can obtain: I c = I Rb, we d mod V Cmod = C R s f s ( V dd V Cmod ) b Equation 15 Equation 13 and Equation 15 form the equation set to calculate the modulator duty cycle as function of sensing capacitance value. Using formula to solve a quadratic equation, the solution can be written in the following form using definitions for calculations simplification: A K g 1 V C s f s R b ; B ; G -- AGND = = = K 2V ref 2 g ; M = B A V V dd ref Equation 16 b = A+ G; c = G A+ M d mod = b b c 4 Equation 17 A V V dd Cmod = d mod + A Equation 18 The maximum capacitance value C smax, which can be measured for given parameters set reflect situation when modulator duty cycle is equal to 1. In this case the PGA output voltage (relatively AGND potential) is equal to V ref. The PGA input voltage V Cmod max can be calculated as: V Cmodmax = V ref + V K AGND g Equation 19 Document Number: Rev. *B Page 13 of 74

14 By combining Equation 18 with Equation 19 and subsituting a maximum sensing capacitance C smax calculation: d mod = 1 V ref + V 1 K AGND C smax g = f s R b V V ref dd V K AGND g we get the following Equation for Equation 20 The figures below illustrate a modulator duty cycle dependance, modulation capacitor Cmod voltage value and duty cycle derivative from sensing capacitance for different feedback resistor values and PGA gain levels. As can be seen from these graphs, a transfer characteristic is somewhat non-linear, with linearity improvement with increasing a PGA gain level. Sensitivity becomes flatter as the gain level increases. However, setting a high gain level increases the noise value, so a compromise value must be selected. Document Number: Rev. *B Page 14 of 74

15 dmod k 1k 1.5k 2k Modulator Duty Cycle C, pf 2 Modulator Voltage Vcmod,V C, pf 0.08 Sensitivity 0.06 d' C, pf Modulator Duty Cycle, Modulator Capacitor Voltage and Duty Cycle Derivative vs. C s for Different Feedback Resistor Values. Document Number: Rev. *B Page 15 of 74

16 dmod Modulator Duty Cycle C, pf 2 Modulator Voltage 1.5 Vcmod,V C, pf Sensetivity d' C, pf Modulator Duty Cycle, Modulator Capacitor Voltage and Duty Cycle Derivative vs. C s for Different PGA Gain Values. Modulator Bit Stream Filter The modulator converts the capacitance to the output bit stream duty cycle. The duty cycle is measured using a Sinc n digital filter, based on the hardware decimator, available in the CY8C24x94 PSoC devices. The decimator is configured in different operation modes and configurations for optimal performance. Document Number: Rev. *B Page 16 of 74

17 When the PRS16 configuration is selected, the decimator is configured in single integration mode (sinc, or incremental filter). The decimation rate is set by the external timer. VC1 VC2 Timer From modulator VC1 4 Sinc filter Decision logic Bitstream Digital Filter for PRS16 Configuration One sample is formed each N m IMO cycles. The conversion interval is set with the external decimator capture timer period T s and software overflow counter that is used for hardware timer interval extension. If the software overflow counter is equal to N s, the sample conversion interval can be evaluated in the IMO cycles using: VC1, VC2 divider values T s capture timer period N s software counter value Modulator bitstream filter N m = VC1 VC2 T s N s Equation 21 The VC1 value is set in the user module API to get different sensor scanning speeds. The VC2 value is set to 4 so that the timer triggers an interrupt each 256 VC2 periods. The software overflow counter Ns is changed in the user module API to get different scanning resolutions. For example, set it to 2 for 9-bit resolution or to 256 for 16-bit resolution. The PRS8, prescaler or VC2 precharge clock configurations use the double integration mode of the decimator called as a Sinc2 filter. The internal decimator counter is used to set the decimation ratio and resolution, so no external timer is required here. This saves one digital block. The decimator is clocked from the VC1 clock internally divided by four. The VC2 clock is not used. VC1 VC1 4 From modulator Sinc 2 filter Decision logic Modulator bitstream filter Bitstream Digital Filter for PRS8, Prescaler, VC2 Configurations Document Number: Rev. *B Page 17 of 74

18 In the PRS8, prescaler or VC2 clock configurations the only allowable resolutions are 10, 12, and 14 bits, and are determined by the supported decimation ratio. The decimator forms one sample each 128, 256, and 1024 VC1 clock intervals at these resolutions. The decimator generates an interrupt after the sample conversion is finished. The decimator interrupt requests are processed using the Analog Column 1 interrupt vector. Because the Sinc 2 filter forms the first valid sample after skipping two samples, the sensor conversion interval N m takes 384, 768, or 3072 VC1 clock intervals for resolutions of 10, 12, and 14 bits respectively. The higher order digital filter used in these configurations gives a shorter conversion time than the PRS16 configuration at the same resolution. The maximum sample value is determined by N max : N max = 2 N 1 Equation 22 N selected conversion resolution. Because the comparator bitstream is supplied to the decimator, the decimator sample N d value is proportional to the duty cycle d mod as follows: N d = ( 1 d mod ) N max Equation 23 To make the reading increase with duty cycle increases, the final sample value is calculated in the following way: N s = N max N d Equation 24 Clock Source The clock source is used to control the switches on the sensing capacitor. The user module supports four selection options as the clock source for the precharge switches: The 16-bit pseudo-random sequence generator (PRS16) The 8-bit PRS source The 8 bit prescaler source The VC2 clock source Document Number: Rev. *B Page 18 of 74

19 (a) IMO PRS16 (b) IMO PRS8 To precharge switches (c) IMO PWM8 (d) IMO VC1 VC2 Precharge Switch Clock Selection Options for CSDADC The required configuration should be selected when you first select the user module. To change this selection later, right click the CSDADC User Module icon in Interconnect View and select User Module Selection Options. The PRS configurations use the (pseudo-random) PRS16 or PRS8 module as a clock source. Using one of the PRS sources provides spread-spectrum operation and ensures good immunity from external noise. In addition, designs with the spread-spectrum clock have lower electromagnetic emission levels. When your application is targeted to pass the EMC/EMI tests or must provide reliable operation in the harsh environments, the PRS16 configuration is recommended. The PRS source is clocked by the IMO directly. The average clock frequency for this configuration is F IMO /4. The peak precharge switch frequency is F IMO /2, or 12 MHz for the 24 MHz IMO operation mode. The PRS sequence repeat period matches the conversion sample cycle count to avoid possible aliasing problems and SNR degradation. This is accomplished by changing the PRS generation period. PRS8 uses shorter poly in than the PSR16 configuration. This gives the PRS8 reduced susceptibility to noise than the PRS16 configuration. A PSR16 configuration uses a 3 digital blocks, the PRS8 uses one. The prescaler configuration uses an 8-bit counter as clock source. This counter is sourced by the IMO clock directly. The prescaler allows you to easily tune the operation frequency by changing the prescaler counter period. The main application area of the prescaler-based configuration is capacitive sensing using high-resistance materials, for example, sensing using the thin transparent ITO films over the display in a double layer touchpad device. The prescaler-based configuration can be used also, when a low sensing frequency is desired, for example to reduce power consumption or radio emission levels. Configuration uses 1 digital block. The VC2-based configuration uses a VC2 divider as precharge switches clock source. It operates in the similar way as prescaler-based configuration, but provides assymetrical on/off time for precharge switches because VC2 divider output has its pulse length fixed to one VC1 period. The precharge clock is changed by setting the scanning speed. Because of this the rawcount and difference touch signal are proportional to the scanning speed, having a maximum value for the Fast setting and minimum value for the Slow setting. Due to the fixed operation frequency, this capacitance sensing configuration is sensetive to noisy signals with frequencies equal to or multiples of the operation frequency of the precharge switches. This configuration is recommended for designs where EMC/EMI tests are not obligatory or where ambient noise or EMC test frequencies do not match the operation frequency of the precharge switches. This configuration does not use digital blocks. Document Number: Rev. *B Page 19 of 74

20 The table below compares the four configurations: Configuration PRS16 PRS8 Operation Frequency Spread-spectrum, average is F IMO /4, peak is F IMO /2 Adjustable spread spectrum, F IMO /4 F IMO /512 Digital Blocks Used EMC Noise Immunity 3 High. Sensitive points are multiples of the PRS sequence repeat period and PRS fundamental frequency F IMO. 2 Moderate. Sensitive at more points due to the shorter PRS repeat period. If good EMI immunity is required, please use a PRS16 configuration Prescaler fixed, IMO/(Period+1) 1 Device is sensetive for EMC signals at operation frequency and its harmonics. Recommended only for operation via high-resistance materials VC2 fixed, IMO/(VC2+1) 0 Device is sensetive for EMC signals at operation frequency and its harmonics. Recommended only when no certification EMC/EMI tests are planned The sensing switched capacitor should be charged and discharged completely during each precharge clock phase (either Ph 1 or Ph 2 ). Operation with a several megahertz clock is not a problem for low resistance, copper sensing electrodes. However, when high-frequency signal is applied to resistive materials (like ITO film) the sensing capacitor charge and discharge transient process is not finished within the clock phase. This phenomenon causes a decrease in measured capacitance values and sensitivity degradation. Reducing the switch frequency helps. The conversion interval N m in Equation 21 should be a multiple of the prescaler period to eliminate possible aliasing problems. Since the measurement interval is a multiple of 256 (2 8 ) for any available resolution, the prescaler period should be a power of two minus one (n 2 1) as well. The configuration with prescaler allows easy tuning of the precharge switch operation frequency to match the clock phase duration with the sensing electrode time constant. If a sensor has a series resistance R x and capacitance C s (the R x and C s values can be distributed on a plane) the operation frequency should be less than: 1 1 f speak R x C s The electrode resistance R x can be found using the material specific resistance and geometric dimensions. The C s capacitance can be measured at low frequency using an impedance meter. Calculate the peak frequency of the precharge switch f speak with the following equation: Equation 25 1 F f speak -- IMO = T PRES + 1 Equation 26 T PRES The prescaler period register value. Document Number: Rev. *B Page 20 of 74

21 Feedback Components Selection Guidelines The user module requires an external modulation capacitor C mod and a modulator feedback resistor R b. The capacitor can be connected to the P0[5], P0[7] port pins and Vss ground. The feedback resistor R b can be connected to port pins P1[1], P1[5], P3[1], P3[5], P5[1], P5[5] and the capacitor pin. The pins are selected with the user module parameter setting. Please do not use pins selected for modulator component connection for any other purposes. 24x94 k=1,3,5 Pk[1], Pk[5] P0[5], P0[7] R b C mod External Component Connections The recommended value for the modulation capacitor is nf. The optimal capacitance can be selected by experiment to get maximum SNR. A value of nf gives good results in the most cases. Note: if configuration with prescaler has been used, a larger modulator capacitor is required. A good quality, 100nF capacitor is sufficient in most cases. You can experiment with several capacitor values to get the best SNR after selecting the feedback resistor. A ceramic capacitor should be used. The temperature capacitance coefficient is not important. The resistor values depend on the total sensor capacitance C s. The resistor value should be selected as follows: Monitor the raw counts for different sensor touches. Select a resistance value that provides maximum readings about 30% less than the full scale readings at the selected scanning resolution. The raw counts are increased when resistor values increase. Typical values are 500Ω 10 kω depending on sensor capacitance and precharge switch operation frequency. You can start with 2.0 kω if you are using the CY3214 evaluation board. Shielding Electrode Some applications require reliable operation in the presence of water films or droplets. White goods, automotive applications, various industrial applications, and others need capacitive sensors that do not provide false triggering because of water, ice, and humidity changes. In this case a separate shielding electrode can be used. This electrode is located behind or outside the sensing electrode. When water films are located on the device insulation overlay surface, the coupling between the shielding and sensing electrodes is increased. The shielding electrode allows you to reduce the influence of parasitic capacitance, which gives you more dynamic range for processing sense capacitance changes. In some applications it is useful to select the shielding electrode signal and its placement relative to the sensing electrode such that increasing the coupling between these electrodes causes the opposite of the Document Number: Rev. *B Page 21 of 74

22 touch change of the sensing electrode capacitance measurement. This simplifies the high-level software API work. The CSDADC User Module supports separate output for the shielding electrode. Water drop Overlay C x C par PCB Sensor electrodes Shielding electrode Possible Shield Electrode PCB Layout The figure above illustrates one possible layout configuration for the button s shield electrode. The shield electrode is especially useful for transparent ITO touchpad devices, where it blocks the LCD drive electrode s noise influence and reduces stray capacitance at the same time. In this example, the button is covered by a shielding electrode plane. As an alternative, the shielding electrode can be located on the opposite PCB layer, including the plane under the button. A hatch pattern is recommended in this case, with a fill ratio of about 30 to 40%. No additional ground plane is required in this case. When water drops are located between the shielding and sensing electrodes, the C par is increased and modulator current can be reduced. In practical tests, the modulator reference voltage can be increased by the API so that the raw count increase from water drops should be close to zero or slightly negative. You can achieve this by selecting the appropriate modulator reference. Document Number: Rev. *B Page 22 of 74

23 In this User Module, the same signal used for the precharge clock is supplied to the shielding electrode. The figure below illustrates its operation. V dd Sw 1 Ph 1 Sw 3 Sw 4 To shield electrode C par V Cmod To modulator Sw 2 C s Ph 2 C s Total sensor capacitance C par Capacitance between the shielding and sensing electrodes The switches Sw 1 and Sw 3 are on at phase Ph 1, the switches Sw 2 and Sw 4 are on at phase Ph 2. The C par is discharged at phase Ph 1 phase and is charged at Ph 2 phase. The modulator current is the algebraic sum of C s and C par currents, and can be evaluated by the following equation: I mod = I C I Cpar = f s C s ( V dd V Cmod ) f s C par V Cmod Equation 27 Also, lowering the modulator reference voltage reduces the parasitic capacitance C par influence on total modulator current. Therefore, in the water-proof sensing optimal value for modulator reference can be minimal. As can be seen in Equation 27, the modulator current is reduced with coupling increases between electrodes. This allows separate signals from the water and finger, which can then be processed in firmware. The shield electrode can be connected to any free row output bus. For the row LUT function you should select A, as illustrated in the figure below: Document Number: Rev. *B Page 23 of 74

24 Shield Row LUT Functions Setup for CSDADC Operation The shield electrode can be connected to any suitable PSoC pins. The drive mode can be set to Strong Slow to reduce ground noise and radiated emissions. Also, the slew limiting resistor can be connected between the PSoC device and the shielding electrode. The resistor value should be selected in such way that all transient processes finish during the precharge clock phase (either Ph 1 or Ph 2 ). This value can be estimated with the following equation: C sh shield electrode capacitance (do not confuse with C par ) Equation 28 For example, the PRS16 configuration (with IMO = 24MHz) maximum peak switching frequency is fs = 12 MHz. The shielding electrode capacitance is 20 pf. This allows us to calculate a value for the slew limiting resistor as 400Ω. Scanning an Array of Sensors 1 R e f s Csh The CY8C24x94 family of devices have 2 built-in analog buses. The two analog buses are connected together to provide the possibility of scanning sensors connected to any pins. The CSDADC User Module uses internal precharge switches to charge active sensors at clock signal phase Ph 1 and connects the Analog Buses to the sensor at phase Ph 2. The sigma-delta modulator modulation capacitor and comparator inputs are connected to the analog bus permanently. The firmware performs sensor scanning in series by setting corresponding bits in the MUX_CRx registers. Document Number: Rev. *B Page 24 of 74

25 Switches enable, MUX_CRx Analog Bus V dd Clock Ph1 Break-before make PRS Ph 1 Pin 1 Ph2 Ph 2 t Cx1 GPIO cell Mux Cell 1 Pin 2 Cx2 Mux Cell 2... Sigma-delta modulator Pin k Mux Cell k Cxk Analog Bus with Precharge Switches and Driving Waveforms Sliders Sliders are used for controls requiring gradual adjustments. Examples include a lighting control (dimmer), volume control, graphic equalizer, and speed control. These sensors are mechanically adjacent to one another. Actuation of one sensor results in partial actuation of physically adjacent sensors. The actual position in the slider is found by computing the centroid location of the set of activated sensors. Sliders are accommodated in the CSDADC Wizard, by establishing groups in which each group of sliders has a specific order. The practical lower limit number for sensors slider is five, the upper limit is simply the number of sensor positions available on the PSoC device selected. Document Number: Rev. *B Page 25 of 74

26 Counts (above Noise Threshold) Finger Position (Centroid) Ordering Physical Sensor Locations The close proximity of strong signals in one half of the slider results in the same levels aliased into the upper half, but the results are scattered. The sensing algorithms search for strong adjacent sets of signals to declare the resolved slider position. Diplexing Each PSoC sensor connection in a slider is mapped to two physical locations in the array of slider sensors. The first (or numerically lower) half of the physical locations is mapped sequentially to the base assigned sensors, with the port pin assigned by the designer using the CSDADC Wizard. The second (or upper) half of the physical sensor locations is automatically mapped by an algorithm in the Wizard and listed in an include file. The order is established so that adjacent sensor actuation in one half does not result in adjacent sensor actuation in the other half. Exercise care to determine this order and map it onto the printed circuit board. There are a number of methods to order the second half of the physical sensor locations. The simplest is to index the sensors in the upper half, all of the even sensors, followed by all of the odd sensors. Other methods include indexing by other values. The method selected for this user module is to index by three. Document Number: Rev. *B Page 26 of 74

27 Counts (above Noise Threshold) Index by 3 You should balance sensor capacitance in the slider. Depending on sensor or PCB layouts, there may be longer routes for some of the sensor pairs. The diplex sensor index table is automatically generated by the CSDADC Wizard when you select diplexing. The table below illustrates the diplexing sequences for different slider segments count. Diplexing Sequence for Different Slider Segment Counts Total Slider Segment Count Segment Sequence 10 0,1,2,3,4,0,3,1,4,2 12 0,1,2,3,4,5,0,3,1,4,2,5 14 0,1,2,3,4,5,6,0,3,6,1,4,2,5 16 0,1,2,3,4,5,6,7,0,3,6,1,4,7,2,5 18 0,1,2,3,4,5,6,7,8,0,3,6,1,4,7,2,5,8 20 0,1,2,3,4,5,6,7,8,9,0,3,6,9,1,4,7,2,5,8 22 0,1,2,3,4,5,6,7,8,9,10,0,3,6,9,1,4,7,10,2,5,8 24 0,1,2,3,4,5,6,7,8,9,10,11,0,3,6,9,1,4,7,10,2,5,8, ,1,2,3,4,5,6,7,8,9,10,11,12,0,3,6,9,12,1,4,7,10,2,5,8, ,1,2,3,4,5,6,7,8,9,10,11,12,13,0,3,6,9,12,1,4,7,10,13,2,5,8, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,0,3,6,9,12,1,4,7,10,13,2,5,8,11,14 Document Number: Rev. *B Page 27 of 74

28 Total Slider Segment Count Segment Sequence 32 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,3,6,9,12,15,1,4,7,10,13,2,5,8,11, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,0,3,6,9,12,15,1,4,7,10,13,16,2,5,8,11, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,0,3,6,9,12,15,1,4,7,10,13,16,2,5,8,11,14, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,0,3,6,9,12,15,18,1,4,7,10,13,16,2,5,8,11,14, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,0,3,6,9,12,15,18,1,4,7,10,13,16,19,2,5,8,11,14, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,0,3,6,9,12,15,18,1,4,7,10,13,16,19,2,5,8,11,14, 17, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,0,3,6,9,12,15,18,21,1,4,7,10,13,16,19,2,5,8, 11,14,17, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,0,3,6,9,12,15,18,21,1,4,7,10,13,16,19,22, 2,5,8,11,14,17, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,0,3,6,9,12,15,18,21,1,4,7,10,13,16,19, 22,2,5,8,11,14,17,20, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,0,3,6,9,12,15,18,21,24,1,4,7,10,13, 16,19,22,2,5,8,11,14,17,20, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,0,3,6,9,12,15,18,21,24,1,4,7,10, 13,16,19,22,25,2,5,8,11,14,17,20, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,0,3,6,9,12,15,18,21,24,1,4,7, 10,13,16,19,22,25,2,5,8,11,14,17,20,23, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,0,3,6,9,12,15,18,21,24, 27,1,4,7,10,13,16,19,22,25,2,5,8,11,14,17,20,23, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,0,3,6,9,12,15,18,21,2, 27,1,4,7,10,13,16,19,22,25,28,2,5,8,11,14,17,20,23, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,0,3,6,9,12,15,18, 21,24,27,1,4,7,10,13,16,19,22,25,28,2,5,8,11,14,17,20,23,26, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,0,3,6,9,12,15, 18,21,24,27,30,1,4,7,10,13,16,19,22,25,28,2,5,8,11,14,17,20,23,26, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,0,3,6,9,12, 15,18,21,24,27,30,1,4,7,10,13,16,19,22,25,28,31,2,5,8,11,14,17,20,23,26, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,0,3,6,9, 12,15,18,21,24,27,30,1,4,7,10,13,16,19,22,25,28,31,2,5,8,11,14,17,20,23,26,29, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,0,3,6, 9,12,15,18,21,24,27,30,33,1,4,7,10,13,16,19,22,25,28,31,2,5,8,11,14,17,20,23,26,29, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,0,3, 6,9,12,15,18,21,24,27,30,33,1,4,7,10,13,16,19,22,25,28,31,34,2,5,8,11,14,17,20,23,26,29, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 0,3,6,9,12,15,18,21,24,27,30,33,1,4,7,10,13,16,19,22,25,28,31,34,2,5,8,11,14,17,20,23,26,29,32, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,0,3,6,9,12,15,18,21,24,27,30,33,36,1,4,7,10,13,16,19,22,25,28,31,34,2,5,8,11,14,17,20,23,26,29, 32,35 Document Number: Rev. *B Page 28 of 74

29 Total Slider Segment Count Segment Sequence 76 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,0,3,6,9,12,15,18,21,24,27,30,33,36,1,4,7,10,13,16,19,22,25,28,31,34,37,2,5,8,11,14,17,20,23, 26,29,32, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,0,3,6,9,12,15,18,21,24,27,30,33,36,1,4,7,10,13,16,19,22,25,28,31,34,37,2,5,8,11,14,17,20, 23,26,29,32,35, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,39,0,3,6,9,12,15,18,21,24,27,30,33,36,39,1,4,7,10,13,16,19,22,25,28,31,34,37,2,5,8,11,14, 17,20,23,26,29,32,35, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,39,40,0,3,6,9,12,15,18,21,24,27,30,33,36,39,1,4,7,10,13,16,19,22,25,28,31,34,37,40,2,5,8, 11,14,17,20,23,26,29,32,35, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,39,40,41,0,3,6,9,12,15,18,21,24,27,30,33,36,39,1,4,7,10,13,16,19,22,25,28,31,34,37,40,2, 5,8,11,14,17,20,23,26,29,32,35,38, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,39,40,41,42,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,1,4,7,10,13,16,19,22,25,28,31,34,37, 40,2,5,8,11,14,17,20,23,26,29,32,35,38, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,39,40,41,42,43,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,1,4,7,10,13,16,19,22,25,28,31,34, 37,40,43,2,5,8,11,14,17,20,23,26,29,32,35,38, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,39,40,41,42,43,44,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,1,4,7,10,13,16,19,22,25,28,31, 34,37,40,43,2,5,8,11,14,17,20,23,26,29,32,35,38,41, ,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 36,37,38,39,40,41,42,43,44,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,1,4,7,10,13,16,19,22,25, 28,31,34,37,40,43,2,5,8,11,14,17,20,23,26,29,32,35,38,41,44 Interpolation and Scaling In applications for sliding sensors and touchpads it is often necessary to determine finger (or other capacitive object) position to more resolution than the native pitch of the individual sensors. The contact area of a finger on a sliding sensor or a touchpad is often larger than any single sensor. In order to calculate the interpolated position using a centroid, the array is first scanned to verify that a given sensor location is valid. The requirement is for some number of adjacent sensor signals to be above a noise threshold. When the strongest signal is found, this signal and those contiguous signals larger than the noise threshold are used to compute a centroid. As few as two and as many as (typically) eight sensors are used to calculate the centroid in the form of: n N i 1 ( i 1) + n i i+ n i + 1 ( i + 1) Cent = n i 1 + n i + n i + 1 Equation 29 Document Number: Rev. *B Page 29 of 74

30 The calculated value is typically fractional. In order to report the centroid to a specific resolution, for example a range of 0 to 100 for 12 sensors, the centroid value is multiplied by a calculated scalar. It is more efficient to combine the interpolation and scaling operations into a single calculation and report this result directly in the desired scale. This is handled in the high-level APIs. Slider sensor count and resolution are set in the CSDADC Wizard. A scaling value is calculated by the wizard and stored as fractional values. The multiplier for the centroid resolution is contained in three bytes with these bit definitions: Resolution Multiplier MSB Multiplier Resolution Multiplier ISB Multiplier Resolution Multiplier LSB Multiplier 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 The resolution is found by using this equation: Resolution = (Number of Sensors 1) x Multiplier The centroid is held in a 24-bit unsigned integer and its resolution is a function of the number of sensors and the multiplier. Document Number: Rev. *B Page 30 of 74

31 Preliminary DC and AC Electrical Characteristics Power Supply Voltage Parameter Min Typical Max Unit Test Conditions and Comments Value V Typical Noise a Parameter Fast Normal Slow Unit Test Conditions (Vdd = 5V, SysClk = 24 MHz, CPU Clock = 12MHz, Baseline >= 70% of Resolution Max Count) Gain = 4 Noise Counts, peak-to-peak Resolution = 14 peak-peak Noise Counts, peak-to-peak Resolution = 12 peak-peak Noise Counts, peak-peak peak-to-peak Resolution = 10 a. SNR increases as the Scan Speed slows and the Baseline counts increase. Power Consumption Supply Voltage Min Typ Max Unit Test Conditions and Comments Active Current 10 ma Average current during scan, 8 sensors Standby Current 250 μa Scanning Speed = Ultra Fast, Resolution = ms report rate, 8 sensors 1.6 ma Scanning Speed = Fast, Resolution = ms report rate, 8 sensors Sleep/Wake Current 10 μa 1s report rate, 1 sensor 5.0V PGA DC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes Gain Deviation from Nominal G= % G= % G= % G= % G= % Document Number: Rev. *B Page 31 of 74

32 5.0V PGA DC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes Input Input Offset Voltage mv Input Voltage Range -- Vss to Vdd V Leakage na Input Capacitance pf Output Swing 0.05 to Vdd V PSRR db 5.0V PGA AC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes Slew Rate(20% to 80%) 2 Low Power V/µs Med Power V/µs High Power V/µs Settling Time Low Power µs Med Power 4 -- µs High Power 1 -- µs Noise 2 Referred to input Med Power 110 nv/ Hz OpAmp bias low except at High High Power 100 nv/ Hz Power. Reference input set to AGND 3.3V PGA DC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes Gain Deviation from Nominal G= % G= % G= % G= % G= % Input Input Offset Voltage mv Input Voltage Range -- Vss to Vdd V Leakage na Input Capacitance pf Output Swing 0.05 to Vdd V PSRR db Document Number: Rev. *B Page 32 of 74

33 3.3V PGA DC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes Operating Current Low Power µa Med Power µa High Power µa 5.0V ADC modulator DC and AC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes Input Input Voltage Range --- Vss to Vdd V Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance pf Includes I/O pin. Input Impedance 1/(C*clk) --- Ω Effective Resolution Decimate by 64 Decimate by 128 Decimate by 256 Sample Rate Decimate by 64 Decimate by 128 Decimate by 256 DC Accuracy DNL Decimate by 64 Decimate by 128 Decimate by , <1 <1 <1 0.6 Bits sps Data Clock 8 MHz --- LSB Source Clock 1.5 MHz Offset Error mv Gain Error 2 % FSR Including Reference Gain Error Data Clock to 8.0 MHz Input to digital blocks and analog column clock 3.3V ADC modulator DC and AC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes Input Input Voltage Range --- Vss to Vdd V Ref Mux = Vdd/2 ± Vdd/2 Input Capacitance pf Includes I/O pin. Input Impedance 1/(C*clk) --- Ω Effective Resolution Decimate by 64 Decimate by 128 Decimate by 256 Sample Rate Decimate by 64 Decimate by 128 Decimate by , Bits sps Data Clock 8 MHz Document Number: Rev. *B Page 33 of 74

34 3.3V ADC modulator DC and AC Electrical Characteristics Parameter Typical Limit Units Conditions and Notes DC Accuracy DNL Decimate by 64 Decimate by 128 Decimate by 256 <1 < LSB Data Clock 1.5 MHz Offset Error mv Gain Error 2 % FSR Including Reference Gain Error Data Clock to 8.0 MHz Input to digital blocks and analog column clock Document Number: Rev. *B Page 34 of 74

35 Preliminary Characterization Graphs Raw Counts vs. Supply Voltage, 5V Vdd/2 VBG Raw Counts ,80 4,85 4,90 4,95 5,00 5,05 5,10 5,15 5,20 5,25 Supply Voltage, V Raw Count Dependence on Supply Voltage 5V at Different References, PRS16 Configuration, Gain=4. Raw Counts vs. Supply Voltage, 3.3V Vdd/2 VBG 1400 Raw Counts ,10 3,15 3,20 3,25 3,30 3,35 3,40 3,45 3,50 3,55 Supply Voltage, V Raw Count Dependence on Supply Voltage 3.3V at Different References, PRS16 Configuration, Gain=4. Note By comparing the curves you can see that the smaller raw count change is achieved at a Vdd/2+- Vdd/2 reference. The Vdd/2+-Vdd/2 reference is recommended for applications that require stable operation in a wide range of supply voltages. Document Number: Rev. *B Page 35 of 74

36 Raw Counts vs. Temperature 5V 2000 Raw Counts Small Button Medium Button Big Button Temperature, C Raw Count Dependence on Temperature for 5V Supply Voltage, PRS16 configuration, Gain=4 Raw Counts vs. Temperature 3,3V Raw Counts Small Button Medium Button Big Button Temperature, C Raw Count Dependence on Temperature for 3.3V Supply Voltage, PRS16 configuration, Gain=4 TTest conditions: 12-bit resolution, power supply voltage 5.0V/3.3V. A complete board with sensors (a CY3214 PSoC evaluation board) was placed in the climatic room during tests. Document Number: Rev. *B Page 36 of 74

37 Raw Counts Baseline-Raw Count Difference (a) Bth=10 Bth=25 Bth=50 Bth=100 Bth=150 Bth=255 Sample # Sample # (b) t, sec Raw Counts Step Change (a) and The Difference Between Raw Count and Baseline for Different BaselineUpdate Threshold (Bth) Parameter Values (b) Test conditions: 12-bit resolution, SensorsAutoreset = Enabled, and total sensor array scanning and data transmission time is about 2.5 ms. Note. Increasing the BaselineUpdate Threshold slows down the difference decay, allowing a longer maximum button touch detection time. Document Number: Rev. *B Page 37 of 74

38 Raw Counts Sample # (a) Baseline-Raw Count Difference Peak Dif. =170 Peak Dif.= 300 Peak Dif.= 600 Finger Threshold Hysteresis Sample # (b) t, sec Raw Counts Step Change (a) and The Difference Between Raw Count and Baseline Values (b) for Different Raw Count Step Change values. Test conditions: 12-bit resolution, SensorsAutoreset = Enabled, and total sensor array scanning and data transmission time is about 2.5 ms. The parameter BaselineUpdate Threshold was set to 255. Note. The larger raw count step values cause longer intervals for sensors to autoreset due to longer time required to drop the difference below the FingerThreshold-Hysteresis value. Placement The blocks for the user module are automatically placed when the user module is instantiated, alternate placements are not available. The modulator comparator is located at ACB01 continuous time block and ASD11/ASD21 switching capacitor blocks. Different UM configurations use 0-3 digital blocks. The table below summarizes the digital resources used. Document Number: Rev. *B Page 38 of 74

39 Configuration The unused analog and digital blocks are available for your own purposes. All UM configurations use the hardware decimator. User modules that consume specific pin resources, including the LCD and I2CHW, must be placed before establishing port pin connections for the CSDADC User Module. The configuration selections are reflected in the Wizard when it is opened. Avoid P1[0] and P1[1] when placing capacitive sensor connections. These pins are used for programming the part and may have excess routing capacitance affecting sensor sensitivity and noise. Wizard Wizard Access Digital Blocks Used PRS16 3 PRS8 2 Prescaler 1 VC2 clock 0 source To access the Wizard, right click any block of the CSDADC in the Device Editor Interconnect View, then select the CSDADC Wizard with a left mouse click. Wizard Access Wizard Pin Legend Blue The pin is available for assignment. Grey The pin has already been assigned. Green The pin does not have a default name and thus cannot be assigned. There are two possible causes for this. The first possibility is that another user module has claimed the pin, i.e. LCD, I2C. The second possibility is that the name of the pin has been customized. Document Number: Rev. *B Page 39 of 74

40 To return the pin name to its default: In the pin configuration grid, from the Select menu, select Default. This will make the pin available for assignment when reopening the wizard. 1. The Wizard opens showing the numeric entry boxes for the number of sensors and the number of slider sensors. 2. Type the number of independent sensors. The number of sensors is limited to the number of pins available. 3. After entering the data, double click to apply new value and click OK to accept. Document Number: Rev. *B Page 40 of 74

41 4. Type the number of sliders. X-Y touch-pads require two sliders but one is selected. 5. After entering the data, double click to apply new value and click OK to accept. 6. Type the number of sensor elements in each slider. The practical minimum number of sensors in a slider sensor is five, the maximum is limited by pin count. 7. After entering the data, double click to apply new value and click OK to accept. 8. Type the output resolution. The minimum value is five. The maximum value is (# of pins used for sensors 1) x or (2 x pins used for sensors 1) x for diplexed sliders. 9. Double click the Resolution box to accept your entry. 10. Select Diplex, if desired. This maps the number of pins selected for sensors to twice as many sensor locations on the board. Only the first half of the diplex sensors is shown; the second half is automatically mapped as outlined in the previous section on Diplexing. See the Diplexing section to find Diplex- Document Number: Rev. *B Page 41 of 74

42 ing tables for pin connections. 11. Left click the port pin and drag it onto any available sensor. The port pin is grayed out after selection and is no longer available. Change sensor assignments by dragging the port pin back to the uncommitted table. Make sure to avoid selecting pins already committed to other user modules. 12. Repeat for the remainder of independent sensors. 13. Mapping of physical port pins onto individual slider sensors is the same as for individual sensors. 14. Click OK to accept data and return to PSoC Designer User Module Selection View. Sensor placement is now complete. Right-click in the Device Editor window and select Refresh to update the pin connections. Set user module parameters and generate application. You can adapt a sample project now, if you wish. When entering the numerical values in the CSDADC Wizard, please delete the old value first, then enter the new value. The cursor is not shown in the edit box. If you want change pin assignment, place your cursor on the assigned pin, click the pin, and drag and drop it outside the switches box. The pin will be unassigned and you can then re-assign it. After completeing the Wizard, click Generate Application. Based on your entries for sensor count, pin assignment, diplexing, and resolution, a set of tables will be generated. The tables are located in CSDADC_Table.asm Sensor Table The Sensor Table consists of a 2-byte entry for each sensor. The first byte is the port number and the second byte is the bit mask for the bit (not the bit number). The table includes all independent sensors, then each sensor in order. An example for a table with ten sensors is: Document Number: Rev. *B Page 42 of 74

43 CSDADC_Sensor_Table: _CSDADC_Sensor_Table: dw 0x0001 // Port 0 Bit 0 dw 0x0002 // Port 0 Bit 1 dw 0x0004 // Port 0 Bit 2 dw 0x0008 // Port 0 Bit 3 dw 0x0010 // Port 0 Bit 4 dw 0x0101 // Port 1 Bit 0 dw 0x0102 // Port 1 Bit 1 dw 0x0104 // Port 1 Bit 2 dw 0x0108 // Port 1 Bit 3 dw 0x0110 // Port 1 Bit 4 This table is used by CSDADC_wGetPortPin() routine. Group Table The Group Table defines each of the groups of button sensors or sliders. There is one entry for each slider plus one for the free button sensors. The first entry is always the free sensors. Each entry is six bytes. The first byte is the index in the Sensor Table where the group starts. The second byte is how many sensors are in that group. The third byte signifies whether the slider is diplexed or not (4 is diplexed, 0 is not diplexed). The fourth, fifth, and sixth bytes are the fixed point multiplier that the slider's calculated centroid will be multiplied by to achieve the resolution desired in the CSDADC wizard. CSDADC_1_Group_Table: _CSDADC_1_Group_Table: ; Group Table: ; Origin Count Diplex DivBtwSw(wholeMSB, wholelsb, fractbyte) db 0x0, 0x5, 0x00, 0x00, 0x00, 0x00 ; Buttons db 0x5, 0x5, 0x3, 0x0, 0x0, 0x71 ; Slider 1 Diplex Table Diplex table scan order data is produced for a group when it is a slider and is also diplexed. Otherwise a label is created but no data is placed. The table consists of two parts: sensor mapping for each slider, and a reference for each separate slider to its table. A typical example for an five sensor slider is shown below. DiplexTable_0: ; This group is not a diplexed slider DiplexTable_1: db 0,1,2,3,4,0,3,1,4,2 // 5 switch slider CSDADC_1_Diplex_Table: _CSDADC_1_Diplex_Table: db >DiplexTable_0, <DiplexTable_0 db >DiplexTable_1, <DiplexTable_1 Parameters ADCEnabled The ADCEnabled parameter can have 2 values: Enabled Disabled Document Number: Rev. *B Page 43 of 74

44 When parameter is set to Enabled, the ADC routines are included in the user module compilable code and can be called from user code. When this parameter is set to Disabled, the ADC routines are not included by using conditional compilation directives. Setting this parameter to Disabled can be useful if no ADC is requred longer by design, in this way a CSDADC allows using second-order modulator for getting SNR improvement over standard CY8C24x94 CSD UM. PGAGain Sets the PGA gain for the ADC. Gain ranges are 1 to 48.00, using PSoC Designer or the CSDADC_SetGain routine provided in the API. Gain settings less than 1 are not supported. PGAReference The gain of the PGA is referenced to a "ground" value that you select. Choices include AGND (on-chip analog ground), V ss, and adjacent continuous time (CT) and switched capacitor (SC) blocks. CT and SC block connections allow for adjustable offsets as a controlled reference voltage. The CSDADC_SetRef API can be used to change the reference at run-time. AnalogBus The PGA block output may be routed through the analog PSoC block array s network of local interconnections and/or through an analog output bus. Setting the PGA User Module AnalogBus parameter to Disable, the default value, restricts the set of possible connections to the local network. If the PGA AnalogBus output is enabled onto the bus, care must be exercised to ensure that no other user module drives this same bus. This parameter is used by both the CSD and ADC portions of the user module. Finger Threshold This threshold is used to determine the state of each button sensor. If any sensor is active, the bisanysensoractive() function returns a 1. If all sensors are off, the bisanysensoractive() function returns a 0. The finger detection threshold values apply to all sensors and sliders. For individual sensors (not contained in a slider group), these thresholds are variable and provided in the babtnfthreshold[] array. The SetDefaultFingerThresholds() function may be used to set the thresholds to the default value set in the Device Editor. To adjust the sensitivity for individual sensors, change the babtnfthreshold[] value for each sensor. (The size of this byte array is equal to the count of implemented individual sensors.) Possible values range from 5 to 255. Noise Threshold For individual sensors, this parameter sets the count value above which the baseline is not updated. For slider sensors, it sets the count value below which the results are not counted in the calculation of the centroid. Possible values are 5 to 255. BaselineUpdate Threshold When the new raw count value is above the current baseline and the difference is below the noise threshold (with the Sensors Autoreset parameter set to Disabled), the difference between the current baseline and the raw count is accumulated into what could be thought of as a bucket. When the bucket fills, the baseline is incremented by some value and the bucket is emptied. This parameter sets the threshold that the bucket must reach for the baseline to increment. Possible values are 0 to 255. Larger Document Number: Rev. *B Page 44 of 74

45 parameter values yield slower baseline update speeds. If you need more frequent baseline updates, decreases this parameter. NegativeNoiseThreshold The NegativeNoiseThreshold parameter adds a negative difference count threshold. If the current raw count is below the baseline and the difference between them is greater than this threshold, the baseline will not be updated. However, if the current raw count stays in the low state (difference greater than threshold) for the number of samples specified by the LowBaselineReset parameter, the baseline will be reset. LowBaselineReset The LowBaselineReset parameter works together with the NegativeNoiseThreshold parameter. If the sample count values are below the baseline minus the NegativeNoiseTreshold for the specified number of samples, the baseline is set to the new raw count value. It essentially counts the number of abnormally low samples required to reset the baseline. It is generally used to correct for the finger-on-at-startup condition. Sensors Autoreset This parameter determines whether the baseline is updated at all times or only when the signal difference is below the Noise Threshold. When set to Enabled the baseline is updated constantly. This setting limits the maximum time duration of the sensor (typical values are 5 10s), but it prevents the sensors from permanently turning on when the raw count suddenly rises without anything touching the sensor. This sudden rise can be caused by a large power supply voltage fluctuation, a high-energy RF noise source, or a very quick temperature change. When the parameter is set to Disabled the baseline is updated only when raw count and baseline difference is below the Noise Threshold parameter. You should leave this parameter Enabled unless there is a demand to keep the sensors in the on state for a long time. The figure below illustrates this parameter s influence on the baseline update. Document Number: Rev. *B Page 45 of 74

46 Autoreset Disabled Baseline Rawcounts Difference Autoreset Enabled Time Time The Sensor Autoreset Parameter Hysteresis The Hysteresis parameter adds or subtracts from the finger threshold depending on whether the sensor is currently active or inactive. If the sensor is inactive, the difference count must overcome the finger threshold plus hysteresis. If the sensor is active, the difference count must go below the finger threshold minus hysteresis. It is used to add debouncing and stickiness to the finger detection algorithm. The threshold with hysteresis is evaluated when bissensoractive() or bisanysensoractive() is called. The sensor state can be monitored with the return value of bissensoractive() or the basnsonmask[] array. Possible values are 0 to 255, but must be lower than the Finger Threshold parameter setting. Proper selection of high-level decision logic parameters allowis you to effectively compensate for enviromental factors (temperature, humidity changes, and so on), suppress the noisy signals (ESD, power supply spikes), and provide reliable touch detection under various use conditions. Debounce The Debounce parameter adds a debounce counter to the sensor active transition. In order for the sensor to transition from inactive to active the difference count value must stay above the finger threshold plus hysteresis for the number of samples specified. The debounce counter is incremented by the bissensoractive or bisanysensoractive API functions. Possible values are 1 to 255. A setting of 1 provides no debouncing. Document Number: Rev. *B Page 46 of 74

47 NegativeNoiseThreshold The NegativeNoiseThreshold parameter adds a negative difference count threshold. If the current raw count is below the baseline and the difference between them is greater than this threshold, the baseline will not be updated. However, if the current raw count stays in the low state (difference greater than threshold) for the number of samples specified by the LowBaselineReset parameter, the baseline will be reset. LowBaselineReset The LowBaselineReset parameter works together with the NegativeNoiseThreshold parameter. If the sample count values are below the baseline minus the NegativeNoiseTreshold for the specified number of samples, the baseline is set to the new raw count value. It essentially counts the number of abnormally low samples required to reset the baseline. It is generally used to correct for the finger-on-at-startup condition. Scanning Speed This parameter affects the sensors scanning speed. The available selections are Fast, Normal, and Slow. Slower scanning speeds provide the following advantages: Improved SNR Better immunity to power supply and temperature changes Less demand for system interrupt latency; you can handle longer interrupts Resolution This parameter determines the scanning resolution in bits. The PRS16 configuration allows scanning sensors with resolutions ranging from 9 to 16 bits. The PRS8, prescaler, VC2 configuration allows scanning sensors at 10, 12, and 14 bits only. If you need higher resolution with these configurations, please use oversampling and average several samples. The maximum raw count for scanning resolution for N bits is 2 N -1. Same parameter value is used for ADC resolution setting. Increasing the resolution improves sensitivity and the SNR of touch detection. Use a high resolution for proximity detection. A 16-bit resolution, slow scanning mode, and a 20 cm wire allows you to detect a hand at 20cm or more. Document Number: Rev. *B Page 47 of 74