PRACE PATC Course Intel MIC Programming Workshop. February, 7-8, 2017, IT4Innovations, Ostrava, Czech Republic
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1 PRACE PATC Course Intel MIC Programming Workshop February, 7-8, 2017, IT4Innovations, Ostrava, Czech Republic
2 LRZ in the HPC Environment Bavarian Contribution to National Infrastructure German Contribution to European Infrastructure PRACE has 25 members, representing European Union Member States and Associated Countries Intel MIC Programming IT4I
3 PATC Courses Advanced Training Centre (PATC) Courses LRZ is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in 2012: Barcelona Supercomputing Center (Spain), CINECA Consorzio Interuniversitario (Italy) CSC IT Center for Science Ltd (Finland) EPCC at the University of Edinburgh (UK) Gauss Centre for Supercomputing (Germany) Maison de la Simulation (France) Mission: Serve as European hubs and key drivers of advanced high-quality training for researchers working in the computational sciences Intel MIC Programming IT4I
4 Agenda MIC Programming Workshop Tuesday February 7, :00-09:30 Registration 09:30-09:45 Welcome 09:45-10:30 Salomon intro 10:30-11:00 Coffee break 11:00-12:00 Overview of the Intel MIC architecture and programming models 12:00-13:00 Lunch break 13:00-13:30 Native mode programming 13:30-15:30 OpenMP and offloading I 15:30-16:00 Coffee break 16:00-17:00 OpenMP and offloading II 17:00-18:00 MKL
5 Agenda MIC Programming Workshop Wednesday February 8, :00-10:30 MPI 10:30-11:00 Coffee break 11:00-12:00 Vectorisation and Intel Xeon Phi performance optimisation 12:00-13:00 Lunch break Plenum session with invited talks: Wednesday February 8, 2017: 13:00-13:45 Jan Zapletal ( IT4Innovations): Boundary element quadrature schemes for multiand many-core architectures 13:45-14:15 Jiri Jaros (VUT Brno): Acceleration of the k-wave toolbox on Xeon Phi 14:15-15:00 Lukasz Szustak, Roman Wyrzykowski (TU Czestochowa): Exploring the impact of Intel MIC and Intel CPU architectures on accelerating scientific applications 15:00-15:30 Coffee break 15:30-16:15 Michal Merta (IT4Innovations): Acceleration of the ESPRESO domain decomposition library 16:15-17:00 Milan Jaros (IT4Innovations): Acceleration of Blender Cycles Render Engine using Intel Xeon Phi
6 Information Lecturers: Dr. Momme Allalen & Dr. Volker Weinberg (LRZ) Dr. Branislav Jansik (IT4Innovations) Complete lecture slides & exercise sheets: x_lecturenotes/mic_workshop_ostrava Examples under: /home/weinberg/mic_workshop
7 Intel Xeon Phi and GPU LRZ LRZ (PATC): KNC+GPU LRZ (PATC): KNC+GPU IT4Innovations: KNC LRZ (PATC): KNC+KNL PRACE Seasonal School, Hagenberg: KNC IT4Innovations (PATC): KNC LRZ (PATC): KNL inside, Vol. 12, No. 2, p. 102, 2014 inside, Vol. 13, No. 2, p. 79, 2015 inside, Vol. 14, No. 1, p. 76f, 2016 inside, Vol. 14, No. 2, p. 25ff, Intel MIC Programming IT4I
8 Evaluating Accelerators at LRZ Research at LRZ within PRACE & KONWIHR: CELL programming Evaluation of CELL programming. IBM announced to discontinue CELL in Nov GPGPU programming Regular GPGPU computing courses at LRZ since Evaluation of GPGPU programming languages: CAPS HMPP PGI accelerator compiler CUDA, cublas, cufft PyCUDA/R Intel Xeon Phi programming Larrabee (2009) Knights Ferry (2010) Knights Corner Intel Xeon Phi (2012) KNL (2016) } OpenACC, OpenMP 4.x
9 IPCC (Intel Parallel Computing Centre) New Intel Parallel Computing Centre (IPCC) since July 2014: Extreme Scaling on MIC/x86 Chair of Scientific Computing at the Department of Informatics in the Technische Universität München (TUM) & LRZ Codes: Simulation of Dynamic Ruptures and Seismic Motion in Complex Domains: SeisSol Numerical Simulation of Cosmological Structure Formation: GADGET Molecular Dynamics Simulation for Chemical Engineering: ls1 mardyn Data Mining in High Dimensional Domains Using Sparse Grids: SG++
10 CzeBaCCA Project Czech-Bavarian Competence Team for Supercomputing Applications (CzeBaCCA) New BMBF funded project that started in Jan to: Foster Czech-German Collaboration in Simulation Supercomputing series of workshops will initiate and deepen collaboration between Czech and German computational scientists Establish Well-Trained Supercomputing Communities joint training program will extend and improve trainings on both sides Improve Simulation Software establish and disseminate role models and best practices of simulation software in supercomputing Intel MIC Programming IT4I
11 CzeBaCCA Trainings and Workshops Intel MIC Programming Workshop, 3 4 February 2016, Ostrava, Czech Republic Scientific Workshop: SeisMIC - Seismic Simulation on Current and Future Supercomputers, 5 February 2016, Ostrava, Czech Republic PRACE PATC Course: Intel MIC Programming Workshop, June 2016, Garching, Germany Scientific Workshop: High Performance Computing for Water Related Hazards, 29 June - 1 July 2016, Garching, Germany PRACE PATC Course: Intel MIC Programming Workshop, 7 8 February 2017, Ostrava, Czech Republic Scientific Workshop: High performance computing in atmosphere modelling and air related environmental hazards, 9 February 2017, Ostrava, Czech Republic PRACE PATC Course: Intel MIC Programming Workshop, June 2017, Garching, Germany Scientific Workshop: HPC for natural hazard assessment and disaster migration, June 2017, Garching, Germany
12 CzeBaCCA Trainings and Workshops 1st workshop series: February IT4I inside, Vol. 14, No. 1, p. 76f, p Intel MIC Programming IT4I
13 CzeBaCCA Trainings and Workshops 2nd workshop series: June LRZ inside, Vol. 14, No. 2, p. 25ff, p Intel MIC Programming IT4I
14 Intel Xeon Top500 November #2 National Super Computer Center in Guangzhou, China: Tianhe-2 (MilkyWay-2) - TH- IVB-FEP Cluster, Intel Xeon E C 2.200GHz, TH Express-2, Intel Xeon Phi 31S1P NUDT #5 DOE/SC/LBNL/NERSC United States: Cori - Cray XC40, Intel Xeon Phi C 1.4GHz, Aries interconnect Cray Inc. #6 Joint Center for Advanced High Performance Computing Japan: Oakforest-PACS - PRIMERGY CX1640 M1, Intel Xeon Phi C 1.4GHz, Intel Omni-Path Fujitsu #12 CINECA Italy: Marconi Intel Xeon Phi - CINECA Cluster, Intel Xeon Phi C 1.4GHz, Intel Omni-Path, Lenovo #17 Texas Advanced Computing Center/Univ. of Texas United States: Stampede - PowerEdge C8220, Xeon E C 2.700GHz, Infiniband FDR, Intel Xeon Phi SE10P, Dell #18 (US) / #32 (US) / #33 (Japan) / #44 (US) / #53 (China) #67 IT4Innovations National Supercomputing Center, VSB-Technical University of Ostrava Czech Republic Salomon - SGI ICE X, Xeon E5-2680v3 12C 2.5GHz, Infiniband FDR, Intel Xeon Phi 7120P, HPE/SGI #76 (USA) / #77 (USA)
15 PRACE: Best Practice Guides
16 Intel MIC within PRACE: Intel Xeon Phi (KNC) Best Practice Guide Created within PRACE-3IP+4IP. Written in Docbook XML. 122 pages, 13 authors Now including information about existing Xeon Phi based systems in Europe: BAS (NCSA), BSC, LRZ Practice-Guide-Intel-Xeon-Phi-1.pdf
17 Intel MIC within PRACE: Knights Landing Best Practice Guide Created within PRACE-4IP. Written in Docbook XML. 85 pages, 3 authors General information about the KNL architecture and programming environment Benchmark & Application Performance results Practice-Guide-Knights-Landing.pdf
18 Xeon Phi References Books: James Reinders, James Jeffers, Intel Xeon Phi Coprocessor High Performance Programming, Morgan Kaufman Publ. Inc., ; new KNL edition in July 2016 Rezaur Rahman: Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers, Apress Parallel Programming and Optimization with Intel Xeon Phi Coprocessors, Colfax Intel Xeon Phi Programming, Training material, CAPS Intel Training Material and Webinars V. Weinberg (Editor) et al., Best Practice Guide - Intel Xeon Phi, HTML and references therein
19 Acknowledgements IT4Innovation, Ostrava. Partnership for Advanced Computing in Europe (PRACE) Intel BMBF (Federal Ministry of Education and Research) Dr. Karl Fürlinger (LMU) Intel MIC Programming IT4I
PRACE PATC Course Intel MIC Programming Workshop. June, 26-28, 2017, LRZ
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