ADC Architectures VI: Folding ADCs. by Walt Kester

Transcription

1 MT-25 TUTOIAL ADC Archiecures VI: Folding ADCs by Wal Keser INTODUCTION The "folding" archiecure is one of a number of possible serial or bi-per-sage archiecures. Various archiecures exis for performing A/D conversion using one sage per bi, and he overall concep is shown in Figure 1. A mulisage pipelined subranging ADC wih one bi per sage and no error correcion is basically a bi-per-sage converer. In pracice, his ype of pipelined converer generally uses a 1.5 bi per sage approach o provide error correcion (his is discussed in more deail in eference 1). In he bi-per-sage ADC, he inpu signal mus be held consan during he enire conversion cycle. There are N sages, each of which have a "bi" oupu and a "residue" oupu. The residue oupu of one sage is he inpu o he nex. The las bi is deeced wih a single comparaor as shown. V EF ANALOG SHA STAGE 1 1 STAGE 2 2 STAGE N-1 BIT 1 MSB BIT 2 BIT N-1 - BIT N LSB DECODE LOGIC AND OUTPUT EGISTES N B. D. Smih, "An Unusual Elecronic Analog-Digial Conversion Mehod," IE Transacions on Insrumenaion, June 1956, pp Figure 1: Generalized Bi-Per-Sage ADC Archiecure I is possible o combine he bi-per-sage archiecure wih oher archiecures. For example, he residue oupu of he final sage can be furher digiized by a flash converer, hereby providing more resoluion. One of he firs references o hese archiecures appeared in an aricle by B. D. Smih in 1956 (eference 2). Smih indicaes, however, ha previous work had been done a M.I.T. by. P. Sallen in a 1949 hesis. In he aricle, Smih describes boh he binary and he Gray (or folding) ransfer funcions required o implemen he A/D conversion. ev.a, 1/8, WK Page 1 of 12

2 MT-25 BINAY AND FOLDING BIT-PE-STAGE (SEIAL) ADCs The basic sage for performing a single binary bi conversion is shown in Figure 2. I consiss of a gain-of-wo amplifier, a comparaor, and a 1-bi DAC (changeover swich). Assume ha his is he firs sage of he ADC. The MSB is simply he polariy of he inpu, and ha is deeced wih he comparaor which also conrols he 1-bi DAC. The 1-bi DAC oupu is summed wih he oupu of he gain-of-wo amplifier. The resuling residue oupu is hen applied o he nex sage. In order o beer undersand how he circui works, he diagram shows he residue oupu for he case of a linear ramp inpu volage which raverses he enire ADC range, o. Noice ha he polariy of he residue oupu deermines he binary bi oupu of he nex sage. G = 2 Σ ESIDUE -V - -V ESIDUE SWITCH POSITION SHOWN FO NEGATIVE BIT OUTPUT (BINAY CODE) -V Figure 2: Single-Sage Transfer Funcion for Binary ADC A simplified -bi serial-binary bi-per-sage ADC is shown in Figure, and he residue oupus are shown in Figure 4. Again, he case is shown for a linear ramp inpu volage whose range is beween and. Each residue oupu signal has disconinuiies which correspond o he poin where he comparaor changes sae and causes he DAC o swich. The fundamenal problem wih his archiecure is he disconinuiy in he residue oupu waveforms. Adequae seling ime mus be allowed for hese ransiens o propagae hrough all he sages and sele a he final comparaor inpu. As presened here, he prospecs of making his archiecure operae a high speed are dismal. However using he 1.5-bi-per sage pipelined archiecure (see eference 1) makes i much more aracive a high speeds. Page 2 of 12

3 MT-25 ±V ANALOG SHA STAGE 1 1 STAGE BIT 1 BIT 2 BIT OUTPUT EGISTE Figure : -bi Serial ADC wih Binary Oupu 1 2 BINAY CODE Figure 4: Inpu and esidue Waveforms of -Bi Binary ipple ADC Alhough he binary mehod is discussed in his paper, B. D. Smih also describes a much preferred bi-per-sage archiecure based on absolue value amplifiers (magniude amplifiers, or simply MagAMPs ). This scheme has ofen been referred o as serial-gray (since he oupu coding is in Gray code), or folding converer because of he shape of he ransfer funcion. Performing he conversion using a ransfer funcion ha produces an iniial Gray code oupu has he advanage of minimizing disconinuiies in he residue oupu waveforms and offers he poenial of operaing a much higher speeds han he binary approach. Page of 12

4 MT-25 The basic folding sage is shown funcionally in Figure 5 along wih is ransfer funcion. The inpu o he sage is assumed o be a linear ramp volage whose range is beween and. The comparaor deecs he polariy of he inpu signal and provides he Gray bi oupu for he sage. I also deermines wheher he overall sage gain is 2 or 2. The reference volage V is summed wih he swich oupu o generae he residue signal which is applied o he nex sage. The polariy of he residue signal deermines he Gray bi for he nex sage. The ransfer funcion for he folding sage is also shown in Figure 5. G = 2 V Σ ESIDUE G = -2 SWITCH POSITION SHOWN FO NEGATIVE -V - ESIDUE BIT OUTPUT (GAY CODE) -V Figure 5: Folding Sage Funcional Equivalen Circui A -bi MagAMP folding ADC is shown in Figure 6, and he corresponding residue waveforms in Figure 7. As in he case of he binary bi-per-sage ADC, he polariy of he residue oupu signal of a sage deermines he value of he Gray bi for he nex sage. The polariy of he inpu o he firs sage deermines he Gray MSB; he polariy of 1 oupu deermines he Gray bi-2; and he polariy of 2 oupu deermines he Gray bi-. Noice ha unlike he binary ripple ADC, here is no abrup ransiion in any of he folding sage residue oupu waveforms. This makes operaion a high speeds quie feasible. Page 4 of 12

5 MT-25 ±V ANALOG SHA BIT 1 BIT 2 BIT GAY CODE EGISTE GAY-TO-BINAY CONVETE OUTPUT EGISTE Figure 6: -bi Folding ADC Block Diagram 1 2 GAY CODE Figure 7: Inpu and esidue Waveforms for -Bi Folding ADC The key o operaing his archiecure a high speeds is he folding sage. N. E. Chasek of Bell Telephone Labs describes a circui for generaing he folding ransfer funcion using nesed diode bridges in a paen filed in 196 (eference ). This circui made use of solid-sae devices, bu required differen reference volages for each sage (see Figure 8). Chasek's circui also suffered from loss of headroom and gain when several sages were cascaded o form higher resoluion Page 5 of 12

6 MT-25 converers as shown in Figure 9. Wha is really needed o make he folding ADC work a high resoluions is nearly ideal volage or curren recificaion. GAY CODE OUTPUT BIT 1 BIT 2 BIT BIAS BIAS BALANCED 1 2 BIAS BIAS Adaped from: N. E. Chasek, "Pulse Code Modulaion Encoder," U.S. Paen,5,258, Filed November 14, 196, Issued May 15, 1962 Figure 8: -Bi Folding ADC Based on N. E. Chasek's Design /2 1 /2 /2 2 /4 /4 /4 GAY CODE Figure 9: Single-Ended Waveforms in Chasek's Folding ADC Page 6 of 12

7 MT-25 F. D. Waldhaur of Bell Telephone Labs remedied he problems of Chasek's nesed diode bridge circuis in a classic paen filed in 1962 (eference 4). Figure 1 shows Waldhaur's elegan implemenaion of he folding ransfer funcion using solid sae op amps wih diodes in he feedback loop. The gain-of-wo op amps allow he same reference volages o be used for each sage and mainain he same signal level a each residue oupu wih nearly ideal recificaion. 2 I OFFSET I BALANCED i i 2 2 i 2i 2i 2i I BIT OUTPUT BALANCED OUTPUT i i i 2i 2i 2i I 2 I OFFSET I Exraced from: F. D. Waldhauer, "Analog-o-digial Converer," U.S. Paen,187,25, Filed July 2, 1962, Issued June 1, 1965 Figure 1: F. D. Waldhaur's Classic Folding Sage using ecifier Amplifiers J. O. Edson and H. H. Henning describe he operaion and performance of his ype of ADC in greaer deail in a 1965 Bell Sysem Technical Journal aricle (eference 5). An operaional 9-bi, 6-MSPS ADC of his ype was used in experimenal sudies on 224-Mbi/second PCM erminals. These erminals were supposed o handle daa as well as voice signals. The voiceband objecive was o digiize an enire 6-channel, 2.4-MHz FDM band, herefore requiring a minimum sampling rae of approximaely 6 MSPS. I is ineresing o noe ha he experimenal erminal was also supposed o handle video as well, which required a higher sampling rae of approximaely 12-MSPS. For his requiremen, he laes (and final) generaion Bell Labs' elecron beam coder (see Tuorial MT-2) was needed o mee he ADC requiremen, as he solid-sae coder based on Waldhaur's paen did no have he necessary accuracy a he higher sampling raes. The firs commercial ADC using Waldhaur's Gray code archiecure was he 8-bi, 1-MSPS HS- 81 from Compuer Labs, Inc., in The insrumen used all discree ransisor circuis (no ICs) and was designed o be mouned in a 19" rack as shown in Figure 11 for an early experimenal digial radar receiver applicaion. The 8-bi, 1-MSPS converer conained is own linear power supply, dissipaed nearly 15 was, and sold for approximaely $1,. The same echnology was used o produce 9-bi, 5-MSPS and 1-bi -MSPS versions. Alhough he nex Page 7 of 12

8 MT-25 generaion of Compuer Labs' designs would ake advanage of modular op amps (Compuer Labs OA-125 and FS-125), ICs such as he Fairchild µa71/711 comparaors, as well as 74 TTL logic, he firs ADCs offered used all discree devices. These early high speed ADCs produced by Compuer Labs were primarily used in research and developmen projecs associaed wih radar receiver developmen by companies such as ayheon, General Elecric, and MIT Lincoln Labs. 19" ACK-MOUNTED, 15W, $1,. INSTALLATION OF 12 ADCs IN EXPEIMENTAL DIGITAL ADA ECEIVE Figure 11: HS-81, 8-bi, 1-MSPS ADC eleased by Compuer Labs, Inc. in 1966 The folding Gray code archiecure was used in a few insrumen and modular ADCs in he early 197s, such as he HS-81, bu commercial high speed ADCs primarily used eiher he flash or he error-correced subranging archiecure in he 198s. Wih improvemens in IC processes, here was, however, coninued ineres in he folding archiecure in he lae 197s and hroughou he 198s wih quie a number of experimenal designs repored in he various journals over he period (eferences 6-1). Analog Devices developed he firs high speed fully complemenary bipolar (CB) process in he mid-198s, and in 1994 Frank Murden and Carl Moreland filed paens on a significanly improved curren-seering archiecure for a Gray code MagAMP -based ADC (eferences 11-15). The echnique was firs implemened for building block cores in he AD bi, 41- MSPS ADC released in 1995, and refinemens of he echnique and a higher speed CB process, XFCB, (eferences 16 and 17) pushed he core echnology o 14-bis wih he release of he AD bi 65-MSPS ADC in 1999, he AD bi 8-MSPS ADC in 21, and a 15- MSPS version of he AD6645 in 2. Alhough hese ADCs use he error-correced pipelined subranging archiecure, he inernal building block core ADCs uilize he MagAMP archiecure. Page 8 of 12

9 MT-25 Modern IC circui designs implemen he ransfer funcion using curren-seering open-loop gain echniques which can be made o operae much faser. Fully differenial sages (including he SHA) also provide speed, lower disorion, and yield 8-bi accurae folding sages wih no requiremen for hin film resisor laser rimming. An example of a fully differenial gain-of-wo MagAMP folding sage is shown in Figure 12 (see eferences 11, 12, 14). The differenial inpu signal is applied o he degeneraed-emier differenial pair Q1,Q2 and he comparaor. The differenial inpu volage is convered ino a differenial curren which flows in he collecors of Q1, Q2. If IN is greaer han IN, cascodeconneced ransisors Q, Q6 are on, and Q4, Q6 are off. The differenial signal currens herefore flow hrough he collecors of Q, Q6 ino level-shifing ransisors Q7, Q8 and ino he oupu load resisors, developing he differenial oupu volage beween OUT and OUT. The overall differenial volage gain of he circui is wo. 2I I OFF 2I - I OFF Q7 V BIAS V BIAS Q8 Q Q4 Q5 Q6 OUT i i- GAY GAY - IN Q1 Q2 -IN -OUT I I Figure 12: A Modern Curren-Seering MagAMP Sage If IN is less han IN (negaive differenial inpu volage), he comparaor changes sae and urns Q4, Q5 on and Q, Q6 off. The differenial signal currens flow from Q5 o Q7 and from Q4 o Q8, hereby mainaining he same relaive polariy a he differenial oupu as for a posiive differenial inpu volage. The required offse volage is developed by adding a curren I OFF o he emier curren of Q7 and subracing i from he emier curren of Q8. The differenial residue oupu volage of he sage drives he nex sage inpu, and he comparaor oupu represens he Gray code oupu for he sage. Page 9 of 12

10 MT-25 The MagAMP archiecure offers lower power and can be exended o sampling raes previously dominaed by flash converers. For example, he AD954A 8-bi, 2-MSPS ADC is shown in Figure 1 and was firs inroduced in The device is fabricaed on a high speed complemenary bipolar process, and power dissipaion is 5 mw. The firs five bis (Gray code) are derived from five differenial MagAMP sages. The differenial residue oupu of he fifh MagAMP sage drives a -bi flash converer, raher han a single comparaor. The Gray-code oupu of he five MagAMPs and he binary-code oupu of he -bi flash are lached, all convered ino binary, and lached again in he oupu daa regiser. Because of he high daa rae, a demuliplexed oupu opion is provided. ANALOG SHA BIT FLASH ADC DIFFEENTIAL OUTPUTS ON BITS 1-5 BIT 1 GAY BIT 2 GAY BIT GAY EGISTE 5 BIT 4 GAY BIT 5 GAY BINAY GAY-TO-BINAY CONVETE 5 OUTPUT EGISTES 8 Figure 1: AD954A 8-bi, 2-MSPS ADC Inroduced in 1997 ecen inroducions in he 8-bi high speed area have uilized CMOS processes and he pipelined subranging archiecure, such as he 8-bi 25 MSPS, AD948 (LVDS oupus) and AD9481 (demuxed CMOS oupus) which dissipae 7 mw and 6 mw, respecively. SUMMAY Alhough iniially used in pioneering insrumen ADCs a Bell Labs and Compuer Labs in he 196s, he flash he pipelined subranging archiecures have dominaed he high speed ADC markeplace. Alhough here have been a number of ICs designed using he folding archiecure, i has never aained he populariy of he pipelined subranging ADC. Neverheless, i is imporan o know ha i exiss because i may regain populariy in he fuure as IC processes evolve. Page 1 of 12

11 MT-25 EFEENCES 1. Wal Keser, Analog-Digial Conversion, Analog Devices, 24, ISBN , Chaper. Also available as The Daa Conversion Handbook, Elsevier/Newnes, 25, ISBN , Chaper. 2. B. D. Smih, "An Unusual Elecronic Analog-Digial Conversion Mehod," IE Transacions on Insrumenaion, June 1956, pp (possibly he firs published descripion of he binary-coded and Gray-coded bi-per-sage ADC archiecures. Smih menions similar work parially covered in. P. Sallen's 1949 hesis a M.I.T.).. N. E. Chasek, "Pulse Code Modulaion Encoder," U.S. Paen,5,258, filed November 14, 196, issued May 15, (an early paen showing a diode-based circui for realizing he Gray code folding ransfer funcion). 4. F. D. Waldhauer, "Analog-o-Digial Converer," U.S. Paen,187,25, filed July 2, 1962, issued June 1, (a classic paen using op amps wih diode swiches in he feedback loops o implemen he Gray code folding ransfer funcion). 5. J. O. Edson and H. H. Henning, "Broadband Codecs for an Experimenal 224Mb/s PCM Terminal," Bell Sysem Technical Journal, Vol. 44, pp , Nov (a furher descripion of a 9-bi ADC based on Waldhauer's folding sage). 6. Udo Fiedler and Dieer Seizer, "A High-Speed 8 Bi A/D Converer Based on a Gray-Code Muliple Folding Circui," IEEE Journal of Solid-Sae Circuis, Vol. SC-14, No., June 1979, pp (an early monolihic folding ADC). 7. udy J. van de Plassche and ob E. J. van de Grif, "A High-Speed 7 Bi A/D Converer," IEEE Journal of Solid-Sae Circuis, Vol. SC-14, No. 6, December 1979, pp (a monolihic folding ADC). 8. ob. E. J. van de Grif and udy J. van de Plassche, "A Monolihic 8-bi Video A/D Converer, IEEE Journal of Solid Sae Circuis, Vol. SC-19, No., June 1984, pp (a monolihic folding ADC). 9. ob. E. J. van de Grif, Ivo W. J. M. uen and Marien van der Veen, "An 8-bi Video ADC Incorporaing Folding and Inerpolaion Techniques," IEEE Journal of Solid Sae Circuis, Vol. SC-22, No. 6, December 1987, pp (anoher monolihic folding ADC). 1. udy van de Plassche, Inegraed Analog-o-Digial and Digial-o-Analog Converers, Kluwer Academic Publishers, 1994, pp (a good exbook on ADCs and DACs wih a secion on folding ADCs indicaed by he referenced page numbers). 11. Carl Moreland, "An 8-bi 15 MSPS Serial ADC," 1995 ISSCC Diges of Technical Papers, Vol. 8, p (a descripion of an 8-bi ADC wih 5 folding sages followed by a -bi flash converer). 12. Carl Moreland, An Analog-o-Digial Converer Using Serial-ipple Archiecure, Masers' Thesis, Florida Sae Universiy College of Engineering, Deparmen of Elecrical Engineering, (Moreland's early work on folding ADCs). 1. Frank Murden, "Analog o Digial Converer Using Complemenary Differenial Emier Pairs," U.S. Paen 5,55,492, filed December 1, 1994, issued Augus 27, (a descripion of an ADC based on he MagAMP folding sage). 14. Carl W. Moreland, "Analog o Digial Converer Having a Magniude Amplifier wih an Improved Differenial Inpu Amplifier," U.S. Paen 5,554,94, filed December 1, 1994, issued Sepember 1, (a descripion of an 8-bi ADC wih 5 folding sages followed by a -bi flash converer). Page 11 of 12

12 MT Frank Murden and Carl W. Moreland, "N-bi Analog-o-Digial Converer wih N-1 Magniude Amplifiers and N Comparaors," U.S. Paen 5,684,419, filed December 1, 1994, issued November 4, (anoher paen on he MagAMP folding archiecure applied o an ADC). 16. Carl Moreland, Frank Murden, Michael Ellio, Joe Young, Mike Hensley, and ussell Sop, "A 14-bi 1- Msample/s Subranging ADC, IEEE Journal of Solid Sae Circuis, Vol. 5, No. 12, December 2, pp (describes he archiecure used in he 14-bi AD6645 ADC). 17. Frank Murden and Michael. Ellio, "Linearizing Srucures and Mehods for Adjusable-Gain Folding Amplifiers," U.S. Paen 6,172,66B1, filed July 1, 1999, issued January 9, 21. (describes mehods for rimming he folding amplifiers in an ADC). Copyrigh 29, Analog Devices, Inc. All righs reserved. Analog Devices assumes no responsibiliy for cusomer produc design or he use or applicaion of cusomers producs or for any infringemens of paens or righs of ohers which may resul from Analog Devices assisance. All rademarks and logos are propery of heir respecive holders. Informaion furnished by Analog Devices applicaions and developmen ools engineers is believed o be accurae and reliable, however no responsibiliy is assumed by Analog Devices regarding echnical accuracy and opicaliy of he conen provided in Analog Devices Tuorials. Page 12 of 12