Self-Checking Carry-Select Adder Design Based on Two-Pair Two-Rail Checker

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1 Self-Checking Carry-Select Adder Design Based on Two-Pair Two-Rail Checker P.S.D.Lakshmi 1, K.Srinivas 2, R.Satish Kumar 3 1 M.Tech Student, 2 Associate Professor, 3 Assistant Professor Department of ECE, Bonam Venkata Chalamayya Institute of Technology & Science, Amalapuram, India. Abstract In the design of integrated circuits error checking And area occupancy plays a vital role because of increasing the necessity of portable systems. InThis paper, the self-checking carry-select adder (CS ea) design is proposed. The capability of self checking can detect transient and all single stuck-at faults on-line in normal operation mode. The proposed CSeA has not only having self-checking capability but also have reduced transistor count. The reduced ratio of transistorcount is proportional to the bit count of self-checking CSeA to be designed. Our design has other advantages such as high extensibility, non-tree detector structure, and reasonable propagation delay time and can keeping well normal operation in the high-bit design.this paper focuses on self-checking carry-select adder design based on two-pair two-rail checker(ttrc). The resulting carry-select adders have capability to detect errors on-line during the normal operation, with reduced silicon area with lower power consumption. Keywords: self-checking, two-pair two-rail checker(ttrc), carry select adder, on-line test. 1.Introduction Arithmetic circuits are fundamental building blocks in many integrated circuits (IC) such as dedicated proce s- sors and digital signal processors. Therefore, to design the high performance and highly reliable adders has become the key issue and In recent years, several types of high performance adders, such as carry lookahead adder, carry skip adder, conditional sum adder, carry-select adder (CSeA) and so on, have been proposed. Each one adder has different advantages and drawbacks in chip area, delay time, design complexity, and power dissipation. Among these adders, CSeA is widely used due to less propagation delay time,easy implementation, low power dissipation and small overhead. Conventional n-bit CSeA circuit, shown in figure 1, achieves high performance but require double hardware overhead. To overcome the this drawback, CSeA is modified with only one carry ripple adder in company with the add-one (add-1) circuit. In order to guarantee highly reliability, the capability to online detect faults in carry select adder is extremely important. The probability of detecting faults, especially transient fault, occurring in modern ICs has grown significantly due to the shrinkage in transistor feature size. It is well-known that transient faults can only be detected by built-in online fault detection, i.e., self-checking capability.a design technique has been proposed for implementing self-checking carry select adders by cascading self-checking 2-bit adders. These carry select adders are totally self-checking for both permanent and transient single s- stuck-at faults. However, when the 2-bit totally selfchecking carry high-bit adder, a carry select adder is expanded and cascaded to a tree structure checker circuit based on 2-pair-2-rail checker(ttrc) is formed. Obviously, for large bit-count the performance and the required silicon area of tree structure checkers based on 2- pair-2-rail checkers make them a non attractive solution for today applications. c 0 n c 0 n-1 c 0 2 c 0 1 c 1 n c 1 n-1 c 1 2 c 1 1 c 1 0 Fig 1.Conventionaln-bit CSeA circuit 1.1 Self-Checking Carry Select Adder self-checking circuits are used in many systems with high reliability requirement. A self-checking circuit consists of Page 2037 c 0 0

2 a function circuit performing the required function specified by the chip designer, a check code generator to generate the check-codes to be check from the outputs of function circuit, and a checker to check the check-codes to be valid or invalid. In this paper, we assume that the function circuit is a two-bit CSeA, the check code generator produces two-rail codes, and a two-rail checker has the capability to detect the faults occurring in the two-bit CSeA. For selection of adequate CSeA as function circuit, conventional CSeA is fast enough, but the required very large silicon area. The modified CSeA implementation by using a single carry ripple adder and an add-1 circuit with leading zero approach can effectively reduce the area and hence to play the vital role. 1.2 Two-pair-Two-Rail Checker(TTRC) The proposed two-rail checker, receives the two -pair two-rail code [(x 1,y 1 ), (x 2, y 2 )] as the check-code input and exports both z 1 and z 2 signals as the error indication output. The two-rail checker can detect the presence of any single stuck-at fault in the function circuit under test, i.e., modified two-bit CSeA module, on-line. There are two output states of the two-rail checker: the (z 1, z 2 ) equivalent to (0, 1) which is considered as invalid codeword, the CSeA under test is faulty; another (z 1, z 2 ) state is (0, 1) which is considered as valid codeword, the CSeA under test is faultfree. A two rail checker has two groups of inputs ( x 1, x 2, x 3, x n ) and (y 1, y 2, y 3, y n ) and two outputs e 1 and e 2.The signals observed on the outputs should always be complementary, i.e. a 1-out-of-2 code if and only if every pair, is also complementary for all j (1 j n). In a non-error situation when x 0 x 1 = 11, y 0 y 1 = 00 ; the result of this is e 1 = 0, e 2 =1 valid code. Now consider a situation where due to fault y 0 y 1 =10 output appears 00 or 11 which shows either fault in the checker or at the inputs of the checker. The fault-free checker will produce the complementary outputs if the inputs are complementary. The error checking functions of the two pair rail checker are as follows: e 1 = x 0 y 1+ y 0 x 1 e 2 = x 0 x 1 + y 0 y 1 This two rail checker can be cascaded with testable block The outputs q and s of one testable block forms the input x 0 and y 0 for the two-pair rail checker, and the outputs of another testable block forms the input x 1 and y 1 as Fig. 2. Two rail checker. 2.DESIGN PROBLEM: The relation between sum bits calculated with identical inputs is only dependent on the carry-input, and for complemented values of carry-input, we will obtain complemented sum bits (keeping other pairs of input bits identical). For example, if the sum bits i 1 and i 0 are generated by using intermediate carry i 1 and i 1 respectively, then according to the above-mentioned statements: if Where, i indicates the bit position, while 1 and 0 in the superscript represent the initial value of in. If we analyze the CSeA design, then the above statements are only valid for the least significant sum bit of a particular CSeA block. This is because the first full-adder in every CSeA block is the only one that will get the complemented values of the carry- input. The remaining full adders will depend on the propagated carry, which may or may not be complementary to each other. Therefore, we cannot say whether the generated sum bits, other than the first full adder, will be inverted to each other or not. shown in Fig.2. Thus, the testable blocks are tested using the two-pair two-rail checker. Page 2038

3 Fig. 3. Examples of 3-bit addition (a) 2 0 S 2 1 (b) 2 0 S 2 1. For the carry input cin=0,cin=1 1.For the identical inputs,if carry input zero or one then it will be normal addition operation. 2. For the inverted inputs with carry input zero then it will be all ones. 3. For the inverted inputs with carry input one then it will be all zeros. The possibility of having equal values of propagated carry by the two corresponding adders in a CSeA was neglected. Therefore, the approach fails for CSeA with more than two bits. Note that the initial carries, and, always complementary to each other because of the design requirement of CSeA, while the inter-mediate carries, and, may or may not be complementary to each other, depending on the conditions of carry propagation. Thus, and will not always be complementary to each other. Therefore, comparing and directly using 2-pair- 2-rail - checker (TTRC) will give the wrong indication of faults. Even if there is no fault, the TTRC will indicate a fault. Since the problem in their approach starts from and, we do not discuss the intermediate carries and. Let us con-sider the binary addition of 3-bit numbers as illustrated in Fig. 3. It can easily be seen from Fig. 3(a) and (b) that the most signif-icant bits may or may not be complementary to each other. 3.PROPOSED DESIGN SOLUTION: A carry select adder precomputes sum bits using two parallel ripple-carry adders (RCAs), with complemented values of the initial, and the actual value of the will be used to determine the final sum bit. However, it is possible to perform a logical operation such that one of the RCA blocks should always provide inverted sum bits with respect to the opponent block for checking purposes only. This will provide a more simplified and systematic design, which can be extended easily. In this paper, we will discuss only one possible way in which the sum bits calculated at initial C i =0 After close observation, we found that: Except for the least significant bit, the sum bit computed when initial carry -in equals 0 will be complementary to the corresponding sum bit with an initial carry- in equal to 1 only when all the lower sum bits are equal to logic-1 Fig. 4. Faulty design of 4-bit self-testing carry-select adder with two-pair two-rail checker Page 2039

4 ISSN (Online) ISSN (Print) Fig. 5. Corrected design of self-testing carry-select adder with two-pair two-rail checker if Thus, in order to apply TTRC for -bit CSeA, we need to have S 1 n along with its complement, and S 0 n will not al- bits at C in =0 are ways equal to S 1 n. If all the (n-1) th sum equal to logic-1, then the value S 0 n is equal to the comple- (n-1) th sum bits at ment of S 1 n.in other cases, if any of the C in =0 Are equal to logic-0, then we take the inverse of S 0 n, so it equals to the complement of S 1. n Therefore, in (1) we performed an XNOR operation between S 0 n and the prod- at the initial C in =0, such uct of all lower sumbits computed that the resultant K will always be equal tos 1 n.the design module shown in Fig. 3will be used to implement the 4-bit self-checking CSeA. TABLE I COMPARISON OF CSEA WITH SELF-CHECKING CSEA BEFORE AFTER CORRECTION Page 2040

5 Fig. 6. Comparison with CSeA, self-checking CSeA [1] and our proposed solution. 7(a) 4.COMPARISON: We applied the same technology and implementation used for comparison.a standard complementary metal-oxide semiconductor-based AND gate with 6 transistors was used for area computation and the transistor count for full-adder, multiplexer (MUX), XNOR gate and TTRC was taken [1], as given below: Full adder 28 transistors; MUX 12 transistors; XNOR 10 transistors; TTRC 8 transistors. For an -bit self-checking CSeA, we required number Of AND gates, number of XNOR gates, number of MUX, number of full adders and number of TTRC, respectively.from Table I,we can see that the difference in transistor overhead for 4- bit to 64-bit self-checking, was found to be 23.2% to 34.5%A graphical representation for area comparison is shown in Fig.6. We can see that after correcting the self-checking CSeA design, the percent change in transistor count shows an increasing trend with the increase in number of bits in the adder. Experimental Results and Analysis The two-rail checker can detect the presence of any single stuck-at fault in the function circuit under test, i.e., modified two-bit CSA module, on-line. There are two output states of the two-rail checker: the (Z1, Z2) equivalent to (0, 1) which is considered as invalid codeword, the CSA under test is faulty; another (Z1, Z2) state is (0, 1) which is considered as valid codeword, the CSA under test is fault-free Proposed system simulation results and analysis 1.fault-free (correct) system output of CseA i)for 4-bit input data 7 (b) Fig 6(a):RTL Schematic 7(b):Output wave form the simulation results for the 4 bit self Checking CSeA circuit based on two-pair two rail checker is shown in figure 7(a) &7(b). 1.faulty system output of CseA i)for 4-bit input data 8(a) Page 2041

6 8(b) Fig 8(a):RTL Schematic 8(b):Output waveform For faulty output the RTL schematic and output waveforms of 4- bit self checking carry select adder based 10(a) on two pair two rail checker is shown in figure 8(a) and 8(b). Extended e system experimental results and analysis The Extended system is simulated and verified using Veriog HDL in Xilinx ISE 14.7.This is the simulation results for the 8- bit self Checking circuit. 1.fault-free (correct) system output of CseA 10(b) Fig 10(a):RTL Schematic 10(b):Output wave form For faulty output the RTL schematic and output waveforms of 8- bit self checking carry select adder based on two pair two rail checker is shown in figure 10(a) and 10(b). Conclusion 9(a) 9(b) Fig 9(a):RTL Schematic 9(b):Output waveform For correct output the RTL schematic and output waveforms of 8- bit self checking carry select adder based on two pair two rail checker is shown in figure 9(a) and 9(b). ii) faulty system output of CseA The self-checking carry-select adder design is proposed. The design is based on TSMC 0.18um mixed signal CMOS process technology. The experimental results shows that this design is very usefull for error checking.for high bit also self-checking carry-select adder can easily be implemented based on proposed totally self-checking two-bit carry-select adder module by appropriately cascading connection. The transistor count of proposed totally selfchecking carry-select adder design is less than conventional CSA. The reduced ratio of transistor-count is proportional to the bit count of totally self-checking CSA to be designed. This design has other advantages such as high extensibility, non-tree detector structure, and reasonable propagation delay time and can keeping well normal operation in the high-bit design. The experimental results show that our design is valid and effective than previous design. REFERENCES: [1] D. P. Vasudevan, P. K. Lala, and J. P. Parkerson, Selfchecking carryselect adder design based on two-rail encoding, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 12, pp , Dec Page 2042

7 [2] M. Alioto, G. Palumbo, and M. Poli, Optimized design of parallel carry-select adders, Integration, the VLSI J., vol. 44, no. 1, pp ,Jan [3] H. Belgacem, K. Chiraz, and T. Rached, A novel differential XOR-based self-checking adder, Int. J. Electron., vol. 99, no. 9, pp , Apr [4] Y. S.Wang, M. H. Hsieh, J. C.-M. Li, and C. C.-P. Chen, An at-speed test technique for high-speed highorder adder by a 6.4-GHz 64-bit domino adder example, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 8, pp , Aug Page 2043