AN-695 APPLICATION NOTE

Transcription

1 APPLICATION NOTE One Technology Way P.O. Box 90 Norwood, MA 00-90, U.S.A. Tel:.9.00 Fax:.. Using the ADN TEC Controller Evaluation Board by Gang Liu and Dongfeng Zhao INTODUCTION The ADN is a thermoelectric cooler (TEC) controller that drives medium power TECs (< A current) with excellent temperature control resolution, stability, and high power efficiency. The ADN integrates two high performance amplifiers dedicated to temperature sensing and thermal loop compensation, allowing direct interface to a thermistor, a resistive temperature device (TD), or other temperature sensors. When used in conjunction with the ADN data sheet, this application note describes how to configure the EAL-ADN evaluation board (ersion..), and how to develop a real TEC control circuit with an ADN. The ADN data sheet provides the detailed technical specifications and internal functional block diagrams, as well as the application design guidelines. Important layout design guidelines are available in the Evaluation Board Layout section of this application note. EALUATION BOAD DESCIPTION The ADN evaluation board offers a configurable design platform to work with various TECs and thermistors. On the evaluation board, the ADN delivers and controls a bidirectional TEC current using two pairs of complementary MOSFETs in an H-bridge configuration. With the on-board, adjustable components, the evaluation board provides configurability of temperature setpoint, temperature setpoint range, TEC current and/or voltage limits, and a PID compensation network. The temperature setpoint range (factory default) circuit, optimized to work with 0 kω negative temperature coefficient thermistors, can also work with other types of temperature sensors. The tunable PID compensation network allows the characteristic matching between the control circuit and the thermal load for achieving the fastest response time and temperature control stability. A green LED illuminates when the TEMOUT voltage is within ±00 m of the TEMPSET setpoint voltage. FUNCTIONAL BLOCK DIAGAM ADN EALUATION BOAD SETPOINT TEMPEATUE ANGE CONFIGUATION POTENTIOMETES LED CUENT AND OLTAGE LIMIT CONFIGUATION POTENTIOMETES POWE SUPPLY SETPOINT TEMPEATUE ADJUSTMENT POTENTIOMETE ADN ON STANDBY ON OFF TEC THEMISTO TUNABLE COMPENSATION NETWOK EXTENAL COMPONENTS Figure. Functional Block Diagram of ADN Evaluation Board ev. B Page of

2 TABLE OF CONTENTS Introduction... Evaluation Board Description... Functional Block Diagram... Getting Started... Switches and Potentiometers... Quick Start... Configure Setpoint Temperature ange... Configure the Setpoint Temperature... Set the Output Current Limits... Set the Output oltage Limit... Monitor the TEC oltage... Monitor the TEC Current... Temperature Compensation... Adjust the PWM Switching Frequency... Multiple Unit Evaluation... Evaluation Board Layout... Evaluation Board Schematic and Artwork...9 ev. B Page of

3 GETTING STATED The EAL-ADN, shown in Figure, is set by factory default to deliver about A bidirectional TEC current while working with a 0 kω thermistor at C. Switch S, Left Hand Side: Standby Control The ADN is placed in standby mode when Switch S (the left hand side knob) is down. When the knob is up (default), the ADN is released from standby mode. In standby mode, all circuits, with the exception of the EF and SYNCO outputs of the ADN, are powered off. Switch S, ight Hand Side: Shutdown Control The ADN is in shutdown mode when Switch S (the right hand side knob) is down. When the knob is up (default), the ADN is released from shutdown mode. In shutdown mode, the ADN is powered off. Switches S, S, S, S, and S: Adjustable Components for an Optimal PID Compensation Network Switches S, S, S, S, and S provide PID network component adjustability for CD, D, I, P, and CI as shown in Figure. After connecting one TEC to an EAL-ADN, a thermal oscillation may occur. To squelch the oscillation, optimize the system settling time, and to control the TEC temperature precisely, PID network component tuning is necessary. Figure. Top iew of the Evaluation Board The factory default setting determines the on-board component values of the temperature-to-voltage converter circuit and the PID circuit shown in Figure. With the on-board switches and potentiometers, the circuits in Figure can be adapted to work with most TEC and thermistors used in telecommunications. EF TH EF CD D P CI CF I TEMPSET OUT Figure. Temperature and Compensation Network Circuits eferring to Figure, note that refers to voltage signal outputs from Pin (OUT) and TEMPSET, a voltage signal, applied to Pin (INP). These terms are used throughout this application note. SWITCHES AND POTENTIOMETES Table. Switch Settings Switch Function Default S CD uf S D.9 kω S I 9 kω S P 9 kω S CI 0 nf S Standby/shutdown Up/up µF.µF.µF µf 0µF Figure. Switch Position for Switch S When a switch knob is in the up position, the value listed below the switch knob is an increment to the component. For example, Switch S determines the CD value in Figure and Figure 9. Switch S shows the up knobs for the. μf and the μf (note that these knobs are set to the upper position). In this example, the value of CD is. μf + μf =. μf The same principle applies to Switches S, S, S, S, and S. On-Board Potentiometers The EAL-ADN has the following on-board potentiometers to adjust the component values (shown in Figure ) and to configure the TEC current limitation at both cooling and heating modes. The default settings are shown in Table. Table. Potentiometer Settings Potentiometer Function Default Temperature compensation network. kω Temperature compensation network. kω Temperature compensation network. kω W TEMPSET 0 kω W LIM 0 kω W ILIMC, ILIMH 0 kω W ILIMC, ILIMH 0 kω ev. B Page of

4 QUICK STAT Connect the power supply, the TEC module, and the thermistor to an EAL-ADN as shown in Figure and as described in Step through Step. TECP OPTIONAL TEMPSET TECN EAL-ADN TH DD TH AGND PGND + TEC POWE SUPPLY Figure. EAL-ADN Quick Start Block Diagram. erify that the on-board switches are set to the defaults.. Connect the thermistor between the board pads labeled TH and AGND.. Connect the positive terminal of a thermoelectric cooler to the TECP board pad and connect the negative terminal to TECN.. erify the on-board potentiometer default settings.. Ensure that the power supply is powered off and then connect it to board pads DD and PGND. Maintain the power supply between.0 and. for proper operation.. Turn on the power supply. The thermistor temperature-dependent voltage,, locks to the programmed setpoint voltage, TEMPSET. The green LED illuminates within several seconds, indicating successful temperature lock. CONFIGUE SETPOINT TEMPEATUE ANGE The default values for esistor,, and, listed in Table, are optimal for a 0 kω, β = 0 (at C) thermistor to lock a TEC temperature at C. The sections that follow describe how to configure potentiometers for different negative temperature coefficient (NTC) thermistors. Thermistor alues Determine the three thermistor resistance values: HIGH, MID, and. To do this, refer to the termistor -T table in the appropriate thermistor data sheet. This is based on required TEC thermal control resolution and the target controllable temperature range. These resistor values correspond to the high, middle, and low setpoint temperatures (THIGH, TMID, and T). {THIGH, T} is the TEC system controllable setpoint temperature range. T MID T = HIGH + T T is the average temperature, between THIGH and T. MID, is the voltage output at the pin. It is TH resistance dependent. is a function of TH,,, and as = 0. EF + + In a design, let equal the following values at the three thermistor resistances: TH = HIGH(at THIGH): = EF TH = MID(at TMID): TH = 0. EF TH = (at T): = 0 In this example, EF equals about. and is a reference voltage at Pin of the ADN. esistor alues To achieve the required outputs at the three different setting point temperatures, use the equation ( + ) MID HIGH HIGH = MID+ () HIGH + MID = () MID ( + ) MID = () MID For example, setting the high setpoint temperature at C and the low setpoint temperature at C results in a middle setpoint temperature ( + )/ = C. Using the -T table of a thermistor, HIGH =.9 kω MID = 0 kω =. kω Note that Equation to Equation result in =. kω =. kω =. kω Adjusting the Potentiometers,, and To adjust on-board potentiometers to get the proper,, and values, turn off the power supply and then measure the resistance between TP and TP, and adjust Potentiometer to =. kω. TP and TP, and adjust Potentiometer to =. kω. Between TP and TP, and adjust Potentiometer to =. kω. ev. B Page of

5 Because these potentiometers connect to the active components inside the ADN, the measured result is not accurate if the internal components conduct a significant leakage current. These components have a turn on voltage of ~0.. After,, and are configured, the output voltage of the first amplifier,, equals = 0. EF + + TH is the thermistor resistance within the setpoint temperature range. EF is the voltage reference value of the ADN, nominally.. When the setpoint temperature range is narrow, such as <0 C, the relationship between the thermistor temperature and the temperature voltage,, is almost linear, and the error is less than 0.%. The linear equations is = EF T T SET HIGH T T THIGH is the upper temperature limit in C. T is the lower temperature limit in C. TSET is the setpoint temperature value in C. In the case where the second part of Equation is negative, that is MID ( HIGH + + HIGH ) HIGH MID 0 Set = MID and = 0. For some applications, the setpoint temperature is not a range, but a single point temperature. In this case, set the single point temperature to be the midpoint temperature, TMID, and set THIGH = TMID + C, and T = TMID C. At the same time, set = MID and = 0. Because the setpoint temperature is a single point, there is no need to linearize the vs. temperature response curve. After calculating, check to see if the gain of the first stage is between 0 and 0. The gain calculates as GAIN = /MID If the gain is too high, increase the span between THIGH and T, otherwise, decrease the span. Note that the lower limit on the pin cannot be 0. The minimum output voltage is 0 m. Configure the setpoint temperature range so that some margin exists in the lower limit. For example, for a temperature range of C to C, use. C (% lower than the C limit) as the lower limit. TH CONFIGUE THE SETPOINT TEMPEATUE The TEMPSET voltage corresponds to a TEC setpoint temperature. Configure the TEMPSET using Potentiometer W. There are two cases in which to use Equation. In the first case, the setpoint temperature is known. Use the -T table in the thermistor data sheet to find the specific value of TH, then solve for TEMPSET. Apply TEMPSET to the TEMPSET pin. In the second case, the voltage at Pin is known. Solve the equation for TH and use the -T table in the thermistor data sheet to find the setpoint temperature. TEMPSET = 0. EF + () + TH TH is the thermistor resistance at the setpoint temperature. EF is the voltage reference value of the ADN, nominally.. An alternative method is to assume that there is a linear relationship between temperature and voltage; this is similar to the linear relationship described for the pin. When the setpoint temperature range is narrow, such as <0 C, the relationship between the thermistor temperature and the temperature voltage,, is almost linear, and the error is less than 0.%. It is possible to derive the setpoint temperature by the upper and lower temperatures and the voltage limit. The equation is TSET T TEMPSET = EF T T HIGH THIGH is the upper temperature limit in C. T is the lower temperature limit in C. TSET is the setpoint temperature value in C. SET THE OUTPUT CUENT LIMITS Use Potentiometers W and W to determine the TEC current limits at cooling and heating modes. Then, use Equation and Equation to determine the required voltage levels applied to the ILIMC and ILIMH pins. EF ILIMC = + ITCMAX S () EF ILIMH = I THMAX () S ILIMC is the voltage applied to Pin ILIMC. ILIMH is the voltage applied to Pin ILIMH. ITCMAX is the maximum TEC current for cooling. ITHMAX is the maximum TEC current for heating. S is the resistance value of a current sense resistor. In Figure 9, S = 0.0 Ω. EF is the reference voltage. When taken from the ADN, EF =.. ev. B Page of

6 For example, to set ITCMAX and ITHMAX equal to A and. A, respectively, use the following equations: ILIMC ILIMH. = =.. =. 0.0 = 0. Turn Potentiometer W while measuring the voltage at Pin (ILIMC); set this value to be equal to.. Turn W while measuring the voltage at Pin (ILIMH); set this value to equal 0.. SET THE OUTPUT OLTAGE LIMIT To protect the TEC from being overdriven, adjust W to set up the LIM voltage. The maximum voltage applied across the TEC can be limited by setting the voltage on Pin (LIM). This voltage is LIM = TMAX/ LIM is the voltage set at the LIM pin. TMAX is the maximum voltage across the TEC. For example, to set a maximum TEC voltage equal to, use the following equation: LIM = / = 0. MONITO THE TEC OLTAGE The voltage across the TEC, TEC, is monitored in real time by measuring the voltage TEC from Pin 0 (TEC). TEC = LFB SFB = (TEC 0. EF) TEC is the voltage across the TEC. LFB is the voltage measured at the LFB pin. SFB is the voltage measured at the SFB pin. TEC is the voltage measured at the TEC pin. EF is the reference voltage. When taken from the ADN, EF =.. Alternatively, measuring the voltage difference between the LFB and SFB pins also results in the voltage across the TEC (TEC). Typically, the LFB pin connects to the positive terminal of the TEC, and the SFB pin connects to the negative terminal of the TEC. The definition of the TEC voltage is the voltage difference between the TEC positive and negative terminals. TEC can be positive or negative. When TEC is positive, the TEC is in cooling mode. When TEC is negative, the TEC is in heating mode. When the ADN is set to standby mode, knowing the voltage across the TEC is useful. This voltage, called the Seebeck voltage, is generated by the temperature difference between the two TEC plates. This measurement is useful for determining the condition of the TEC and/or the TEC working status for high end systems. MONITO THE TEC CUENT The TEC current is monitored in real time by measuring the voltage, ITEC, on the ITEC pin (Pin 9). To calculate the TEC current from the ITEC pin voltage, use the following equation: ITEC 0. EF ITEC = S ITEC is the TEC current; defined as the current flowing in through the TEC positive terminal (TECP) and out the TEC negative terminal (TECN). S is the current sense resistor value, set to 0.0 Ω on the evaluation board. TEMPEATUE COMPENSATION Temperature stability and settling time are control loop gain and bandwidth dependent. This includes the gain of the ADN and the TEC/thermistor feedback. To achieve the highest dc precision, the control loop uses a proportional integral differential (PID) compensation network. Because thermal loads can vary widely from TEC to TEC, a tunable compensation network is available on the evaluation board. To tune the PID compensation network, apply a low frequency square wave to the LP solder pad and monitor the OUT test point using an oscilloscope. EF TH EF CD I D TEMPSET LP P LP CF Figure. Tunable Compensation Network CI OUT Before doing this, connect a TEC to the evaluation board TECP and TECN pads and connect the thermistor attached to the TEC to the evaluation board TH and AGND pads. The low frequency square wave equates to sending a step function to TEMPSET. An alternative method to the square wave is to use a pair of tweezers to short-circuit the LP solder pad with the AGND test point. Observe the waveform at OUT to determine if the compensation network matches the thermal load. The ideal response at OUT has the fastest possible rise time and settling time with little or no overshoot. Use the following steps to tune the network:. Set CI to μf, I and P to 9 kω, D to 00 kω, and CD to 0 nf. Make sure that the loop is stable. If not, increase CI and decrease P. This has the effect of increasing the time constant of the loop, allowing it to become stable. The effect of this increased time constant is a slower response time in the compensation network ev. B Page of

7 . When the compensation loop is stable, it is possible to adjust the component values in the network to decrease the overall loop response time. This is accomplished by slowly decreasing CI, increasing P, decreasing D, increasing CD, and decreasing I. Adjust these such that the output at Pin OUT has a fast rise and fall time with little or no overshoot. In applications where fast response time is critical, allow for a small amount of overshoot (0% to 0%).. After tuning the compensation network to satisfactory values, it is recommended to replace the tunable compensation network components with the discrete components to be used in the future system and repeat the test. After soldering the discrete components, turn off the tunable compensation network components by placing all the switches into the lower position.. The capacitors used in the compensation network should be multilayer ceramic capacitors of X material. This type of capacitor maintains a stable capacitance over temperature and bias drifts. X type capacitors also have a very low leakage current and low noise. Typical performance for a butterfly-packaged laser with a settling time of C change in setpoint temperature is approximately 0. second to second; for a large mass laser head of W to W, the settling time is about seconds to 0 seconds. For more details of the temperature compensation network, see the ADN data sheet. ADJUST THE PWM SWITCHING FEQUENCY The ADN evaluation board is default set to a free-run PWM clock at MHz. To modify FEQ, adjust the PWM switching frequency (see Figure ). educing the frequency of the PWM switching frequency improves the system power efficiency, but requires the use of a large physical size LC filter inductor and capacitors. For telecommunication applications, the recommended setting (default) is MHz for the switching frequency. However, for applications where efficiency is critical, a 00 khz clock is an option. Table. Switching Frequencies vs. FEQ fswitch FEQ 0 khz kω 00 khz 9 kω 0 khz kω MHz kω ADN COMPOSC FEQ SYNCI/SD kω LP nf FEQ DD 0.µF Figure. Switching Frequencies MULTIPLE UNIT EALUATION P DD The ADN can drive one TEC or, in a multiple unit configuretion, can drive multiple TECs. Details for connecting multiple devices together are available in the ADN data sheet. Access to the connection pins for synchronizations and phase assignment is available through the PHASE, SYNCO, and SYNCIN solder pads located in the center of the evaluation board. If the system noise is significant, change the MΩ resistors of the slaves to % ( kω) higher than the kω recommended for the master ADN. For details, contact your local Analog Devices, Inc. sales office. ADN MASTE SYNCO COMPOSC FEQ SYNCI/SD 0kΩ PHASE ADN SLAE COMPOSC SYNCI/SD FEQ PHASE ADN SLAE COMPOSC SYNCI/SD DD FEQ PHASE DD kω DD NC kω MΩ nf PHASE kω MΩ nf PHASE 0.µF 0.µF Figure. Multiple Unit Configuration ev. B Page of

8 EALUATION BOAD LAYOUT Figure 0 through Figure show the layout of the ADN evaluation board. Seven important guidelines are helpful when designing an ADN evaluation board layout. efer to Figure 9 for the part numbers listed here.. The ground terminals of decoupling capacitors from the PDD to PGND and the PWM LC output filter capacitors must be tied together to reduce the power rail ripple. Using PCB traces or a ground plane (with long current paths) to connect these two components may generate, rather than reduce, the power rail ripple (supply pumping).. The two source terminals of the PWM MOSFETs must be connected directly or through a thick trace (> mm) to the terminals of the power supply decoupling capacitors (C and C9).. It is not necessary to use a -layer PCB for the circuit; -layer boards are sufficient (EAL-ADN uses a -layer PCB layout). Several recommendations to consider when using a -layer PCB follow. Use one internal layer as the ground plane, the other internal layer for signal traces. Use both top and bottom layers as heat sinks for the ADN IC, the output filter inductor, and the output MOSFETs (both on the linear and on the PWM sides). Avoid conducting high current on the ground plane. Always differentially run the PCB traces for critical signal paths. For example, run a dedicated parallel trace for the analog ground (AGND) with the Pin trace; both are for connecting the two terminals of the thermistor. This ensures that any interference coupled on the thermistor traces can cancel each other. The low frequency temperature control circuit can be degraded easily by high frequency interference due to the rectifier effect. This effect refers to the phenomenon that occurs when a high frequency signal interferes with a low frequency circuit; the interference signal is rectified, or coupled, onto dc or lower frequency signals, thus affecting the operation of the circuit. When high frequency interference is unavoidable, use a small capacitor of up to 00 nf con-nected across the thermistor and mounted close to the controller to decouple the high frequency interference.. Ensure that the power supply decoupling capacitors have a total value of >0 μf. SMT multilayer ceramic capacitors of type X or X are the recommended capacitors. These types of capacitors have stable capacitance over temperature and very low equivalent series resistance (ES).. The resistor placed between ADD and PDD is Ω to 0 Ω in value.. Design the AGND and PGND carefully and connect both grounds at where the lowest current density exists on the PCB.. Because the ADN and the MOSFETs take huge amounts of current, heat can build up quickly. For stable component performance, a metal heat sink design can relieve the component heat dissipation problem, especially at the PWM MOSFET side. When designing your layout, it is good practice to leave adequate space between the components. To ensure that your heat sink design is adequate, contact Analog Devices for design review support of your layout before fabricating the PCB. ev. B Page of

9 EALUATION BOAD SCHEMATIC AND ATWOK AN-9 Figure 9 shows the schematic of the ADN evaluation board (ersion.). Note that THPAD, shown as Pin in this schematic, refers to the exposed thermal pad underneath the chip set. Connect THPAD to AGND to dissipate heat. ITEC TEC LIM ILIMH ILIMC W 0K EF EF TECP Q 0K TP 9 0 U W 0K W 0K S 0mOhm C0.nF 0K 0K B 0K C9 00pF.K LPGATE LNGATE LFB CS ITEC TEC LIM ILIMH C 00nF THPAD TP COMPSW ILIMC PDD INP 0K FDC00C SFB TECN PGND INM W 0K 0K TP TP Q SNGATE OUT 00K L.uH ADNACPZ TH K 0 C 0uF SW INP TEMPSET C 0uF 9 SPGATE INM CMIN PDD AGND PGND LP PDD OUT OUT COMPOSC EF DD C9 0uF C 0uF C 0uF C 0uF C uf PDD FDC00C EF 00nF SYNCIN/SD SYNCO SS/SB FEQ AGND TMPGD PHASE C ADD TEMPSET LP LP K 99K CF 0 9 ADD I NP PDD 0 00K SYNCO 9 K 00 CI 0nF SYNCIN PDD CD D OUT C nf CIP CIP OUT P NP B C 00nF NP NP NP OUTB PDD CDD CMIN CIP OUT S SWPA C 00nF PHASE C 00nF D LED Figure 9. ADN Evaluation Board Schematic OUT S SWPT CI uf 0 GND CI 0nF 9 CMIN AGND S SWPT CMIN S SWPT I CI 0nF P M P P P P.9K K 9K 99K 99K I M 9K I K I I.9K S SWPT CI 00nF CD 0uF 0 CI nf CD.uF 9 S SWPT D 00K D 00K D.9K D D.K CDD CDD CD.uF 9.9K 9 0 CD uf CD 0nF ev. B Page 9 of

10 Figure 0. Top Layer Silkscreen Figure. Top Layer Layout ev. B Page 0 of

11 Figure. Bottom Layer Layout (Mirrored) ev. B Page of

12 NOTES 00 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN09-0-9/0(B) ev. B Page of