The Design and Simulation of Radio Frequency Narrow Band Low Noise Amplifier with Input, Output, Intermediate Matching

Transcription

1 The Design and Simulation of Radio Frequency Narrow Band Low Noise Amplifier with Input, Output, Intermediate Matching Pramod K B Kumaraswamy H.V 1, Praveen K B 2 Department of Electronics Engineering Jain University Bangalore, Karnataka, India pramod63putta@gmail.com 1,2 Department of Telecommunication 1 R. V. College of Engineering, Bangalore, India 2 Dr. Ambedkar Institute of technology, Bangalore, India 1 kumaraswamyhv@rvce.edu.in, 2 prvn.guru@gmail.com Abstract- This paper presents the design and simulation of 2- stage low noise amplifier(lna) for the application of L-band used for mobile satellite communications by using microstrip technology and focusing on development of low noise amplifier operating from 0.6GHz-1.2GHz by using Enhancement Mode Pseudomorphic HEMT ATF34143 from Avago Technologies. The design circuit uses lumped elements to implement with input, output, intermediate matching networks and purpose 2- stage is to achieve good gain. Input and output matching network is to produces 50Ω impedance for maximum power transfer. The target simulation are gain (S21) with 30 db, noise figure (NF) with 1dB throughout the band from 0.6G -1.2GHz, Input Return loss -16dB and Output Return Loss -18dB. A 2- stage LNA has successfully designed with 35 db forward gain, 0.56 db noise figure, Input Return loss -16dB to -27dB and Output Return Loss -19dB to -23dB by using Advance Wireless Revolution (AWR) Microwave office tool. KEYWORDS--Advance Wireless Revolution, Low Noise Amplifier, Radio Frequency, Noise Figure, Mobile Satellite Communications and Pseudomorphic High Electron Mobility Transistor. I. INTRODUCTION The low noise amplifiers (LNA) are electronic voltage amplifier used to amplify possibly very weak signals from the antenna for the reduction of external as well as internal noise of the circuit. This paper gives complete idea about how to design the LNA step by step starting from stability enhancement circuit, Small scale analysis, Biasing and finally matching and presents a low noise amplifier with a very low noise figure, high gain, bandwidth of 950MHz and good VSWR is achieved by proper choice of input and output matching and interstate matching for two stage is designed. In this reference [1] presented on LNA design with matching network at 5.0 GHz is implemented in TSMC 0.18 μm CMOS technology. The simulation recorded that the amplifier gain S21 is 25.3 db. The input insertion loss S11 is db, overall noise figure (NF) is 2.2dB, and the output insertion loss S22 is -12 db. References [2-4] presented that LNA which are able to provide gain to input signal powers up to -15 dbm without degrading linearity or adding much noise. Such properties enable the wireless receiver to operate in hostile communication environments. In low noise amplifier design, the most important factors are forward gain, low noise, matching, and stability. [5] Have proposed a model of the double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology, which is also an application for the LNA. The proposed LNA operates at 5.0 GHz frequency used in IEEE standard a WLAN. II. LOW NOISE AMPLIFIER CIRCUIT SYNTHESIS Selection of the transistor is the crucial stage in LNA design. Any transistor has its NF maximum available gain (MAG) and minimum intrinsic noise figure (NFmin). Therefore, after adding the matching and biasing sections, we cannot achieve gain more than MAG and Noise figure less than NFmin. To achieve a gain over 30 db, a 2-stage LNA is designed, because the noise figure of the next stages is reduced by a factor equal to the total gain till that stage. From the comparison from many transistors like ATF 34143,ATF etc., it is observed that Transistor ATF34143 has the Noise Figure of 0.5 db at bias point of 4V, IDS=60 ma 2 GHz and associated Gain of 17.5dB. Series Resistance Stabilization Method Steps: 1. Convert Transistor S-parameters to Z-Parameters 2. Add series resistance to real part of Transistor Z22 3. Convert composite Z-Parameters to S-Parameters 4. Check K The LNA design formula and equation were referred to [9]. A low-noise amplifier is designed using a device s noise modal or noise parameters and S-parameters [16]. In a low noise amplifier, the transistor s input is matched for optimum noise figure and the transistor has output is conjugate matched with 50Ω system impedance for a maximum gain. In reference [6-8], a common gate topology has been used to realize wide-band characteristics but the common-gate topology usually has related higher noise figure (NF) than common-source topology. III. STABILITY The main way of determining the stability of a device is to calculate the Rollett s stability factor (K), which is calculated using a set of S-parameters for the device at the frequency of operation /13/$ IEEE

2 The parameters must satisfy K > 1 and < 1 for a transistor to be unconditionally stable. Once we have calculated the K factor and find the device to be unconditionally stable we can calculate the Maximum available gain (MAG):- 1 1 IV. STABILITY ENHANCEMENT A. Series Resistance Stabilization Method Steps: Convert Transistor S-parameters to Z-Parameters Add series resistance to real part of Transistor Z22 Convert composite Z-Parameters to S-Parameters Check K (1) B. Design Of Intermediate Matching Network The 1st stage has no matching on the output and as we require a good output return loss we should match to S22*. Note S22 will now have been modified by adding the input matching circuit and will have to design the matching circuit to be the conjugate of S22 modified (This is because S22 is looking into the device and the conjugate will looking towards the matching circuit. The intermediate matching section should transfer the impedance from the S22 ( j27.855) modifiedd to the S11 of the 2nd stage transistor (ATF-34143). Figure 3. Interstage matching network Figure 1. Stabilization circuit After substituting the values of S parameters in the above equations, the values of Z parameters obtained are given below V. MATCHING CIRCUIT The matching for lowest possible noise figure over a band of frequencies requires that particular source impedance be presented to the input of the transistor. The noise optimizing source impedance is called as Gopt, and is obtained from the manufacturer s data sheet. A. Optimum Noise Match: The matching for lowest possible noise figure over a band of frequencies requires that particular source impedance be presented to the input of the transistor. The noise optimizing source impedance is called as Gopt, and is obtained from the manufacturer s data sheet. The design of intermediate matching network is shown in the figure 3. The circuit is designed for the frequency 900MHz. The characteristic impedance Z0 = 50. VI. OUTPUT MATCHING CIRCUIT The above figure 4 shows the schematic of output matching network followed by interconnecting the MLINS and MTEE for layout purpose. In order to improve the gain and noise response of the second stage we need to provide the RL ( i). In order to improve the gain and noise response of the final stage we need to provide the RL = ROUT* given by: Γ 1 11 Γ This composite design using ideal elements was then optimized. Finally, the ideal elements were replaced with vender elements and the design was again optimized. After this step, the layout process was started. The layout process involved interconnecting appropriate bends, tees, and MLINs to the optimized LNA design with vender elements. This composite design using ideal elements was then optimized. Finally, the ideal elements were replaced with vender elements and the design was again optimized. Figure 2. Input matching circuit schematic. Figure 4. Output matching circuit schematic

3 After this step, the layout process was started.the layout process involved interconnecting appropriate bends, tees, and MLINs to the optimized LNA design with vender elements. Figure 8. schematic of input matching circuit Figure 5. Ideal elements circuit The above circuit shows the input matching circuit. The input matching circuit is matched to noise optimizing source impedance called as Gopt, and is obtained from the manufacturer s data sheet. The combined circuit of input matching, output matching and interstage matching is shown in the above figure 5.The input matching is done by L matching. The interstage and output is done by T matching. Figure 9. layout of input matching circuit Figure 6. vender elements circuit The process of layout involves the interconnection of MLINS, Tees between the elements. The layout obtained for the input matching network shown in figure 9 is shown in above figure 10.The layout has certain constraints that the width and the length of MLIN, MTEE, should be not less than 0.025mm. The ideal elements are replaced by vender components which are shown in the above figure 6. VII. IMPLEMENTATION OF THE DESIGN. The grounding must be done using via. The design is implemented on FR4 substrate with the relative permittivity r=4.4 with a height of 1.6mm. The substrate thickness is chosen to be 0.035mm, Rho=1.The below figure 7 shows the sub circuit of final schematic of an amplifier, the first sub circuit represents the input matching network. Figure 10. Schematic of first stage The figure 10 shows the first stage of the amplifier. The selected device will not be stable, so the device is made unconditionally stable by adding resistive loading, which is one of the methods to make the device stable for the entire range of frequency. Figure 7. Sub circuit of the complete schematic. This circuit component models a length of Micro strip Transmission Line. The model assumes a Quasi-TEM mode of propagation and incorporates the effects of dielectric and conductive losses. Figure 11. layout of first stage The supply voltage to the drain and the gate o f the transistor are provided through MLEF whose arm is

4 extended through MLIN. The layout of first stage of the stabilised transistor is shown in the figure 11. The transistor and resistors makes use of MLIN and tee for connection purpose.the recommended ratio of width and length should not be lessthan 0.05mm. The grounding is done through vias which has the diameter of 0.254mm. The ratio of width and length should not be lessthan Figure 15. layout of second stage The layout of second stage makes use of two MCURVEs and MLIN with a length of 5.46mm to reduce the size of final layout that is shown in figure 15. The MCURVE radius should be greater than the Figure 12. Schematic of interstage matching The interstage matching network is matched to the S22 ( j27.855) of first stage of matching network with the S11( j ) of second stage.. The intermediate matching section should transfer the impedance from the S22 modified (after adding input matching network) to the S11 of the 2nd stage transistor. Figure 16. Schematic of output matching circuit The above figure 16 shows the schematic of output matching network followed by interconnecting the MLINS and MTEE for layout purpose. In order to improve the gain and noise response of the second stage we need to provide the RL ( i). Figure 13. layout of intermediate matching The corresponding layout of intermediate matching circuit is shown in the above figure 13. Figure 17. layout of output matching circuit The layout of output matching network is shown in the above figure 17. Figure 14. Schematic of second stage To increase the gain of the amplifier second stage is designed. The second stage is designed in the same way as first using resistive loading. In order to reduce the size of the layout the gate terminal of the transistor is provided with MCURVES which can be shown in the above figure 14. Figure 18. Completee layout of the Schematic The final schematic including input matching, interstage matching and output matching is shown in the figure above

5 18. The input is fed through the input port P1 and the RF out is taken at the output port P2. The necessary and sufficient condition for unconditional stability of the two ports is that MU1 > 1. From the above graph it is shown that geometric stability factor is greater than one and the condition is satisfied for the full transistor frequency, ranging from 0.5 to 18 GHz. MU2 computes the geometric stability factor of a 2-port. The geometric stability factor computes the distance from the center of the Smith Chart to the nearest unstable point of the input source plane.the necessary and sufficient condition for unconditional stability of the two port is that MU2 > 1. Figure 19. Complete layout of the Schematic The layout of the schematic shown in figure 19 is shown in the above figure 20.The 3x3 pads are used to provide supply to the gate and the drain of the transistor. VIII. RESULTS ANALYSIS Figure 21. Transducer Gain (GT) and Available Gain (GA). Figure 20. Graph of Rollett's stability factor (K), supplemental stability factor (B1), geometric stability factor (Load), geometric stability factor (Source) The main way of determining the stability of a device is to calculate the Rollett s stability factor (K), which is calculated using a set of S-parameters for the device at the frequency of operation. The stability condition is satisfied which is shown in the above figure 20. The Rollett s stability factor (K) is also checked for the transistors entire frequency range. From the above figure we can determine that the stability factor is greater than one and the device is stable for the frequency ranging from 0.5 to 18 GHz. B1 is one of the parameter of stability; it is called as supplemental stability factor for a two port. This factor should be greater than 0 for the device to be stable. This measurement is applicable to 2-port circuits only. MU1 computes the geometric stability factor of a 2-port. The geometric stability factor computes the distance from the center of the Smith Chart to the nearest unstable point of the output load plane. The transducer power gain is the ratio of the power delivered to the load to the power available from the source. The transducer power gain is given by G T = P Power delivered to the load / P Power available from the source. From the above shown Figure 21, it is observed that the transducer power gain ranges from 33.59dB to db for the frequency ranging from 0.8GHz to 1 GHz. The available gain (also known as the available power gain) is the ratio of the power available from the network to the power available from the source. The available gain is given by G A = P Available form the network / P Available form the source The available gain is measured for the required frequency, ranging from 0.8 to 1GHz. The available gain varies from 33.65dB to 31.08dB which can be seen from the above shown in figure 21. Figure 22. Noise Figure and Minimum Noise Figure Noise Figure is the noise factor expressed in db. The noise factor/ figure can be displayed as cascaded from the starting point to the output of the block.the "Ideal" noise factor option produces results similar to spreadsheet computations, where compression and impedance mismatch effects are ignored.

6 From the above figure 22, it is seen that the noise figure varies from 0.4dB to dB which is less than the required value.the Noise Figure of the Low Noise Amplifier has to be made as low as possible. NFMin computes the minimum noise factor as a ratio. This measurement computes what the minimum noise factor would be with an optimum source termination. NFMin shown in the above graph shows that it is varying from dB to dB from the frequency 0.8dB to 1dB Figure 23. Input Return Loss and Output Return Loss The above figure 23 shows that the return loss varies from dB to dB for the frequency ranging from 0.8GHz to 1GHz.The return loss has to be in negative values.s11 is the ratio of the reflected voltage to the incident voltage at an input port when looking from the start test point towards the end test point. This measurement displays the overall cascaded S11 versus frequency. Return loss or Reflection loss is the reflection of signal power resulting from the insertion of a device in a transmission line. Input return loss is a scalar measure of how close the actual input impedance of the network is to the nominal system impedance value. S11 is equivalent to the reflected voltage magnitude divided by the incident voltage magnitude. The above graph 23 shows that the return loss varies from dB to dB for the frequency ranging from 0.8GHz to 1GHz The output return loss has a similar definition to the input return loss but applies to the output port (port 2) instead of the input port. Figure 24. Input VSWR and Output VSWR VSWR is a Voltage Standing Wave Ratio. SWR is usually defined as VSWR. The ratio of the standing wave maximum voltage to the standing wave minimum voltage defines the VSWR. The VSWR value 1.4:1 denotes maximum standing wave amplitude that is 1.4 times greater than the minimum standing wave value. Output VSWR relates to the magnitude of output port. From the above figure 24, it is seen that the VSWR ranges from to for the frequency.08 to 1 GHZ. Output Voltage Standing Wave Ratio relates to the magnitude of output port. The output VSWR varies from to 1.146, which can be seen from the above graph figure 24.It relates to the magnitude of the voltage reflection coefficient and hence to the magnitude of S22 for the output port. IX. CONCLUSION In this paper, a Narrow Band Low Noise Amplifier (LNA) circuit is designed successfully for frequency bandwidth of 600MHz (0.6GHz to 1.2GHz) 35 db forward gain, 0.56 db noise figure, Input Return loss -16dB to -27dB and Output Return Loss -19dB to -23dB throughout the frequency band using E-PHEMT ATF34143 by Avago technologies with 1.4:1 VSWR ratio. Circuit simulation is done in AWR Microwave Office 2010 with very good overall performance apart from the ultra low noise result. REFERENCES [1] Ravinder Kumar1, Munish Kumar2, and Viranjay M, Srivastava1DESIGN AND NOISE OPTIMIZATION OF RF LOW NOISE AMPLIFIER FOR IEEE STANDARD A WLAN Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan , India. [2] Nazif Emran Farid, Arjuna Marzuki, and Ahmad Ismat, A variable gain 2.5 GHz CMOS low noise amplifier for mobile wireless communications, Proc. of 9th IEEE Int. Conf. of communications,kuala Lumpur, Malaysia, Dec. 2009, pp [3] Ming Hsien Tsai, S. Hsu, Fu Lung Hsueh, Chewn Pu Jou, Sean Chen, and Ming Hsiang, A wideband low noise amplifier with 4 kv HBM ESD protection in 65 nm RF CMOS, IEEE Microwave and Wireless Components Letters, vol. 19, no. 11, pp , Nov [4] Bo Huang, Chi Hsueh Wang, Chung Chun Chen, Ming Fong Lei, Pin Cheng Huang, Kun You Lin, and Huei Wang, Design and analysis for a 60 GHz low noise amplifier with RF ESD protection, IEEE Trans. on Microwave Theory and Techniques, vol. 57, no. 2, pp , Feb [5] Viranjay M. Srivastava, K. S. Yadav, and G. Singh, Analysis of double gate CMOS for double-pole four-throw RF switch design at 45-nm technology, J. of Computational Electronics, vol. 10, no. 1-2, pp , June [6] Hyung Jin Lee, Dong Sam Ha, and Sang S. Choi, A systematic approach to CMOS low noise amplifier design for ultra wideband applications, Proc. of Int. Symp. on Circuit and System, Kobe, Japan, May 2005, pp [7] Wei Chang Li, Chao Shiun Wang, and Chorng Kuang Wang, A 2.4 GHz/3.55 GHz/5 GHz multiband LNA with complementary switched capacitor multi-tap inductor in 0.18 μm CMOS, IEEE National Science Council (NSC) Taiwan, 2006, pp.1-4. [8] Roee Ben Yishay, Sara Stolyarova, Shye Shapira, Moshe Musiya, David Kryger, Yossi Shiloh, and Yael Nemirovsky, A CMOS low noise amplifier with integrated front-side micro-machined inductor, Microelectronics Journal, vol. 42, no. 5, pp , May [9] Nam Jin, A low power GHz ultra wide band CMOS low noise amplifier with common gate input stage, Current Applied Physics, vol. 11, no. 1, pp , Jan