ECONOMY HIGH-SPEED PWM CONTROLLER

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1 SLUSD -- MARCH REVISED AUGUST 00 ECONOMY HIGH-SPEED PWM CONTROLLER FEATURES D Peak Current Mode, Average Current Mode, or Voltage Mode (with Feed-Forward) Control Methods D Practical Operation Up to MHz D 0-ns Propagation Delay to Output D ±.-A Peak Totem Pole Outputs D 9-V to 0-V Nominal Operational Voltage Range D Wide Bandwidth Error Amplifier D Fully Latched Logic with Double Pulse Suppression D Pulse-by-Pulse Current Limiting D Programmable Maximum Duty Cycle Control D Under -Voltage Lockout with Hysteresis D Trimmed.-V Reference with UVLO D Same Functionality as UC8 and UC8 APPLICATIONS D Off-Line and DC/DC Power Supplies D Converters Using Voltage Mode, Peak Current Mode, or Average Current Mode Control Methods D Single-Ended or Two-Switch Topology Designs ORDERING INFORMATION T A= T J -- 0 C to 0 C DESCRIPTION The UC80 and are fixed-frequency PWM controllers optimized for high-frequency switched-mode power supply applications. The UC80 is a single output PWM for single-ended topologies while the offers dual alternating outputs for double-ended and full bridge topologies. Targeted for cost effective solutions with minimal external components, UC80x include an oscillator, a temperature compensated reference, a wide band width error amplifier, a high-speed current-sense comparator and high-current active-high totem-pole outputs to directly drive external MOSFETs. Protection circuitry includes a current limit comparator with a -V threshold, a TTL compatible shutdown port, and a soft-start pin which will double as a maximum duty cycle clamp. The logic is fully latched to provide jitter free operation and prohibit multiple pulses at an output. An undervoltage lockout section with 800 mv of hysteresis assures low start-up current. During undervoltage lockout, the outputs are high impedance. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. Devices are available in the industrial temperature range of --0 C to 0 C. Package offerings are -pin SOICW (DW), or -pin PDIP (N) packages. OUTPUT EXTERNAL CURRENT PACKAGED DEVICES CONFIGURATION LIMIT REFERENCE PDIP- (N) SOICW-- (DW) Single Yes UC80N UC80DW Dual Alternating No N DW () The DW package are also available taped and reeled. Add an R suffix to the device type (i.e., UC80DWR (,000 devices per reel). PRODUION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright , Texas Instruments Incorporated

2 SLUSD -- MARCH REVISED AUGUST 00 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted () UC80 RATING UNIT Input voltage range, V C, V CC V C, V CC 0 V Output current, I OUT(DC) OUT OUTA, OUTB ±0. A Peak output current, pulsed 0. ms I OUT(pulsed) OUT OUTA, OUTB ±.0 A Capacitive load, C LOAD 00 pf INV, NI, RAMP INV, NI, RAM --0.VtoV Analog inputs V SS, ILIM/SD SS, ILIM/SD REF +0.V, V V Output current, I REF VREF VREF 0 Output current, I -- Soft-start sink current, I SINK_SS SS SS ma Output current, I OUT(EA) EAOUT EAOUT 0 Oscillator charging current, I OSC_CHG -- Power Dissipation at T A = C (all packages) W Operating junction temperature range, T J -- to 0 Storage temperature, T stg -- to 0 CC Lead temperature, mm (/ inch) from case for 0 seconds, T sol 00 () Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. All currents are positive into and negative out of the specified terminal.

3 SLUSD -- MARCH REVISED AUGUST 00 UC80 N PACKAGE (TOP VIEW) UC80 DW PACKAGE (TOP VIEW) INV NI EAOUT RAMP SS VREF VCC OUT VC PGND ILIMREF GND ILIM/SD INV NI EAOUT RAMP SS VREF VCC OUT VC PGND ILIMREF GND ILIM/SD INV NI EAOUT RAMP SS N PACKAGE (TOP VIEW) VREF VCC OUTB VC PGND OUTA GND ILIM/SD INV NI EAOUT RAMP SS 8 DW PACKAGE (TOP VIEW) 0 9 VREF VCC OUTB VC PGND OUTA GND ILIM/SD

4 SLUSD -- MARCH REVISED AUGUST 00 ELERICAL CHARAERISTICS T A =--0 C to 0 C,T J =T A, R T =.kω, C T =nf,v CC = V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE V REF Reference voltage T J = C, I REF =ma.0.0. V Line regulation voltage 0 V V CC 0 V Load regulation voltage ma I REF 0 ma Temperature stability () T (min) <T A <T (max) mv/ C Total output voltage variation () Line, load, temperature.9. V Output noise voltage () 0Hz<f<0kHz 0 μv Long term stability voltage () T J = C, 000 hours mv I SS Short circuit current V REF =0V ma OSCILLATOR f OSC Initial accuracy () T J = C khz Voltage stability () 0 V V CC 0 V 0.%.0% Temperature stability () T (min) <T A <T (max) % Total voltage variation () Line, temperature 0 0 khz V _H High-level clock output voltage.9. V _L Low-level clock output voltage..9 V RAMP(p) Ramp peak voltage ()..8.0 V V RAMP(v) Ramp valley voltage () V RAMP(v-p) Ramp vally-to-peak voltage ()..8.0 ERROR AMPLIFIER V IN Input offset voltage mv I BIAS Input bias current 0..0 I IN Input offset current 0..0 A VOL Open loop gain V V OUT V 0 9 CMRR Common mode rejection ratio. V V CM. V 9 db PSRR Power supply rejection ratio 0 V V CC 0 V 8 0 I OUT(sink) Output sink current V (EAOUT) = V.0. IOUT(src) Output source current V (EAOUT) = V V OH High-level output voltage I (EAOUT) = --0. ma.0..0 V OL Low-level output voltage I (EAOUT) = ma PWM COMPARATOR Unity gain bandwidth ().0. MHz Slew rate () V/μs I BIAS RAMP bias current V RAMP = 0 V μa Maximum duty cycle Minimum duty cycle UC80 80% 90% () 0% % UC80 0% 0% EAOUT zero DC threshold V RAMP = 0 V.0..0 V t DELAY Delay to output time () 0 00 ns () Ensured by design. Not production tested. () Tested as 80% minimum for the oscillator which is the equivalent of 0% for. mv μaa ma V

5 ELERICAL CHARAERISTICS T A =--0 C to 0 C,T J =T A, R T =.kω, C T =nf,v CC = V (unless otherwise noted) SLUSD -- MARCH REVISED AUGUST 00 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SOFT-STA I CHG Charge current V SS = 0. V 9 0 μa I DISCHG Discharge current V SS =.0 V.0. ma CURRENT LIMIT/SHUTDOWN I LIMIT Current limit bias current 0V<V (ILIM/SD) <V ±0 μa ILIMIT Offset voltage UC80 mv I LIMREF Common mode range () UC Current limit threshold voltage V Shutdown threshold voltage..0. t DELAY Delay to output time () 0 80 ns OUTPUT V OL V OH Low-level output voltage High-level output voltage I OUT = 0 ma I OUT = 00 ma.. I OUT = --0 ma.0. I OUT = --00 ma Collector leakage V C = 0 V μa Rise time / Fall time () C LOAD = nf 0 0 ns UNDERVOLTAGE LOCKOUT (UVLO) SUPPLY CURRENT Start threshold voltage Hysteresis Start-up current V CC = 8 V..0 I CC Operating current V INV = V RAMP = V ILIM = 0 V V INV = V () Ensured by design. Not production tested. V V ma THERMAL RESISTANCE PACKAGE θ JA ( C/W) θ JC ( C/W) N () 90 () DW () () () Specified θ JA (junction-to-ambient) is for devices mountied to -square-inch FR PC board with one ounce copper where noted. When resistance range is given, lower values are for -square-inch aluminum PC board. Test PWB is 0.0 inches thick and typically uses 0. mm trace width for power packages and. mm trace widths for non-power packages with a 00x00 mil probe land area at the end of each trace.

6 SLUSD -- MARCH REVISED AUGUST 00 FUNIONAL BLOCK DIAGRAM OSCILLATOR Toggle F/F VC RAMP. V + PWM Latch R T OUTA EAOUT NI Wide Bandwidth Error Amplifier + S D V IN OUTB PGND INV Inhibit 9 μa UC80 VC OUT SS ILIMREF (UC80 Only) ILIM/SD 8 9 V ( Only) V. V ILIM Comparator Shutdown Comparator Internal Bias PGND VREF VCC VCC Good REF GEN VREF Good 9V V GND 0 UVLO Output Inhibit UDG--008

7 SLUSD -- MARCH REVISED AUGUST 00 TERMINAL FUNIONS NAME UC80 TERMINAL I/O O Output of the internal oscillator I DESCRIPTION Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. EAOUT O Output of the error amplifier for compensation GND Analog ground return pin. ILIM/SD 9 9 I Input to the current limit comparator and the shutdown comparator. ILIMREF -- I Pin to set the current limit threshold externally. INV I Inverting input to the error amplifier NI I Non-inverting input to the error amplifier OUT -- O High current totem pole output of the on-chip drive stage. OUTA -- O High current totem pole output A of the on-chip drive stage. OUTB -- O High current totem pole output B of the on-chip drive stage. PGND -- Ground return pin for the output driver stage RAMP I Non-inverting input to the PWM comparator with.-v internal input offset. In voltage mode operation this serves as the input voltage feed-forward function by using the ramp. In peak current mode operation, this serves as the slope compensation input. I Timing resistor connection pin for oscillator frequency programming SS 8 8 I Soft-start input pin which also doubles as the maximum duty cycle clamp. VC -- VCC -- VREF O Power supply pin for the output stage. This pin should be bypassed with a 0.-μF monolithic ceramic low ESL capacitor with minimal trace lengths. Power supply pin for the device. This pin should be bypassed with a 0.-μF monolithic ceramic low ESL capacitor with minimal trace lengths.--v reference. For stability, the reference should be bypassed with a 0.-μF monolithic ceramic low ESL capacitor and minimal trace length to the ground plane.

8 SLUSD -- MARCH REVISED AUGUST 00 APPLICATION INFORMATION + V IN V to V 90 Ω V OUT V Ato0A - + V. μf 0.8 μh 0. μf VCC VREF VC OUTB N 80 kω μf -. kω nf NI OUTA INV ILIM/SD 9 Ω pf 0 kω kω :. μf. kω EAOUT RAMP 8. kω 0 pf 0 nf kω PGND C T 0 pf. kω GND SS μf Figure. Typical Application:. MHz, 8-V to -V DC/DC Push-Pull Converter Using UDG--00 8

9 APPLICATION INFORMATION SLUSD -- MARCH REVISED AUGUST 00 PCB LAYOUT CONSIDERATIONS High speed circuits demand careful attention to layout and component placement. To assure proper performance of the UC80x follow these rules:. Use a ground plane.. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt -A Schottky diode at the output pin serves this purpose.. Bypass VCC, VC, and VREF. Use 0.-μF monolithic ceramic capacitors with low equivalent series inductance. Allow less than -cm of total lead length for each capacitor between the bypassed pin and the ground plane.. Treat the timing capacitor, C T, as a bypass capacitor. ERROR AMPLIFIER Figure shows a simplified schematic of the UC80x error amplifier and Figures and show its characteristics.. V VREF INV 00 Ω EAOUT NI UDG--009 Figure. Simplified Error Amplifier Schematic 9

10 SLUSD -- MARCH REVISED AUGUST 00 APPLICATION INFORMATION 00 GAIN AND PHASE vs FREQUENCY VOLTAGE vs TIME 80 V IN V OUT A V - Gain - db GAIN 0 PHASE k 0 k 00 k M 0 M 00 M f OSC - Frequency - Hz Figure. Open Loop Frequency Response Phase - V SEAout - E/A Output Voltage - V t delay - Delay Time - μs Figure. Unity Gain Slew Rate CONTROL METHODS UC80x UC80x OSCILLATOR I SENSE C T OSCILLATOR RAMP C T. V From Error Amplifier * R SENSE RAMP *. V From Error Amplifier Figure. Voltage Mode Control UDG--000 * A small filter may be required to supress switch noise. UDG--000 Figure. Peak Current Mode Control 0

11 APPLICATION INFORMATION SLUSD -- MARCH REVISED AUGUST 00 OSCILLATOR I R V UC80x kω R T 00 kω DEAD TIME vs TIMING CAPACITANCE. V Blanking I C= I R T D - Dead Time - μs T D 00 μa UDG C T - Timing Capacitance - nf 00 Figure. Oscillator Circuit Figure k TIMING RESISTANCE vs FREQUENCY 0 DEAD TIME vs FREQUENCY. nf. nf R T - Timing Resistance - Ω 0 k 00 nf nf nf 0 pf T D - Dead Time - ns C T = 0 pf C T =nf k 00 nf 0 nf k 0 k 00 k M f OSC - Frequency - Hz Figure 9. Oscillator Circuit 80 0 k 00 k M f OSC - Frequency - Hz Figure 0.

12 SLUSD -- MARCH REVISED AUGUST 00 APPLICATION INFORMATION SYNCHRONIZATION Figure shows a generalized synchronization. Figure shows a synchronozed operation of two units in close proximity. UC80x (Master) UC80x (Slave) VREF 0 μf R T. Ω R T C T N Ω Ω Ω 0. μf 0. μf 0. μf To other slaves Ω C T Ω Local Ramp 0 Ω Local Ramp UDG--000 Figure. Generalized Synchronization UC80x (Master) UC80x (Slave) VREF R T Local Ramp C T UDG--000 Figure. Synchronization of Two Units In Close Proximity

13 APPLICATION INFORMATION SLUSD -- MARCH REVISED AUGUST 00 FEEDFORWARD CIRCUIT VIN RFF UC80x RAMP CFF UDG--000 Figure. Feedforward Technique for Off-Line Voltage-Mode Applications CONSTANT VOLT-SECOND CLAMP CIRCUIT The circuit for the UC80 shown in Figure describes achievement a constant volt-second product clamp over varying input voltages. The ramp generator components, R T and C R are chosen so that the ramp at Pin 9 (ILIM/SD) crosses the -V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional inverter block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. VIN UC80 ILIM/SD 9 OUT CR UDG--000 Figure. Achieving Constant Volt-Second Product Clamp with the UC80

14 SLUSD -- MARCH REVISED AUGUST 00 The circuit for the shown in Figure describes achievement a constant volt-second product clamp over varying input voltages. The ramp generator components, R T and C R are chosen so that the ramp at Pin 9 (ILIM/SD) crosses the -V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional inverter block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. VIN ILIM/SD OUTB 9 OUTA CR UDG--000 Figure. Achieving Constant Volt-Second Product Clamp with the

15 APPLICATION INFORMATION SLUSD -- MARCH REVISED AUGUST 00 OUTPUTS UC80 has one output and has dual alternating outputs. UC80x VCC SATURATION VOLTAGE vs OUTPUT CURRENT VC OUTx V SAT - Saturation Voltage - V Source Figure. Simplified Schematic PWRGND 0 GND Sink I OUT - Output Current - A Figure. V OUT - Output Voltage - V 0 RISE/FALL TIME vs OUTPUT VOLTAGE AND LOAD CURRENT C LOAD =nf t RISE (t FALL )-Time-ns Figure I LOAD - Load Current - A V OUT - Output Voltage - V 0 RISE/FALL TIME vs OUTPUT VOLTAGE AND LOAD CURRENT C LOAD =0nF t RISE (t FALL )-Time-ns Figure I LOAD - Load Current - A

16 SLUSD -- MARCH REVISED AUGUST 00 Open Loop Laboratory Test Fixture APPLICATION INFORMATION The following test fixture is useful for exercising many of the s functions and measuring their specifications. As with any wideband circuit, careful ground and by-pass procedures should be followed. The use of a ground plane is highly recommended. VCC 0. μf V R T. kω C T.0 nf OSCILLATOR VC 0. μf 0 μf V 0 uf RAMP 00 Ω OUTA 0 Ω kω kω 0 kω kω. kω. kω EAOUT 8 kω 8 NI INV SS ERROR AMPLIFIER OUTB PGND GND 0 N80 N80 0 kω 0 μf 9 ILIM/SD VREF 0. μf. kω UDG--00 Figure 0. Laboratory Test Fixture References..-MHz Current Mode IC Controlled 0 -Watt Power Supply, Texas Instruments Application Note Literature No. SLUA0.. The UC8A,B and UC8A,B Enhanced Generation of PWM Controllers, Texas Instruments Application Note Literature No. SLUA.

17 PACKAGE OPTION ADDENDUM -Feb-00 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty UC80DW AIVE SOIC DW 0 Green (RoHS & UC80DWG AIVE SOIC DW 0 Green (RoHS & UC80DWR AIVE SOIC DW 000 Green (RoHS & UC80DWRG AIVE SOIC DW 000 Green (RoHS & UC80N AIVE PDIP N Green (RoHS & UC80NG AIVE PDIP N Green (RoHS & DW AIVE SOIC DW 0 Green (RoHS & DWG AIVE SOIC DW 0 Green (RoHS & DWR AIVE SOIC DW 000 Green (RoHS & DWRG AIVE SOIC DW 000 Green (RoHS & N AIVE PDIP N Green (RoHS & NG AIVE PDIP N Green (RoHS & Eco Plan () Lead/Ball Finish MSL Peak Temp () Level--0C- YEAR Level--0C- YEAR Level--0C- YEAR Level--0C- YEAR N / A for Pkg Type N / A for Pkg Type Level--0C- YEAR Level--0C- YEAR Level--0C- YEAR Level--0C- YEAR N / A for Pkg Type N / A for Pkg Type () The marketing status values are defined as follows: AIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) () MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page

18 PACKAGE OPTION ADDENDUM -Feb-00 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

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High Speed PWM Controller

High Speed PWM Controller application INFO available FEATURES Compatible with Voltage or Current Mode Topologies Practical Operation Switching Frequencies to 1MHz 50ns Propagation Delay to Output High