NJW1262. Analog Signal Input Class-D Amplifier for Piezo Speaker with DC-DC Converter PACKAGE OUTLINE

Transcription

1 Analog Signal Input Class-D Amplifier for Piezo Speaker with DC-DC Converter GENERAL DESCRIPTION The NJW262 is an analog signal input monaural class-d amplifier for Piezo speaker. And a built-in DC-DC converter generates fixed output voltage. Therefore, it realizes 7Vrms@kHz output signal with louder sound and high efficiency. The NJW262 incorporates BTL amplifier, which eliminate AC coupling capacitors, and it is capable of driving Piezo speaker with simple external LC low-pass filters. Class-D operation achieves lower power operation for Piezo speaker, thus the NJW262 is suited for battery-powered applications. PACKAGE OUTLINE NJW262NL2 FEATURES Output Voltage VDD=3.0V to 4.2V VDDO=3.0V@SP MODE VDDO=4.5V@REC MODE Analog Audio Signal Input 2input selector (Speaker Mode and Receiver Mode) -channel BTL Output, Piezo Speaker Driving Built-in DC-DC Converter Built-in Low Voltage Detector Standby (Hi-Z), Soft Start, Soft Mute Control Built-in Pop noise reduction Built-in Short Protector) Built-in Thermal Protection Package Outline: EPCSP32 BLOCK DIAGRAM EQ EQ 2 V DD V DDO IN SP V DD UVLO V DDO UVLO IN PREC Selector Level Shifter OUT P IN NREC EQ 3 Pulse Width Modulator OCP V SS Level Shifter OUT N COM STBYb COM BIAS CONTROL SOFT - LOGIC OSC Pulse Width Modulator TSD OCP SW V SSREG MODE OUT TEST R OSC R OSC2 FB IN- NJW262Ver.4.0_E --

2 PIN CONFIGURATION No. SYMBOL I/O Function 23 V DD Power supply:v DD =3.7 V 28,29 V DDO Output Power supply:v DDO =3 V IN SP I Noninverted signal input (SP Mode) terminal 7 IN PREC I Noninverted signal input (REC Mode) terminal 6 IN NREC I Inversion signal Input (REC Mode) 2 EQ I/O LPF Setting terminal 3 EQ 2 I/O LPF Setting terminal 4 EQ 3 I/O LPF Setting terminal 5 COM I/O Bias terminal 9 SOFT I/O Capacitor connection terminal for soft start 4 STBYb I Standby control terminal 3 MODE I (STBYb =L: Standby) SP/REC mode switch terminal (MODE =H: SP Mode, MODE =L: REC Mode) The mode maintains the logic when the STBYb terminal is started up. 22 R OSC I/O Class-D Amplifier Oscillator resistance connection terminal 0 R OSC2 I/O Switching Regulator Oscillator resistance connection terminal 26,3 V SS GND:V SS =0 V 30 OUT P O Noninverted signal output terminal 27 OUT N O Inversion signal output terminal 2 OUT TEST O Test Pin (50kΩ ground) Should be floating or V SS fixation. 8 SW O Inductor connection terminal 5 V SSREG GND:V SSREG =0 V 2 IN- I/O Phase compensating device connection terminal for switching regulator 20 FB I/O Phase compensating device connection terminal for switching regulator 8 TEST I Test Pin (50kΩ ground), 9,6,7, 24,25,32 Note: V BAT = V DD Note: Do not do floating the input terminal. Should be floating or V SS fixation. pin Should be floating or V SS fixation. TERMINAL CONFIGURATION OUTN TEST IN- FB SOFT SW VSS OUTp VDDO VDDO VSS OUT TEST MODE STBYb COM IN NREC IN PREC V DD R OSC ROSC2 INSP EQ EQ2 EQ3 VSSREG NJW262Ver.4.0_E

3 NJU3555 INPUT TERMINAL Terminal Internal Circuit Vss NJW262 Ver.4.0_E -3-

4 ABSOLUTE MAXIMUM RATINGS (Ta=25 C) PARAMETER SYMBOL CONDITIONS RATING UNIT Supply Voltage V DD V DD -0.3 to +5.5 V DDO V DDO -0.3 to +36 V Input Voltage V IN IN SP, IN PREC, IN NREC, STBYb, MODE, OUT TEST -0.3 to V DD +0.3 V Operating Temperature Topr -40 to +85 C Storage Temperature Tstg -40 to +25 C Power Dissipation P DMAX2 2 layers (EIAJ), T j = 25 C 760 mw P DMAX4 4 layers (EIAJ), T j = 25 C 800 mw Thermal resistance θ ja2 2 layers (EIAJ), T j = 25 C 32 C /W θ ja4 4 layers (EIAJ), T j = 25 C 54 C /W Note ) All voltage are relative to V SS =0V reference. Note 2) Power dissipation is a value in condition where it is mounted on 2-layer/ 4-layer board based on EIA/JEDEC. Note 3) The IC must be used inside of the Absolute maximum ratings. Otherwise, a stress may cause permanent damage to the LSI. Note 4) De-coupling capacitors must be connected between each power supply terminal and GND (V DD -V SS, V DDO -V SS ). Note 5) The maximum power dissipation in the system is calculated, as shown below. TjMAX [ C] Ta [ C] PDMAX = θ ja [ C / W] Pdmax: Maximum Power Dissipation, Tjmax: Junction Temperature = 25 C Ta: Ambient Temperature, θja: Thermal Resistance of package = 32 C/W P D = = 32 / W 570[ mw] NJW262Ver.4.0_E

5 NJU3555 ELECTRICAL CHARACTERISTICS DC Characteristics T a = 25 C,V DD = 3.7 V, V DDO = 3.0 V(SP Mode), V DDO = 4.5V (REC Mode), V SS = V SSREG = 0.0 V, Load=.5 µf, R OSC = 82 kω, R OSC2 = 82 kω, C LPF = 330 pf, Cc=0.033 µf, Output Filter: [L OUT = 22µH, R DAMP = 3.9 Ω] SW regulator: [L SW = 6.8µH, C SW = 20µF+ 0.µF, C cmpn = 4.7 nf, R cmpn = 68 kω] Input Signal :IN SP = 00 mvrms, IN PREC - IN NREC =00 mvrms, Input Frequency= khz PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Supply Voltage V DD V Boost voltage Output Driver On-state Resistance (High-side) Output Driver On-state Resistance (Low-side) Switching Regulator Output Driver On-state Resistance Input Impedance V SWSP SP Mode V V SWREC REC Mode V R ONHSP SP Mode, OUT P, OUT N V OUTP, N = V DDO - 0. V Ω R ONHREC REC Mode, OUT P, OUT N V OUTP, N = V DD - 0. V Ω R ONLSP SP Mode, OUT P, OUT N V OUTP, N = 0. V Ω R ONLREC REC Mode, OUT P, OUT N V OUTP, N =0. V Ω R ONSW SW V SW = 0. V Ω R INSP IN SP kω R INPREC IN PREC kω R INNREC IN NREC kω Operating Current (Standby) I ST STBYb: "L",No Load - - µa SP Mode, I BATSP - 4 ma Non-LC Filter, No Load Operating Current (No signal input) REC Mode I BATREC ma Non-LC Filter, No Load NJW262 Ver.4.0_E -5-

6 PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT V IH STBYb, MODE Pin.5 - V DD V Input Voltage V IL STBYb, MODE Pin V Input Leakage Current I LK STBYb, MODE Pin - - ± µa SW Off Leak Current I LKSW SW Pin - - ± µa OUT P Ground Resistance R OUTP OUT P Pin kω OUT N Ground Resistance R OUTN OUT N Pin kω Class-D Amplifier Oscillation Frequency f OSCD khz Switching Regulator Oscillation Frequency f OSCSW khz Soft Start Resistance R SST SOFT Pin kω Soft Mute Resistance R SMT SOFT Pin kω Start-up Time T ON ms Stop Time T OFF ms Class-D Amplifier Voltage Gain Av SP SP Mode, No Load C LPF =00 pf db Av REC REC Mode, No Load C LPF =00 pf db MODE Setup Time T STUP Refer to Figure µs MODE Holding Time T HLD Refer to Figure µs Offset Voltage V OFFSET REC Mode 2ms After OUT P and OUT N pin start switching mv STBYb MODE T STUP T HLD Figure : STBYb/MODE input timing NJW262Ver.4.0_E

7 NJU3555 AC Characteristics T a = 25 C,V DD = 3.7 V, V DDO = 3.0 V(SP Mode), V DDO = 4.5V (REC Mode), V SS = V SSREG = 0.0 V, Load =.5 µf, R OSC = 82 kω, R OSC2 = 82 kω, C LPF = 330 pf, Cc=0.033 µf, Output Filter: [L OUT = 22µH, R DAMP = 3.9 Ω] SW regulator: [L SW = 6.8µH, C SW = 20µF+ 0.µF, C cmpn = 4.7 nf, R cmpn = 68 kω] Input Signal :IN SP = 00 mvrms, IN PREC - IN NREC =00 mvrms, Input Frequency= khz PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT THD+N THD+N SP SP Mode, V OUTSP =2.5 Vrms % THD+N REC REC Mode V OUTREC = Vrms % Maximum Output Voltage V OUTSP SP Mode, THD+N=2 % V rms V OUTREC REC Mode, THD+N=2 % Vrms S/N SN REC MODE, V OUTREC = Vrms db A-weight Noise Floor V N REC MODE, A-weight µvrms Note) A noise by the Class-D amplifier oscillation frequency and the switching regulator oscillation frequency may be felt in receiver mode. Therefore, please test the circuit carefully to fit your application. NJW262 Ver.4.0_E -7-

8 FUTIONAL DESCRIPTION Signal Input Terminal (IN SP, IN PREC, IN NREC ) Analog signal input. The input signal is selected by the operational mode. Capacitor connection terminal for LPF (EQ, EQ2, EQ3) The amount of current passing through a capacitive load increases proportionately with frequency of audio signal. Input filters should be put in the input line to reduce load current at high frequency-band. The input low pass filters are composed of feedback resister (R ) and capacitor (C LPF ). Refer to the following expression. R = 20kΩ, C LPF = 330pF flpf = = 4.0[kHz] 2 R C kΩ 330pF LPF Figure 2: Input LPF composition Signal Output Terminal (OUT P, OUT N ) The output signals are PWM signals, which will be converted to analog signal via external 2nd-order or higher LC filter. Should be connected to the damping resistor (R DAMP ) between OUT P pin and coil, and between OUT N pin and coil to reduce the current consumption with signal-input close to cutoff-frequency of LPF (f c ). Set the value of LOUT, CL, and RDAMP to become Q<. Refer to the following expression. f c L OUT =22µH, C L =.5µF, R DAMP =3.9Ω, Equivalent series resistance of L (R DCR ) =0.8Ω = = 9.6[kHz] 2 2L C µ H.5µ F Q = R DAMP OUT L + R DCR LOUT 2 C L = 3.9Ω + 0.4Ω 22µ H µ F R =20[kΩ] NJW262Ver.4.0_E

9 NJU3555 Standby Terminal (STBYb) By setting the STBYb pin to L level, it switches the NJW262 into standby condition. During the standby condition, output pins (OUT P, OUT N, SW) become high impedance and class-d amplifier output is connected with V SS with about 00kΩ. Keep the STBYb pin to L level at least 3.3ms once switched into the standby condition. For normal operation, the STBYb pin requires H level. Time from the standby release to class-d power amplifier operation is 6.7ms(TYP). Do not change to the standby mode until the power amplifier operation. Set the standby mode at power supply ON/OFF. Capacitor connection terminal for soft start (SOFT) Capacitor connection terminal for soft start and soft mute. V DD R SFT SOFT R SFT =50[kΩ] C SFT =0.[µF] R SFT C SFT V SS Step-up switching regulator The switching regulator is used as power supply (V DDO ) for power amplifier of class-d. The PWM controlled switching regulator works with external components, which are coil, capacitor, Schottky barrier diode. NJW262 Ver.4.0_E -9-

10 Mode SP/REC mode selection terminal. The output power-supply voltage, the input selector, and the voltage gain change when the mode is switched. MODE= H :SP Speaker Mode Audio input terminal: IN SP (Shingle end input) Class-D amplifier output power-supply voltage: Step-up switching regulator R VSWSP =.0V + = 3.0V ( TYP) R 2SP Voltage gain: 27.6 db (TYP) MODE= L REC Receiver Mode Audio input terminal: IN PREC IN NREC (Difference input) Class-D amplifier output power-supply voltage: Step-up switching regulator R VSWREC =.0V + = 4.5V ( TYP) R 2REC Voltage gain: 5. db (TYP) Note) Reset it when you switch MODE. (STBYb L") Switching regulator circuit Low Voltage Detector When the power-supply voltage drops down to below V DD, the output driver is turned off output pins (OUT P, OUT N, SW) become high impedance and class-d amplifier output is connected with V SS with about 00kΩ NJW262Ver.4.0_E

11 NJU3555 Short Circuit Protection The short-circuit protection circuit operates at the condition of the following. -Short between OUT P and OUT N - Power supply short and earth fault of OUT P terminal - Power supply short and earth fault of OUT N terminal - Power supply short of SW terminal When OUT P and OUT N of the short-circuit protection circuit operates, the OUT P and OUT N become high impedance and class-d amplifier output is connected with V SS with about 00kΩ. It restarts by pulse-by-pulse of built-in clock of class-d amplifier. When SW terminal of the short-circuit protection circuit operates, the SW terminal become high impedance. It restarts by pulse-by-pulse of built-in clock of the switching regulator. Note) * The detectable current and the period for the protection depend on the power supply voltage, chip temperature and ambient temperature. *2 The short protector is not effective for a long term short-circuit current but for an instantaneous accident. Continuous high current may cause permanent damage to the NJW262. Thermal protection When the junction temperature is more than specified value, the output driver is turned off output pins (OUT P, OUT N, SW) become high impedance and class-d amplifier output is connected with V SS with about 00kΩ. When the junction temperature is less than specified value, protection is released. OUT TEST pin This pin is JRC s test pin. TOTAL HARMONIC DISTORTION MEASUREMENT CIRCUIT NJW262 Ver.4.0_E --

12 TYPICAL APPLICATION CIRCUIT Recommended Parts CL: VSLBP25E00-T(muRata) CSW: GRM3CB3E06KA75L (murata) 2 CDD: GRM3CB3E06KA75L(muRata) CDD2,CSW2, CSFT: GRM55B3E04KA87D(muRata) CCSP, CCPREC, CCNREC: GRM033B0J333KE0D(muRata) CLPF, CLPF2: GRM55BH33KA0D(muRata) CCM: GRM55B3A05KE5D(muRata) LSW: LQH44PN6R8MPO(muRata) LOUT: LQH44PN220MP0(muRata) DSW: RSX20VA-30(ROHM) RDAMP: ERJ-4YJ3R9U(Panasonic) specifiedparts Rosc, Rosc2 = RK73HJTTD8202F(KOA) Note) De-coupling capacitors must be connected between each power supply terminal and GND (V DD -V SS, V DDO -V SS ). Note) C DD2 (V DD -V SS ) should be connected at a nearest point to the IC on PCB. Note) V SS and V should be connected at a nearest point to the IC on PCB. Note) IN SP, IN PREC, IN NREC, EQ, EQ 2 and EQ 3 should be not designed near OUT P, OUT N and SW, which emit PWM noise. Note) The transition time for MODE and STBYb signals must be less than 00µs. Otherwise, a malfunction may be occurred. Note) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please test the circuit carefully to fit your application. Note) The speaker should be designed at a near the IC. [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights NJW262Ver.4.0_E

13 NJU3555 PACKAGE INFORMATION NJW262 Ver.4.0_E -3-

14 [CAUTION] The specifications on this databook are only given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights NJW262Ver.4.0_E