SERVICE MANUAL 5100 SERIES PORTABLE RADIO. APCO Project 25 Conventional Trunked SMARTNET / SmartZone Analog FM Conventional

Transcription

1 SERVICE MANUAL DIGITAL/ANALOG PORTABLE RADIO 00 SERIES PORTABLE RADIO APCO Project Conventional Trunked SMARTNET / SmartZone Analog FM Conventional VHF and Watts UHF and Watts 00 MHz and. Watts 00 MHz and Watts. VDC Part No. xxxxx Part Number: CD December 00 Supersedes: CD; /0

2 xx SERIES PORTABLE VHF, UHF, 00/00, 00 MHz PROJECT CONVENTIONAL AND TRUNKED ANALOG CONVENTIONAL SMARTNET /SMARTZONE. VDC W (VHF), W (UHF),.W (00 MHz) W (00 MHz) Part No. xxxx0 Copyright 00 by the EFJohnson Company The EFJohnson Company, which was founded in, provides wireless communication systems solutions for public safety, government, and commercial customers. The company designs, manufactures, and markets conventional and trunked radio systems, mobile and portable subscriber radios, repeaters, and Project digital radio products. EFJohnson is a wholly owned subsidiary of EFJ, Incorporated. Viking Head/EFJohnson logo, Call Guard, PCConfigure, and PCTune are trademarks of the EFJohnson Company. SMARTNET, SmartZone, SecureNet, Call Alert, and Enhanced Private Conversation are trademarks of Motorola, Inc. All other company and/or product names used in this manual are trademarks and/or registered trademarks of their respective manufacturer. The IMBE voice coding technology embodied in this product is protected by intellectual property rights including patent rights of Digital Voice Systems, Inc. Information in this manual is subject to change without notice. Covers Firmware Versions: 00../../../PCConfigure..0

3 TABLE OF CONTENTS TABLE OF CONTENTS GENERAL INFORMATION. SCOPE OF MANUAL RADIO DESCRIPTION General New 00/00 MHz Band Information Analog/Digital Operation Operating Protocols Full and Limited Keypad Models Systems, Channels, and Zones Programming Alignment PRODUCT WARRANTY PART NUMBER BREAKDOWN TRANSCEIVER IDENTIFICATION ACCESSORIES FACTORY CUSTOMER SERVICE RETURNS FOR REPAIRS REPLACEMENT PARTS INTERNET HOME PAGE INTRINSICALLY SAFE INFORMATION... Introduction Definitions Possible Ignition Sources Intrinsically Safe and Nonincendive Ratings... Classification of Hazardous Areas and Atmospheres SECURE COMMUNICATION RADIO HARDWARE CHANGES RF Module Changes Logic and UI Board Changes BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION. BATTERY INFORMATION Battery Removal/Installation Battery Charging Preventing Loss of Encryption Keys Battery Care BELT CLIP INSTALLATION ACCESSORY INSTALLATION TRANSCEIVER DISASSEMBLY Separating Front Cover and Chassis Removing RF and Logic Boards From Chassis. Removing UI (User Interface) Board Removing Switch assembly OPERATION. GENERAL TRANSCEIVER PROGRAMMING. PROGRAMMING SETUP COMPUTER DESCRIPTION USING THE PCCONFIGURE SOFTWARE.. CLONING PROCEDURE CIRCUIT DESCRIPTION. GENERAL OVERVIEW Introduction Analog Mode Project Digital Mode VHF RF BOARD (Version C) Receiver Synthesizer Transmitter UHF RF BOARD (VERSION C) Receiver Synthesizer Transmitter /00 MHz RF BOARD (VERSION C)... Receiver Synthesizer Transmitter RF BOARD OVERVIEW (VERSION A/B).0. VHF/UHF RF BOARD (VERSION A/B)... Frequency Generation Unit (FGU) Antenna Switch Receiver Front End Receiver Back End Transmitter MHz RF BOARD (VERSION A/B).... Frequency Synthesis Antenna Switch Receiver Front End Receiver Back End Transmitter USER INTERFACE BOARD (ALL) Introduction Microcontroller (U) Memory Graphical Display LOGIC BOARD (VERSION C) Introduction Digital Signal Processing Overview Receive Signal Path LOGIC BOARD (VERSION A/B) Introduction Digital Signal Processing Overview Receive Signal Path ii

4 TABLE OF CONTENTS TABLE OF CONTENTS (CONT D) Transmit Signal Path ADSIC (U) AUDIO CIRCUIT (VERSION A/B) Receive Audio Circuit Transmit Audio Circuit ALIGNMENT PROCEDURE. GENERAL Introduction Tune Software PCTune Version Required MAIN SCREEN MENU BAR DESCRIPTION File Menu Radio Menu Transfer Menu Tools Menu Help Menu TUNING PROCEDURE Connecting Test Setup Starting and Configuring PCTune DIGITAL PERFORMAE TESTS General Receive Test Setup Receive Sensitivity Test Transmitter Tests ANALOG PERFORMAE TESTS General Receiver Performance Tests Transmitter Performance Tests PARTS LIST Chassis, Hardware, Misc RF Board (A00) Logic Board (A00) Logic Board (A00) User Interface Board (A00) User Interface Board (A00) Exploded Views SCHEMATIC DIAGRAMS AND COMPONENT LAYOUTS Interconnect Schematic For Version C For Version A/B) VHF RF Board Version C Schematic Board Layout VHF RF Board Version B Schematic Board Layout UHF RF Board Version C Schematic Board Layout UHF RF Board Version A/B Schematic Board Layout /00 MHz RF Board Version C Schematic Board Layout MHz RF Board Version A/B Schematic Board Layout Logic Board Version C Schematic Board Layout Logic Board Version A Schematic Board Layout Logic Board Version B Schematic Board Layout Logic Board Version B Schematic Board Layout User Interface Board Version C Schematic Board Layout User Interface Board Version A Schematic Board Layout User Interface Board Version B Schematic Board Layout User Interface Board Version B Schematic Board Layout Programming Cable Schematic Test Cable Schematic OBSOLETE BOARD SCHEMATICS AND LAYOUTS Interconnect Schematic VHF RF Board Version A Schematic Board Layout Logic Board Version A Schematic Board Layout iii

5 TABLE OF CONTENTS TABLE OF CONTENTS (CONT D) 000 Logic Board Version B Schematic Board Layout User Interface Board Version A Schematic Board Layout LIST OF FIGURES LIST OF TABLES Accessories Area Classification Material Classification xx Family Logic and Firmware Versions... LO and First IF Frequencies Hardware Changes Flowchart Programming Setup VHF RF Board Block Diagram (Version C)... UHF RF Board Block Diagram (Version C)... 00/00 MHz RF Board Block Diagram RF Board Block Diagram (Version A/B).... Alignment Setup PCTune Main Screen (Version.0) iv

6 GENERAL INFORMATION SECTION GENERAL INFORMATION. SCOPE OF MANUAL This service manual contains operation, programming, alignment, and service information for the EFJohnson 00 series portable radio. The SL and Ascend (MultiNet) models are similar in appearance and covered by separate manuals as follows: SL Portable Serv Man P.N CD Ascend Portable Serv Man P.N CD The distinguishing characteristics of the 00, SL, and Ascend models are as follows: 00 Series Portable Part No. xxxxx (see Section.) EFJohnson logo under display Black front bezel with black keypad keys SL Series Portable Part No. xxxxx (see Section.) SL label under display Grey front panel bezel with white keypad buttons Ascend Series Portable Part No. xxxx (see Section.) ASCEND label under display Black front panel bezel with black keypad buttons. RADIO DESCRIPTION.. GENERAL The 00series portable transceivers have multiple system programming capability to allow operation in various types of radio systems as described in the information which follows. Models are available for operation in the following frequency ranges. Repeater talkaround, which allows transmitting on the receive frequency, is also available with all bands. VHF: MHz UHF Low: 00 MHz (Federal Users Only) UHF Mid: 00 MHz UHF High: 0 MHz 00/00 MHz: 0 and 00 MHz 00 MHz: 00 MHz (see next section) Power output is user switchable for low and high levels as follows: VHF and watts UHF and watts 00 MHz and. watts 00 MHz and watts.. NEW 00/00 MHZ BAND INFORMATION As described in Section., 00 models are starting to ship with a new design RF board. The 00 MHz models with this new board operate on both the 00 and 00 MHz bands. Earlier models can operate in only the 00 MHz band. Other bands remain the same with this new board. With the 00/00 MHz models, channels can be programmed anywhere in the 00 and 00 MHz bands. For example, Channel can be programed for.000 MHz, Channel for MHz, and so on. The only restriction is that the FCC does not permit receiving in one band and transmitting in the other band on the same channel and vice versa... ANALOG/DIGITAL OPERATION The 00series transceiver uses a digital signal processor (DSP) to provide IF and audio filtering and modulation functions. This allows operation on the various types of channels (see following), backward compatibility with existing equipment, and the ability to operate on various types of radio systems. Narrow Band Analog FM modulation is used with a maximum deviation of. khz. This mode is usually used in systems with a channel spacing of. or khz. Wideband Analog FM modulation is used with a maximum deviation of khz. This mode is usually

7 GENERAL INFORMATION used in systems where the channel spacing is khz or 0 khz. Digital CFM modulation is used. The voice is digitized, filtered, error corrected, optionally encrypted, and then transmitted. Operation in the Project mode is always digital, and operation in the SMARTNET/ SmartZone mode can be either analog or digital. This mode uses a channel spacing of. khz... OPERATING PROTOCOLS Standard 00series transceivers can be programmed for any or all the following operating protocols. The conventional analog protocol is standard and the others are optional and therefore must be enabled by factory programming. Refer to Section for more operation information. APCO Project (digital) conventional APCO Project (digital) trunked SMARTNET /SmartZone analog or digital Analog conventional NOTE: MultiNet operation can be programmed with Ascend models only... FULL AND LIMITED KEYPAD MODELS Both DTMF (key) and limited (key) models are available. The DTMF keypad version includes the 0, *, and # keys for making telephone calls (not currently available), entering unit or group ID numbers, and keypad programming. Both models have the programmable FF option buttons and an Up/Down switch on the front panel. In addition, both models have a pushbutton and rotary switch on the top panel and three pushbutton switches on the side panel that are programmable. A menu mode can also be programmed with both models to select functions that are also selectable by the option buttons. Refer to Section for more information on transceiver operation... SYSTEMS, CHANNELS, AND ZONES A zone and channel are selected to place and receive calls. The following describes the relationship between systems, channels, and zones. Systems A system is a collection of channels or talk groups belonging to the same repeater site. It defines all the parameters and protocol information required to access a site. Up to systems of any type can be programmed. The maximum number of channels assignable to a system is limited to approximately with the channel option (or the available memory space as described in the following information). The channel option is typically standard with all radios. Channels A channel selects an RF channel or talk group as follows: Conventional Analog Mode A channel selects a specific radio channel, Call Guard (CTCSS/DCS) squelch coding, and other parameters unique to that channel. Conventional Project Mode A channel selects a specific radio channel, NAC squelch coding, talk group ID, and other parameters unique to that channel. Trunked Project Mode A channel selects a specific talk group, announcement group, emergency group, and other parameters unique to that talk group. SMARTNET/SmartZone and Project Trunked Operation A channel selects a specific talk group, announcement group, emergency group, and other parameters unique to that talk group. As described in the preceding Systems description, a maximum of up to approximately channels can be programmed. Although it is theoretically possible to program any combination of systems that produces up to total channels, the maximum number is also limited by the available memory. For example, since more memory is required to program a SMARTNET system than a conventional system, the total number of channels decreases as the number of SMARTNET systems increases. The programming software displays a bar graph which shows the amount of available memory space that is used by the current data. Refer to Section for more information.

8 GENERAL INFORMATION Zones A zone is a collection of up to channels of any type. For example, a zone could include conventional channels and SMARTNET channels. One use of zones may be to program the channels used for operation in a specific geographical area. Up to zones can be programmed with standard models and up to can be programmed if the channel option is enabled... PROGRAMMING Transceiver programming is performed using a PCcompatible computer, the EFJohnson 00 Programming Cable, and PCConfigure programming software (see Table ). A link to the PCConfigure programming manual is located in Section... ALIGNMENT Transceiver alignment is performed using EFJohnson PCTune software and test cable, and the same computer used for programming (see preceding section). All adjustments are made electronically using the software (no manual adjustments are required). Refer to Section for alignment and performance testing information.. PRODUCT WARRANTY The warranty statement for this transceiver is available from your product supplier or from the Warranty Department, EFJohnson Company, 0 Corporate Drive, Irving, TX 00. This information may also be requested from the Warranty Department by phone as described in Section.. The Warranty Department may also be contacted for Warranty Service Reports, claim forms, or any other questions concerning warranties or warranty service.. PART NUMBER BREAKDOWN The following is a breakdown of the part number used to identify this transceiver. Some combinations are not available. MFKABCxxD M (Model) 00 series SL series Ascend series F (Frequency Band) VHF ( MHz) UHF (00 MHz) Federal Users Only UHF (00 MHz) UHF (0 MHz) 0000 MHz 00 MHz 00 MHz K (Keypad) Standard, Limited keypad (xx/xx only) Standard, DTMF keypad (xx/xx only) Standard, Limited keypad (xx only) Standard, DTMF keypad (xx only) Intrin Safe, Limited keypad (all models) Intrin Safe, DTMF keypad (all models) A (Antenna) 0 No antenna VHF MHz VHF MHz VHF MHz UHF 00 MHz VHF MHz 00 MHz B (Battery) 0 No battery Ultra high capacity, NiMH Clamshell for alkaline batteries Intrin Safe, ultra high cap NiMH C (Front Housing Color) 0 Black Yellow Orange xx Software enabled features/options These xx letters indicate other operating protocols and options that are enabled by factory programming. Options may include encryption, OTAR, Talk Groups, Digital SMARTNET/ SmartZone, AES encryption, and others. Use the Transfer > Read Options From Radio menu

9 GENERAL INFORMATION function of PCConfigure to determine which protocols and options are enabled in your radio (see Section ). D Encryption Hardware (see Section..) No encryption hardware (software encryp) EFJ SEM module Motorola UCM module. TRANSCEIVER IDENTIFICATION The transceiver identification number is printed on a label that is attached to the chassis. The following information is contained in the identification number: Model From P.N. Revision Letter. ACCESSORIES Manufacture Date Plant The accessories available for this transceiver are listed in Table.. FACTORY CUSTOMER SERVICE Warranty Number xx 0 A A Week No. Last Digit of Year of Year The Customer Service Department of the EFJohnson Company provides customer assistance on technical problems and the availability of local and factory repair facilities. Regular Customer Service hours are :00 a.m. :00 p.m. Central Time, Monday Friday. A technical support subscription service is available or support can be purchased on an asneeded basis. The Customer Service Department can be reached using the following telephone numbers: TollFree: (00) (all except MultiNet) (00) (MultiNet only) FAX: () 0 customerservice@efjohnson.com You can also a person directly if you know their first initial/last name (example: jsmith@efjohnson.com). NOTE: Emergency hour technical support is also available at the 00 and preceding numbers during off hours, holidays, and weekends. When your call is answered at the EFJohnson Company, you will hear a brief message informing you of numbers that can be entered to reach various departments. This number may be entered during or after the message using a tonetype telephone. If you wait until the message is finished and an operator will come on the line to assist you. When you enter some numbers, another number is requested to further categorize the type of information you need. You may also contact the Customer Service Department by mail. Please include all information that may be helpful in solving your problem. The mailing address is as follows: EFJohnson Company Customer Service Department 0 Corporate Drive Irving, TX 00. RETURNS FOR REPAIRS Repair service is normally available through local authorized EFJohnson Land Mobile Radio Service Centers. However, before returning equipment, contact the Customer Service Repair Depot for the correct Ship To address. It is suggested that you call Tech Support as they may be able to suggest a solution to the problem that would make return of the equipment unnecessary. Be sure to fill out a Factory Repair Request Form # for each unit to be repaired, whether it is in or out of warranty. These forms are available free of charge by calling Customer Service (see Section.) or by requesting them when you send a unit in for repair. Clearly describe the difficulty experienced in the space provided and also note any prior physical damage to the equipment. Include this form in the shipping container with each unit. Your telephone number and contact name are important as there are times when the technicians may have specific questions that need to be answered in order to completely identify and repair a problem.

10 GENERAL INFORMATION Table Accessories Accessory Part No. Batteries 00 mah NiMH standard mah NiMH std intrin safe 00* Battery case for AA alkaline 0000 Battery eliminator, V cigar. lighter plug 000 Battery Chargers Kits Charger kit, 0 chgr, 0 PS, US cord 0000 Charger kit, chgr, 0 PS, US cord 000 Charger kit, 0 chgr, 0 PS, Eur cord 0000 Charger kit, chgr, 0 PS, Eur cord 000 unit charger kit, 0 station, four chargers, US cord unit chgr/cond kit, 0 station, four 000 charger/conditioners, US cord unit charger kit as above, Euro cord 0000 unit chgr/cond kit as above, Euro cord 000 Vehicular charger 000 Battery Charger Replacement Parts Singleunit rapid chgr, w/o power supply 000 Singleunit rapid chgr/cond w/o pwr sup 00 Docking station, unit for 0 (0 000 power supply included) Pwr supply, switching 0/0 VAC, V 000.0A, cord required Power supply, switching 0/0 VAC 000.0A for docking stat., cord req d Wall mount kit for unit docking station 00 Power cord, AC / ft US 00 Power cord, AC / ft Euro 00 Antennas MHz helical wideband (red core) MHz helical (yellow core) 0000 MHz helical (black core) 0000 MHz helical (blue core) MHz whip dipole MHz halfwave (red core) MHz /wave (white core) 0000 Carrying Accessories Leather case with belt flap 000 Leather case with belt flap (for use with 00 alkaline battery clamshell) Leather case w/ Dswivel belt loop 00 Table Accessories (Continued) Accessory Part No.. Dswivel belt loop only Dswivel belt loop only 00 Radio Dswiv button for 0/ loops 00 Nylon case with Dswivel belt loop, blk 00 Nylon case with Dswivel belt loop, yel 00 Belt clip, / std spring loaded 00 Belt clip, / long spring loaded 00 Speaker/Microphones and Earphones Spkr/mic, coil cord w/.mm earphone jk 000* Replacement coil cord for above spkr/mic 000 Earphone kit, coil cord w/.mm rt angle 000* plug, for 0 spkr/mic Spkr/mic, public safety, 00 MHz only, 000* 0000 antenna req d Earphone kit, coil cord w/.mm straight 000* plug, for 0 spkr/mic Earphone adapter, w/. mm thrd jack 000* Lightwght headset w/inline PTT for 0 000* wire earphone kit, for 0 adapter 000* wire palm mic kit, for 0 adapter 000* Programming Accessories 00 Programming Kit ( software, cable, CD manual) 00 Programming Cable Cloning Cable 0000 PCConfigure programming software, CD 0 Adapter, DBMDBF 0000 Test Cables and Accessories PCTune radio tuning software 0 PCTune cable w/.mm audio out jack 0000 Patch cord,. mm phone plug to B Tuning Kit ( software, cable, 0 patch cord) SMA F to B F adapter 000 UI to Logic Board Test Cable 000 Encryption Keyloader Accessories SMA (PDA) keyloader 0000 SMA keyloader to 00 radio cable SMA keyloader to 00 radio cable KVL 000 keyloader to 00 radio cable 000 * Accessory is approved for use with intrinsically safe radios.

11 GENERAL INFORMATION When returning equipment for repair, it is also recommended that you use a PO number or some other reference number on your paperwork in case you need to call the repair lab about your unit. These numbers are referenced on the repair order and make it easier and faster to locate your unit in the lab. Return Authorization (RA) numbers are not necessary unless you have been given one by the Field Service Department. RA numbers are required for exchange units or if the Field Service Department wants to be aware of a specific problem. If you have been given an RA number, reference this number on the Factory Repair Request Form sent with the unit. The repair lab will then contact the Field Service Department when the unit arrives. For additional information on factory service, the Depot Service Department can be contacted at the following address: depotrepair@efjohnson.com. REPLACEMENT PARTS Replacement parts can be ordered directly from the Service Parts Department. To order parts by phone, dial the tollfree number as described in Section.. When ordering, please supply the part number and quantity of each part ordered. EFJohnson dealers also need to give their account number. If there is uncertainty about the part number, include the designator (C, for example) and the model number of the equipment the part is from. You may also send your order by mail or FAX. The mailing address is as follows and the FAX number is shown in Section.. EFJohnson Company Service Parts Department 0 Corporate Drive Irving, TX 00.0 INTERNET HOME PAGE The EFJohnson Company has an web site that can be accessed for information on the company about such things as products, systems, and regulations. The address is INTRINSICALLY SAFE INFORMATION.. INTRODUCTION Intrinsically safe 00 transceivers have been approved by the Factory Mutual Research Corporation for operation in certain flammable atmospheres. The specific atmospheres in which operation is approved are shown in Section.. and also on the label on the back cover of the transceiver. WARNING When servicing an intrinsically safe transceiver, these rules must be followed to maintain intrinsic safety: Service can be provided only by the factory or by service centers specifically authorized by the Factory Mutual Research Corporation to service EFJohnson intrinsically safe transceivers. Contact Factory Mutual at the following address for information concerning their auditing procedure. Contact the EFJohnson Customer Service Department as described in Section. if you have questions. Factory Mutual Research Corporation BostonProvidence Turnpike P.O. Box 0 Norwood, Massachusetts 00 Phone: () 00 Replace the battery pack only with Intrinsically Safe Battery Pack, Part No. 00. Do not make any modifications to the circuitry. When replacing a part, use only the exact replacement part listed in the service manual parts list. Do not install any accessory that is not specifically approved for use with intrinsically safe 00 models. Approved accessories are indicated by an asterisk (*) in Table... DEFINITIONS Intrinsically Safe This is a fire rating given to these transceivers by the Factory Mutual Research Corporation. When electrical equipment is given this rating, the equipment is considered incapable of releasing suffi

12 GENERAL INFORMATION cient electrical and thermal energy under normal operation or specified fault conditions per the testing standard to cause ignition of a specific flammable or combustible atmosphere in its most easily ignited concentration. In other words, this transceiver should not cause a fire or explosion when used in certain flammable atmospheres. Fault A defect or electrical breakdown of any component, spacing, or insulation which alone or in combination with other faults may adversely affect the electrical or thermal characteristics of the intrinsically safe circuit (for example, a shorted transistor)... POSSIBLE IGNITION SOURCES When a transceiver is evaluated by Factory Mutual, possible sources of ignition are checked. These sources may be electrical (spark) or thermal (heat). The following could be sources of spark ignition: Discharge of a capacitive circuit by a fault such as a short circuit. Interruption of an inductive circuit. Intermittent making or breaking of a resistive circuit. Hotwire fusing. The following could be sources of thermal ignition: Heating of a smallgauge wire or PC board trace. High surface temperature of components... INTRINSICALLY SAFE AND NONIENDIVE RATINGS This transceiver is rated intrinsically safe for some types of hazards and nonincendive for other types of hazards. An intrinsically safe rating applies to operation in Division areas, and a nonincendive rating applies to operation in Division areas (see next section). The difference between these ratings is as follows: The intrinsically safe rating is a higher rating because more severe conditions must be met. To be approved for this rating, the transceiver must not cause ignition of a particular atmosphere if two of the faults specified in the testing procedure occur. In other words, it must be able to withstand two simultaneous unrelated breakdowns without causing ignition. To receive a nonincendive rating, the transceiver needs to withstand only a single fault without causing ignition of a particular atmosphere... CLASSIFICATION OF HAZARDOUS AREAS AND ATMOSPHERES Introduction This transceiver has been submitted for approval to operate in the following hazardous atmospheres and areas. Contact your sales representative or refer to the label on the back of the transceiver to determine the specific atmospheres and areas for which approval was obtained. Intrinsically Safe Class I, II, and III, Division, Groups C, D, E, F, and G. NOTE: Models with the UCM module (P.N. xxxxxxx) are not approved for Group C operation (see Section.). Nonincendive Class I, Division, Groups A, B, C, and D. Temperature Code TC The meanings of these Class, Division, and Group designations are as follows. Classification of Hazardous Areas (Division) Hazardous areas are classified as Division or as shown in Table. Since a Division area is considered most hazardous, a transceiver approved for a specific Division atmosphere can also be used in the same Division atmosphere. The intrinsically safe rating applies to Division areas and the nonincendive rating applies to Division areas. Atmosphere Classification (Class/Group) For the purposes of testing and approval, various atmospheric mixtures have been grouped on the basis of their hazardous characteristics. Equipment is approved for a class of material and also for the specific group of gas, vapor, or dust in that class. Class I materials include gases and vapors, Class II materials

13 GENERAL INFORMATION include combustible dusts, and Class III materials include ignitable fibers or flyings. The typical hazardous materials in each group and class are shown in Table. Division. SECURE COMMUNICATION NOTE: Refer to Section of the 00 Operating Manual for more information on secure communication. A link to the operating manual is located in Section of this manual. General Table Area Classification Area Class I and II Materials (Gases, Vapors, and Dusts) An area where there is or could be an explosive atmosphere most of the time in normal operation An area where an explosive atmosphere exists only as a result of a fault (something going wrong) Class III Materials (Fibers or Flyings) An area in which easily ignitable fibers or materials producing combustible flyings are handled, manufactured, or used. An area in which easily ignitable fibers are stored or handled. An exception is in process of manufacture. Table Material Classification Typical Hazard Group Class Acetylene A I Hydrogen B I Ethylene, ethyl ether, cyclopropane C I Gasoline, naphtha, butane, propane, D I alcohol, acetone, benzol, natural gas Metal dust including aluminum, magnesium, E II and their alloys Carbon black, coal, or coke dust F II Flour, starch, or grain dusts G II Ignitable fibers/flyings such as rayon or cotton III SecureNet and AES voice encryption can be used to provide secure communication with this transceiver. These protocols digitize the voice and then encrypt it using the DES or AES algorithm and an encryption key. The following types of encryption are available on analog and digital channels: Analog Conventional and SMARTNET/Smart Zone Analog Channels DES DESXL (00 versions with UCM module only; see Table ) Digital Project and SMARTNET/SmartZone Channels DESOFB (Output Feedback) AES (Advanced Encryption Standard). Later 00 models only. Refer to Section of the 00 Operating Manual for more information (a link is located in Section ). FIPS 0 Approved Encryption DESOFB and AES encryption is FIPS 0 approved in 00 models equipped with the SEM or UCM encryption module (see Table ). DES encryption with the SEM on analog channels and DESXL encryption with the UCM is not FIPS approved. OverTheAirRekeying (OTAR) Encryption keys are loaded into the radio by OTAR (OverTheAirRekeying) using a KMF (Key Management Facility) and/or a handheld keyloader such as the EFJohnson SMA (Subscriber Management Assistant) or Motorola KVL 000 Plus with the AES option. The keyloader is connected directly to the radio using an interconnect cable, and it loads DES, DES OFB, and AES keys. Currently, OTAR can be used to load DESOFB keys on Project conventional channels. Future OTAR of AES keys and on Project trunked channels is planned. Refer to Section of the 00 Operating Manual for more OTAR information. A link to this manual is located in Section of this manual.

14 GENERAL INFORMATION RF MODULE CHANGES Version A Version B Version C VHF MHz 0000 Replaced By VHF MHz 0000 Replaced By VHF 0000 MHz UHF 0 MHz 00 MHz 0000 Replaced By UHF 0 MHz 00 MHz 0000 Replaced By UHF 0 MHz MHz UHF 0 MHz 00 MHz 0000 Replaced By UHF 0 MHz 00 MHz 0000 Replaced By UHF 0 MHz MHz UHF 0 MHz 0 MHz 0000 Replaced By UHF 0 MHz 0 MHz 0000 Replaced By UHF 0 MHz MHz 00 MHz 00 MHz 0000 PCTune.0.. can be used to tune these modules. Version A (Software Encryption Only) Logic Board 0000 UI Board 0000 Software Encryption Only DESXL not available Not FIPS approved Version.x.x Firmware Replaced By Version B ( Separate Encryption Module) SEM Logic Board 0000 SEM UI Board MHz 00 MHz 0000 These modules have minor rx front end and other changes. With the VHF module only (Rev Letter "B" or later), PCTune Version..0 or later must be used. With the others, Version.0.. can be used. LOGIC CHANGES DESXL not available FIPS approved Version.x.x Firmware Compatible with Version A and B RF Modules Only Replaced By Discontinued Replaced By 0000 MHz MHz Completely redesigned modules that are compatible with Version C Logic only. PCTune Version.0 or later must be used. Version C ( Separate Encryption Module) SEM Logic Board 0000 SEM UI Board 0000 DESXL not available FIPS approved Version.x.x Firmware Compatible with Version C RF Modules Only UCM Logic Board 0000 UCM UI Board 0000 DESXL available FIPS approved Version.x.x Firmware Compatible with Version A and B RF Modules Only Discontinued 00 Production Start Figure Hardware Changes Flowchart. RADIO HARDWARE CHANGES NOTE: Version A/B/C references in the following information are for descriptive purposes in this manual only and do not correspond to any radio revision letters or letters on the boards... RF MODULE CHANGES As shown in Figure, there have been three significant changes to the RF module used in 00 series radios: Version A This is the original module version that was used until approximately late 00. All versions of PCTune can be used to tune radios with these modules. The schematic diagrams and board layout for this VHF board are located in the Unrev_Bd folder and the other boards are located in Section. Version B The changeover to this version occurred starting in late 00. This change was made because of part obsolescence. Significant changes occurred to only the VHF board, so this is the only board with revised schematics and layouts in this manual. With the UHF and 00 MHz boards, only minor layout and value changes occurred. The Version B boards are being replaced by the following Version C boards as they become available. NOTE: PCTune, Version.0.0 or later must be used to tune VHF radios with this board (see following). PCTune Version.0.0 or later must be used to adjust radios with the Version B VHF board because of changes made in the front end. The earlier version (.0..) can still be used to tune all other Version B and all Version A boards.

15 GENERAL INFORMATION The Revision Letter in the radio identification number (see Section.) can be used to determine if a VHF radio has this new Version B board. Radios with a Revision Letter of B or later have the new board and PCTune.0.0 or later must be used. Version C These boards are a completely new design. Highlights of this board version are as follows: Because of different interface requirements, the new Version C logic and UI boards described in the next section must be used. This logic is PowerPCbased, similar to Version A and B. A new version of the PCTune software (.0 or later) is required to tune radios with these boards. The new 00 MHz version of this board operates on both 00 and 00 MHz channels instead of only 00 MHz channels like the A and B versions. Therefore, radios with the Version C board can operate on channels from 0 MHz, while radios with the earlier Version A and B boards can operate only on channels from 00 MHz. Radios with this new 00/00 MHz RF board have a as the F character of the radio part number (see Section.), while radios with the older A and B versions have an for this character... LOGIC AND UI BOARD CHANGES As shown in Figure and Table, there have been three significant changes to the control logic used in xx series radios. More information on these changes follows. NOTE: The firmware version number (.x/.x/.x) is briefly displayed when radio power is turned on. Version A This version of logic and UI boards provides software generated encryption (Version in Table ). DESXL and FIPS 0 approval is not available with these models. Version B This version began shipping in mid 00 to provide FIPS 0 approved and DESXL encryption. SEM and UCM versions of these boards are available (Versions and in Table ). These boards have separate encryption modules to provide encryption instead of doing it through software. The SEM and UCM versions are functionally the same except only the UCM version provides DESXL encryption. Normally, the SEM version is used unless DESXL encryption is required. Version C This version of the logic and UI boards is a new design that is required to interface with the new Version C RF module. Only a SEM version will be offered (similar to Version in Table ). This version of boards has more Flash and RAM memory to allow additional features to be added if necessary. This logic version uses Version.x.x firmware. 0

16 GENERAL INFORMATION Table xx Family Logic and Firmware Versions Logic/Radio Version [] Application (Firmware) Code Base Analog Channel Encryption Digital Channel Encryption DES DESXL DESOFB AES Version (No Module/Software Encryption).xx Yes No Yes Yes Current standard version which uses the 0 Logic board and 0 UI Board. Not FIPS approved. Version (uses EFJ SEM module).xx Yes No Yes Yes Current version which has the EFJohnson SEM (Subscriber Encryption Module) on the logic board. This version uses the 0 Logic and 0 UI boards. All radios include the SEM, and the desired encryption options (if any) are enabled by factory programming. FIPS approved. Version (uses Motorola UCM module).xx Yes Yes Yes Yes Current version which has the Motorola UCM (Universal Crypto Module) on the logic board. This version uses the 0 Logic and 0 UI boards, and is ordered when DESXL encryption is required. FIPS approved. Version (uses EFJ SEM module) New version designed for use with the new Version C RF modules described in Section... It uses the same EFJohnson SEM (Subscriber Encryption Module) as Version boards above. This version uses 000 Logic and 000 UI boards. All radios include the SEM, and the desired encryption options (if any) are enabled by factory programming. FIPS approved..xx Yes No Yes Yes [] The version number of Versions is also indicated by the th digit of the radio part number (xxxxxxxv).

17 GENERAL INFORMATION 00 PORTABLE SPECIFICATIONS The following are general specifications intended for use in testing and servicing this transceiver. For current advertised specifications, refer to the specification sheet available from your sales representative. Values are typical and are subject to change without notice. GENERAL Frequency Range Available Operating Modes Channels/Talk Groups Transmit/Receive Separation Channel Spacing Maximum Deviation Frequency Stability VHF: MHz UHF: 00 MHz, 00 MHz, 0 MHz 00/00 MHz: 0 MHz, 00 MHz: 00 MHz (see Section..) Conventional analog, Project conv. and trunked, SMARTNET/SmartZone analog and digital (see Section..) Up to (dependent on available memory) Any frequency within the range VHF:.,, and 0 khz UHF:. and khz 00/00 MHz:. and khz khz analog khz. khz analog. khz. khz analog SPAC.0 khz VHF/UHF.0 PPM, 00/00 MHz. PPM ( to 0 F or 0 to 0 C). H x. W x. D (.0 cm x. cm x. cm) Dimensions (w/o antenna) Weight (w/std battery) oz. ( g) Supply Voltage. volts DC nominal Battery Life hours typical w/std 00 mah battery Current Drain (maximum Standby 00/0 ma (with Ver A B/Ver C RF board, see Section..) w/o backlight, w/backlight Receive (rated audio out) 00/0 ma add 00 ma) Low Tx Power./. A High Tx Power./. A RECEIVER Sensitivity Selectivity Spurious and Image Rejection Intermodulation Maximum Frequency Spread Audio Power Output Audio Distortion 0. µv (analog mode db SINAD), 0. µv (digital mode % BER) db db (VHF/UHF), 0 db (00/00 MHz) db (VHF), db (UHF), db (00/00 MHz) Any spread within the range 00 mw Less than % at khz TRANSMITTER RF Power Output VHF: W (high), W (low) UHF: W (high), W (low) 00 MHz:.W (high/ta), W (low) 00 MHz: W (high), W (low),. TA Spurious and Harmonic Emissions 0 db (VHF/UHF), db (00/00 MHz) FM Hum and Noise db at khz bandwidth Audio Modulation K0FE, K0FE (all), K0FE (VHF/UHF), K0FE (00/00 MHz) Audio Distortion Less than % at khz Maximum Frequency Spread Any spread within the band

18 BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION SECTION BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION Battery Release Button Figure Battery Removal. BATTERY INFORMATION.. BATTERY REMOVAL/INSTALLATION To remove the battery from the radio for recharging or replacement, press the release button (see Figure ) and then rotate it upward to the approximate point shown and remove it from the radio... BATTERY CHARGING NOTE: Do not charge the battery with radio power on (see following). The battery can be charged separately or while attached to the radio. When it is charged while attached to the radio, radio power should be turned off. If it is not, the battery begins slowly discharging when the trickle charge mode is entered. The trickle mode is indicated by a green Ready indication, and it is entered automatically when the battery is nearly fully charged. Gradual discharging occurs in the trickle mode because the charge current of approximately 0 ma is less than the radio standby current of 00 ma. CAUTION: Do not transmit in close proximity to the charger base (see following). Do not expose the charger base to high level RF signals while a battery is being charged because this may cause a charger fuse to blow (especially in the UHF range). Radios programmed for SMARTNET/ SmartZone operation, for example, may affiliate while in the charger which causes them to key automatically. Therefore, do not leave radio power on while charging as described above... PREVENTING LOSS OF ERYPTION KEYS NOTE: Later models (manufactured in 00 and later) have reduced storage time as follows. If Infinite Key Retention is not programmed, the transceiver must be connected to a constant power source to preserve the encryption keys in memory. Storage capacitors maintain the supply voltage (and these keys) for approximately 0 seconds to allow the battery to be changed. Therefore, when changing the battery of a transceiver containing keys, make sure to reattach another battery within 0 seconds. Models with Flash code..0 or later can be programmed for Infinite Key Retention. The keys are then stored in memory and are not lost, even if power is disconnected for an extended period.

19 BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION.. BATTERY CARE WARNING: Do not incinerate a battery pack because it may explode. Also, do not short circuit the terminals because the battery pack and the object causing the short may become very hot. Do not disassemble or modify a battery pack. Proper battery care enhances the useful life of the battery. The battery should be recharged as soon a practical after the low battery indication appears (see Section ). Follow the charging instructions in the manual included with the charger. When the battery fails to hold a charge or provides only a very short operating time, it must be replaced with a new unit. A fully charged battery provides approximately hours of service before recharging is required. This time assumes that % of the time is spent transmitting, % in the receive unsquelched mode, and 0% in the receive squelched mode. The operating time may be less if more time is spent in the transmit or unsquelched modes, or if the battery is not fully charged or its capacity has deteriorated. Be sure to dispose of the nickel metalhydride (NiMH) battery pack in accordance with local waste regulations. Figure Belt Clip Installation. BELT CLIP INSTALLATION Remove the battery and slide the belt clip into the slot on the battery as shown in Figure. To remove the clip, simply slide it out. It is held in place by the chassis when the battery is installed on the radio.

20 BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION Install Lock Screw Here Accessory Connector Latch Hook Figure Accessory Installation. ACCESSORY INSTALLATION To connect an accessory such as a speakermicrophone to the transceiver, refer to Figure and proceed as follows:. Remove the dust cover over the accessory jack on the side of the transceiver.. Insert the hook of the accessory connector into the slot on the side of the transceiver.. Hold the latch open, press the connector against the transceiver, and then release the latch to lock the connector in place.. Install the included locking screw in the latch tab in the location shown. Option Select Lines Opt Sel (pin ) and Opt Sel (pin ) of the UDC (accessory) connector indicate to the control logic when an accessory is connected and what accessory is installed. These lines function as follows: Opt Sel and High (.V) This is the normal operating condition in which no accessory is connected. Both lines are pulled high (.V) by internal pullup resistors. Opt Sel Low A speakermicrophone or some other accessory is connected. Opt Sel then functions as an external PTT line (low = PTT), and the radio PTT switch is also functional. The internal speaker and microphone are disabled. Opt Sel High, Opt Sel Low The encryption keyloader is connected.

21 BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION. TRANSCEIVER DISASSEMBLY.. SEPARATING FRONT COVER AND CHASSIS. Remove the antenna.. Insert a small flatblade screwdriver or similar tool between the plastic front cover and metal chassis as shown below. Carefully lift the chassis out of the cover with the screwdriver blade. Raise it to approximately the point shown in the next illustration. Front Cover Metal Chassis. Slide the chassis out of the top part of the front cover. NOTE: Before reassembling the front cover and chassis, make sure the UDC (accessory) connector flex circuit is flat against the side of the front cover. If it is not, the RF board shield clip may catch and damage it.. When reassembling, make sure the perimeter gasket is in place, and then use the screwdriver blade again as a guide to prevent damage to the bottom part of the gasket as the chassis slides back in place. Firmly press the chassis and the cover together until they snap in place.

22 BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION.. REMOVING RF AND LOGIC BOARDS FROM CHASSIS. Separate the front cover and chassis as described in the preceding section. The RF and logic boards are located inside the metal chassis as shown below. RF Board Logic Board. Remove the shields over the RF and logic boards. These shields insert in slots on one side of the chassis and then clip to the other side of the chassis. These shields also hold the boards in place.. Unplug the antenna cable from the RF board using a plier or similar tool at the location shown below. Unlock the logic board flex circuit by sliding the tab on the connector outward. The RF and logic boards can now be removed. Unplug Ant Jack Cable RF Module Unlock Flex Circuit. When handling these boards, minimize bending of the flex circuit to prevent it from being damaged. Before replacing the RF board, make sure there is adequate heat sink compound on the pad under the RF module.

23 BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION.. REMOVING UI (USER INTERFACE) BOARD. Separate the front cover and chassis as described in Section... The UI board is located inside the front cover as shown below. Microphone UI Board Unsolder Wires Unlock Flex Circuits Remove Screws. Unlock the three flex circuits shown above by sliding the tab on each connector outward. Carefully slide the flex circuits out of the connectors, taking care to minimize bending which could crack the traces.. Remove the two screws shown above. If required, also unsolder the two speaker wires.. Carefully lift the bottom end of the UI board upward (guide the microphone out of its cavity). Then slide the UI board out of the radio.. When reinstalling the UI board, the display assembly on the bottom of the board must slide into the area above the keypad (see following illustration). If the UI board does not lie flat against the keypad after it is installed, the display is probably hanging up on the keypad. Do not force it in place. Reorient the keypad and UI board as required until the display slides into place. Also make sure that the optic fiber bundle slides under the boss on the switch assembly, and the microphone is properly positioned back in its cavity. Display Area Keypad

24 BATTERY, ACCESSORY, AND DISASSEMBLY INFORMATION.. REMOVING SWITCH ASSEMBLY. Separate the front cover and chassis as described in Section... Then remove the UI board as described in the preceding section.. Pull the rubber knobs and plastic channel number ring off the shafts.. To remove the position indicator ring under the channel knob, turn the channel switch so that the flat part of the shaft is toward one of the tangs (see below). Then insert a tweezers or similar tool under both tangs and push it inward to release the tangs from the groove in the shaft.. Remove the spanner nut on each shaft and slide the switch assembly out of the cover.

25 OPERATION SECTION OPERATION. GENERAL The operation of the 00 transceiver is included in a separate manual that is included on the CDROM with this manual.

26 TRANSCEIVER PROGRAMMING SECTION TRANSCEIVER PROGRAMMING Connect To Serial Port 00 Programming Cable Part No Figure Programming Setup. PROGRAMMING SETUP The following items are required to program the transceiver. The part numbers of this equipment are shown in Table in Section. The programming setup is shown above. Computer running Windows software 00 Programming Cable, Part No PCConfigure programming software, Part No. 0. NOTE: The 0 cable, software, and a CD manual are included in the 00 Series Programming Kit, Part No COMPUTER DESCRIPTION The computer used to run this program should meet the following minimum requirements: The computer used to run this program should meet the following minimum requirements: Windows //NT/000 Pentium processor or equivalent At least MB of RAM A hard disk drive with at least MB of free space A CDROM drive An available serial port. USING THE PCCONFIGURE SOFTWARE The PCConfigure software is described in a separate manual included on the CDROM with the service manual. Tone (CTCSS) and digital (DCS) Call Guard tones and 00 MHz channel frequencies are located in the back of the above manual. NOTE: The latest programming manual is also included on the PCConfigure CDROM.

27 TRANSCEIVER PROGRAMMING. CLONING PROCEDURE The Clone feature allows one radio to be used to program another with identical information. The PCConfigure programming software is not required. Only conventional analog and Project zones can be programmed with this feature. SMARTNET/Smart Zone and Project trunked information is not transferred. The Clone option switch must be programmed on the master radio. With the latest 00 versions, both wireless and wired cloning are available. For more information on cloning one radio with another, refer to Section of the PCConfigure Manual included on the CDROM with this service manual. To open this manual, click the link on the preceding page or go to the PCConfigure directory on the CD and open the file Manual.pdf.

28 CIRCUIT DESCRIPTION SECTION CIRCUIT DESCRIPTION. GENERAL OVERVIEW.. INTRODUCTION The EFJohnson 00 series digital portable radio uses a PowerPC based controller and a Digital Signal Processor (DSP) to provide the following modes of operation: Narrowband Analog FM modulation with a maximum deviation of. khz. This mode is usually used in systems where the channel spacing is. khz. Call Guard (CTCSS or DCS) subaudible squelch signaling can be used in this mode. Wideband Analog FM modulation with a maximum deviation of khz. This mode is usually used in systems where the channel spacing is khz or 0 khz. Call Guard (CTCSS or DCS) subaudible squelch signaling can be used in this mode. Project Digital The voice is digitized, error corrected, optionally encrypted and transmitted using CFM modulation according to the Project standard. This mode can be used in channel spacings of. khz. The DSP processes the received signals and generates the appropriate output signals. The microcontroller controls the hardware and provides an interface between hardware and DSP. PC Boards This radio contains the following PC boards: RF Board Logic Board User Interface (UI) Board Five flex circuits that provide interconnection with the RF board, display, top panel controls, side buttons, and UDC (accessory) connector. The User Interface Board provides the input/ output interface for the user. It contains the PowerPC processor which is the main controller for the transceiver. It also contains the keypad and has inputs for the various buttons and switches. It also controls the display and performs all RS communications between the radio and remote computer stations for the purposes of radio programming, tuning, encryption key loading and software downloading. The Logic Board contains the digital audio processing circuitry which includes the CODEC (or ADSIC with early versions) and DSP devices. NOTE: The next two sections (.. and..) describe operation with the revised logic (Version C in Section.). Generally, the Digital IF chip on the revised RF board replaces the ABACUS chip on the early version, and the CODEC on the revised logic board replaces the ADSIC chip on the early version... ANALOG MODE Receive Mode The signal is routed from the antenna connector to the RF Board where it is filtered, amplified, and mixed with the first local oscillator frequency generated by the synthesizer. The resulting IF signal is also filtered and amplified and sent to the AD digital IF chip. The signal is then mixed with the second local oscillator frequency to create a second IF signal. The second IF signal is then sampled and downconverted to baseband. The baseband signal is then decimated to a lower sample rate that is selectable at 0 khz. This signal is then routed via a serial interface from the IF chip to the DSP on the logic board. On the logic board the DSP digitally filters the input signal and performs frequency discrimination to obtain the message signal. The DSP first performs a carrier detection squelch function on the radio. If a signal is determined to be present, the audio portion of the signal is resampled and then filtered appropriately. The filtered signal is then routed back to a D/A in the CODEC to produce an analog signal for output to the audio power amplifier and then the speaker. Any detected signaling information is decoded and the resulting information is sent to the microcontroller.

29 CIRCUIT DESCRIPTION VHF RF BOARD (VERSION C) Transmit Mode The signal from the microphone is amplified and then routed to the CODEC chip where it is first digitized and then sent to the DSP. The DSP performs the required filtering, adds the desired signaling, converts the sample rate and then sends the resulting signal back to a D/A in the CODEC to produce the analog modulation signals for the VCOs. The modulated VCO signal is then sent to the RF power amplifier and transmitted. This bit stream in then encoded, two bits at a time, into a digital level corresponding to one of the four allowable frequency deviations. This produces bit symbols with a rate of 00 Hz. The symbols are resampled to a rate of khz and filtered to comply with channel bandwidth requirements. The filtered signal is then sent to a D/A in the CODEC to produce the analog modulation signal for the VCO. The modulated VCO signal is then mixed up to the final transmit frequency and then sent to the RF PA for transmission... PROJECT DIGITAL MODE Introduction In Project Digital Mode, the carrier is modulated with four discrete deviation levels. These levels are ± 00 Hz and ± 00 Hz. Digitized voice is created using an IMBE vocoder. Receive Mode The signal is processed in the same way as an analog mode transmission until after the squelch function is performed. If a signal is detected to be present, the DSP resamples the signal from 0 khz to khz. This is done so that the sample rate is an integer multiple (x) of the data rate of the digital modulation which is 00 symbols/sec (00 bits/sec). The resampled signal is then processed by a demodulator routine to extract the digital information. The resulting bit stream (00 bps) is sent to a routine that performs unframing, errorcorrection, and voice decoding. The result of these operations is a reconstructed voice signal sampled at khz. The sampled voice signal is sent to a D/A in the CODEC to produce an analog signal for output to the audio power amplifier and speaker. Transmit Mode The microphone signal is processed as in the analog mode until it reaches the DSP. At this point the audio signal is processed by a voice encoding routine to digitize the information. The resulting samples are then converted to a bit stream that is placed into the proper framing structure and error protected. The resulting bit stream has a bit rate of 00 Hz.. VHF RF BOARD (Version C) NOTE: The following describes the new revised Version C RF board described in Section... The RF Board is not field serviceable. It must be replaced as a unit with a new board... RECEIVER Front End Bandpass Filter A harmonic filter is followed by a PIN diode transmit/receive switch. Following this switch a fixed tuned bandpass filter is used at the frontend of the receiver. This filter provides first image rejection with minimal loss in order to provide the desired receiver sensitivity. Following the filter a variable attenuator is used to increase the dynamic range of the receiver when receiving high level signals. Front End LNA and Bypass Switching The Low Noise Amplifier (LNA) is critical in determining the overall noise figure of the receiver chain. An MGA amplifier (U) provides optimum noise figure, gain, intercept point, and power consumption. PostLNA Bandpass Filters An additional bandpass filter is located after the LNA. This filter is identical to the front end filter previously described and provides additional image rejection.

30 CIRCUIT DESCRIPTION VHF RF BOARD (VERSION C) RF / Logic Interface BPF LNA BPF R L I. MHz SPI RFOut Kbit SPI EEPROM SPI SPI Clk SPI MOSI khz khz Receiver Back End SPI MISO SPI Addr MHz Antenna LO BPF 00 MHz ch DAC SPI SPI Addr SPI Addr SPI Addr Harmonic Filter C T/R Switch C Switch D0D VCO PD SPI RF RX PLL REF. MHz VCXO RF Out RF Clk RF Data RF Frame Sync Lock 0 Enable 0 Lock Detect PD Reference RF PLL REF SPI ntxena ntxnap TxMod PA DRIVER MHz D0D VCO L R I. MHz. SPI MHz RF TX PLL VCXO REF BPF PD High Frequency Modulation Low Frequency Modulation TxMod Temp Unswitc h Batt.V.V Power Control Figure VHF RF Board Block Diagram (Version C) Mixer and LO Filter A doublebalanced, lowlevel ADEX0L mixer (MX) with a LO drive level of dbm is used for the first conversion. This mixer provides a good dynamic range with a db lower LO drive than the more traditional dbm drive mixers. This reduces power consumption and also the conducted and radiated local oscillator leakage from the receiver. High side injection is used to provide optimum spurious performance. A LO filter prior to the mixer LO port reduces wideband noise from the LO synthesizer which improves receiver sensitivity. IF Filter and Amplifier A twopole. MHz crystal filter (U) is used to provide the desired level of adjacent channel rejection while providing minimal amplitude and phase distortion within a KHz bandwidth. Shields are installed around the crystal filter to provide sufficient isolation to meet the second image response specifications and to minimize noise pickup by the impedancematching inductors (L, L, L, L and L.) A transistor IF amplifier (Q) and supporting circuitry is required to boost the signal strength, thereby reducing the overall noise figure. The noise figure, signal gain, intercept point, and power consumption are optimized in this design. An additional twopole. MHz crystal filter (U) is used to increase the adjacent channel rejection. An LC circuit provides the required impedance matching between the output of the IF filter and the input of the backend chip (U.) Back End IC An Analog Devices AD IF Digitizing Subsystem IC (U) provides a variety of functions for the receiver as follows: Second Local Oscillator A varactortuned transistor (Q) oscillator is phaselocked to a fixed frequency of. MHz for converting the first

31 CIRCUIT DESCRIPTION VHF RF BOARD (VERSION C) IF of. MHz to a second IF frequency of. MHz. Phase Locked Loop circuitry inside of the AD operates with a phasedetector frequency of khz. Second Conversion Mixer and Filtering A mixer inside the AD converts from the first IF of. MHz to the second IF of. MHz. External filters (L and L0) provide IF bandpass filtering. Additional filtering is provided by the inherent operation of the sigmadelta analog/digital converters. Gain Control This device provides up to db of AGC range via a combination of analog and digital controls. Additionally, there is a db attenuator in the front end. The optimum settings are controlled by the host microprocessor. Analog/Digital Conversion and Processing Sigmadelta converters provide I and Q sampling directly from the second IF frequency. The resulting digital words are first filtered by internal programmable FIR filters and then clocked out of the AD via a serial data bus using a programmable data rate... SYNTHESIZER The following three phase locked loops are used in the VHF radio module to provide the required overall functionality and performance levels. Receive PLL The receive PLL provides a signal that is in the frequency range of 00 to MHz. In receive mode it is programmed for a frequency that is. MHz above the receive frequency. In transmit mode it is programmed for a frequency that is equal to. MHz minus the desired transmit frequency. Transmit PLL The transmit PLL phase locks a transmit oscillator that is operating at an output frequency of to MHz. The RF signal into the PLL chip is created by mixing the transmit frequency with the receive PLL frequency to generate a mix frequency of. MHz. This provides low frequency modulation of the VCO by modulating the transmit PLL reference frequency. Reference PLL The reference PLL phase locks the receive PLL reference oscillator to the transmit PLL reference oscillator with a loop bandwidth of less than 0 Hz. This PLL ensures that the center frequency of both reference oscillators are the same. It also limits the modulation of the receive PLL reference oscillator by the low frequency modulation applied to the transmit PLL reference oscillator. PLL IC Two CX0 sigmadelta modulated PLL chips (U & U) are used for the PLLs described above. This PLL chip provides good phase noise capabilities to reduce adjacent channel interference and quick switching between the receive and transmit modes. Reference Oscillators One. MHz oscillator (Y) is used as the frequency reference for the receive PLL and also for the receiver backend IC. The other. MHz oscillator (Y) is used as the frequency reference to the transmit PLL. The center frequency of this oscillator is corrected using a DC tuning voltage from the digital board in the receive mode and it is modulated with voice or data in the transmit mode. The receive PLL reference oscillator is phase locked to the transmit PLL reference oscillator as discussed above. Analog Switches and PLL Loop Filters An analog switch (U) provides faster switching of signals during channel changes by varying the time constant of the PLL loop filter... TRANSMITTER Modulation A dualport modulation scheme is used to provide the DC coupling of the signal required for data modulation applications. In this scheme, modulation applied to the transmit PLL frequency reference provides lowfrequency modulation, and modulation

32 CIRCUIT DESCRIPTION applied to the transmit PLL transmit VCO (U) provides highfrequency modulation. Signals for both modulation ports are provided by DACs on the digital board. Power Amplifier The power amplifier (U) is a Mitsubishi RA0MM module. This PA module provides the desired RF power output level and is stable over a wide range of VSWR conditions. The PA is driven by a SGA driver (U0) that typically provides dbm output power. The PA is turned on and off by switching the power to this driver via transistor D0. ALC To maintain the specified transmitter output power level, Automatic Level Control (ALC) is used to control the drive level to the PA. The detected forward power is compared to a reference level provided by the digital board via op amp UA. The resulting error voltage is applied to a power level control port of the power amplifier module. Transmitter on/off splatter filtering is provided by an RC network (R, R, C and C.) T/R Switching and Harmonic Filter The output of the power amplifier is applied to the transmit/receive RF PIN switch (D/D). This is a high dynamicrange switch that is capable of passing the desired transmit power with minimal compression. Any harmonics generated by the PA module and the RF T/R switch are filtered by a harmonic filter that is located between the RF T/R switch and the antenna jack.. UHF RF BOARD (VERSION C) NOTE: The following describes the new revised Version C RF board described in Section... The RF Board is not field serviceable. It must be replaced as a unit with a new board... RECEIVER VHF RF BOARD (VERSION C) Front End Bandpass Filter A harmonic filter is followed by a PIN diode transmit/receive switch. Following the switch, two UHF RF BOARD (VERSION C) fixed tuned bandpass filters are used in the frontend of the receiver. Depending on the desired receive band, the appropriate filter is selected using RF switches (U/U). This filter provides firstimage rejection with minimal loss in order to provide the desired level of receiver sensitivity. A variable attenuator, which follows the filter, increases the dynamic range of the receiver when receiving highlevel signals. Front End LNA and Bypass Switching The Low Noise Amplifier (LNA) is critical in determining the overall noise figure of the receiver chain. An MGA amplifier (U) provides optimum noise figure, gain, intercept point, and power consumption. PostLNA Bandpass Filters Additional bandpass filters are positioned after the LNA. These filters are identical to the frontend filters previously described. RF switches U and U0 are used to select between the two bands. These filters provide additional image rejection. Mixer and LO Filter A doublebalanced, lowlevel ADEX0L mixer (MX) with a LO drive level of dbm is used for the first conversion. This mixer provides good dynamic range with a db lower LO drive than the more traditional dbm drive mixers. This reduces power consumption and also the conducted and radiated local oscillator leakage from the receiver. For the low band UHF version, a highside mix is used for the 0 MHz receive band and a lowside mix is used for the 0 MHz receive band. For the high band UHF version, a highside mix is used for the 0 MHz receive band and a lowside mix is used for the 0 MHz receive band. This band plan reduces the tuning range requirements for the VCOs. A LO filter is used prior to LO port of the mixer to reduce the impact of wideband noise from the LO synthesizer on the receiver sensitivity. IF Filter and Amplifier A twopole. MHz crystal filter (U) is used to provide the desired level of adjacent channel

33 CIRCUIT DESCRIPTION UHF RF BOARD (VERSION C) C Bandpass Filters 0 MHz (0 MHz) Switch 0 MHz (0 MHz) AT Switch Var Atten C C LNA MGA LNA Bypass Switch C C Switch Bandpass Filters 0 MHz (0 MHz) 0 MHz (0 MHz) Switch C MIXER ADEX0L R L I LO BPF. MHz KHz BW IF Amp MMBR. MHz KHz BW Receiver Back End Fif =.MHz AD RF Out SPI SPI SPI Addr RF / Logic Interface SPI Clk SPI MOSI SPI MISO SPI Addr SPI Addr. MHz SPI Addr Antenna Jack Harmonic Filter C D0 T/R PIN Switch Switch C RF Switch C VCO 0 MHz ( 0 MHz) VCO 0 MHz ( MHz) RX Band Select VCO Select RX LNA Bypass Kbit EEPROM ch bit DAC SPI SPI RF Out RF Clk RF Data RF Frame Sync Lock 0 Enable 0 Lock Detect TX Pwr Control ntxena. MHz ntxnap PLL SPI Low Frequency Modulation TxMod High Frequency Modulation TxMod PA Mitsubishi RA0M DRIVER Sirenza SGA Temp Unswitched Battery.V.V Power Control TX Pwr Control Figure UHF RF Board Block Diagram (Version C) rejection while providing minimal amplitude and phase distortion within a KHz bandwidth. Shields installed around the crystal filter provide sufficient isolation to meet the second image response specifications and minimize noise pickup by the impedancematching inductors (L, L, L, L and L.) A transistor IF amplifier (Q and supporting circuitry) is required to boost the signal strength, thereby reducing the overall noise figure. The noise figure, signal gain, intercept point, and power consumption are optimized in this design. An additional twopole. MHz crystal filter (U) is used to increase the adjacent channel rejection. An LC circuit provides the required impedance matching between the output of the IF filter and the input of the backend chip (U.) Back End IC An Analog Devices AD IF Digitizing Subsystem IC (U) provides a variety of functions for the receiver as follows: Second Local Oscillator A varactortuned transistor (Q) oscillator is phaselocked to a fixed frequency of. MHz for converting the first IF of. MHz to a second IF frequency of. MHz. Phase Locked Loop circuitry inside of the AD operates with a phasedetector frequency of khz. Second Conversion Mixer and Filtering A mixer inside the AD converts from the first IF of. MHz to the second IF of. MHz. External filters (L and L0) provide IF bandpass filtering. Additional filtering is provided by the inherent operation of the sigmadelta analog/digital converters. Gain Control This device provides up to db of AGC range via a combination of analog and digital controls. Additionally, there is a db attenuator in the front end. The optimum settings are controlled by the host microprocessor.

34 CIRCUIT DESCRIPTION UHF RF BOARD (VERSION C) Analog / Digital Conversion and Processing Sigmadelta converters provide I and Q sampling directly from the second IF frequency. The resulting digital words are first filtered by internal programmable FIR filters and then clocked out of the AD via a serial data bus using a programmable data rate... SYNTHESIZER PLL IC A CX0 sigmadelta modulated PLL (U) forms the basis of the main synthesizer that is used for both receive and transmit modes. This PLL chip provides good phase noise capabilities to reduce adjacent channel interference and quick switching between the receive and transmit modes. In receive mode the PLL is programmed for a local oscillator frequency that is. MHz away from the receive frequency. In transmit mode the PLL is programmed directly for the transmit frequency. Reference Oscillator A. MHz oscillator (Y) is used as the frequency reference to the synthesizer and also to the receiver backend IC. The center frequency of this oscillator is corrected using a DC tuning voltage from the digital board during receive and voice and data modulation during transmit. Analog Switches and PLL Loop Filters An analog switch (U) provides quicker switching of signals during channel changes by varying the time constant of the PLL loop filter. VCOs Two different VCOs minimize the tuning range of the VCOs in order to meet phase noise specifications. Both VCO's (U and U) are used for transmit and receive modes. Their combined tuning range covers the entire transmit and receive frequency bands. Transmit modulation is provided to each oscillator's modulation port from the digital board. A RF buffer amplifier (U) provides the required level of drive for the receiver mixer's local oscillator signal as discussed above... TRANSMITTER Modulation A dualport modulation scheme is used in order to provide DC coupling of the signal required for data modulation applications. Modulation applied to the PLL's frequency reference provides lowfrequency modulation, whereas modulation applied to the PLL's transmit VCO's (U and U) provide highfrequency modulation. Signals for both modulation ports are provided from DACs on the digital board. Power Amplifier The power amplifier (U) is a Mitsubishi RA0M0M0 module for the low band version and a Mitsubishi RA0MM0 module for the high band version. The PA module provides the desired RF power output level and is stable over a wide range of VSWR conditions. The PA is driven by a SGA driver (U0) that typically provides dbm output power. The PA is turned on and off by switching the power to this driver via transistor D0. ALC To maintain the specified Transmitter output power level, Automatic Level Control (ALC) is provided to control the drive level to the PA. The detected forward power is compared to a reference level provided by the digital board via op amp UA. The resulting error voltage is applied to a power level control port of the power amplifier module. Transmitter on/off splatter filtering is provided by an RC network (R, R0, C and C.) T/R Switching and Harmonic Filter The output of the power amplifier is applied to the transmit/receive RF PIN switch (D & D.) This is a high dynamicrange switch that is capable of passing the desired transmit power with minimal compression. Any harmonics generated by the PA module and the RF T/R switch are filtered by a harmonic filter that is between the RF T/R switch and the antenna jack.

35 CIRCUIT DESCRIPTION 00/00 MHz RF BOARD (VERSION C) RF / Logic Interface VaracterTuned Bandpass Filter U Switch C LNA RF U Switch U C LNA Bypass U Switch C Bandpass Filters MHz 0 MHz U Switch C MX MIXER ADEX0L R L I LO BPF U. MHz KHz BW IF Amp MMBR Q Receiver Back End (Digital IF) Fif =.MHz U RF Out AD SPI SPI SPI Addr SPI Clk SPI MOSI SPI MISO SPI Addr SPI Addr. MHz SPI Addr Antenna Jack Harmonic Filter U C D0 T/R Switch U Switch C RX VCO MHz U RX VCO 0 MHz U RX Band Select RX Filter Tuning RX LO Filter Tuning RX LNA Bypass U Kbit EEPROM U ch bit DAC SPI SPI RF Out RF Clk RF Data RF Frame Sync Lock 0 Enable 0 Lock Detect TX Pwr Control ntxena U Switch C U PLL SPI Y. MHz TCXO Low Frequency Modulation High Frequency Modulation ntxnap TxMod TxMod PA Mitsubishi RA0M DRIVER Sirenza SGA TX VCO 0 MHz Temp U0 U Unsw Batt U.V.V Power Control Figure 00/00 MHz RF Board Block Diagram. 00/00 MHz RF BOARD (VERSION C) NOTE: The following describes the new revised Version C RF board described in Section... The RF Board is not field serviceable. It must be replaced as a unit with a new board... RECEIVER Front End Bandpass Filter A varactortuned bandpass filter (including W and W) is used in the frontend of the receiver. This filter provides firstimage rejection with minimal loss to provide the desired level of receiver sensitivity. The frontend bandpass filter center frequency is tuned via voltages from an channel D/A converter. Ceramic resonators provide a high circuit Q and lower loss than a fixed inductor. A backtoback varactor diode configuration increases the circuit's thirdorder intercept point. Front End LNA and Bypass Switching Low Noise Amplifier (LNA) U is critical in determining the overall noise figure of the receiver. The RF amplifier provides a good noise figure, gain, intercept point and power consumption. RF switches U and U bypass the signal around the LNA when required to increase the effective thirdorder intercept point and the interference rejection capabilities of the receiver. PostLNA Bandpass Filters Additional bandpass filters are used after the LNA. These filters are fixedtuned since varactortuned filters would have an excessive thirdorder intercept point. One filter bank is tuned to the 00 MHz receive band and the other bank to the 00 MHz receive band. RF switches U and U select the desired band. These filters have better selectivity and more loss than the frontend filters, but the gain of the

36 CIRCUIT DESCRIPTION 00/00 MHz RF BOARD (VERSION C) LNA minimizes the impact of the filter loss on the receiver sensitivity. Mixer and LO Filter A doublebalanced, lowlevel ADEX0L mixer (MX) with a LO drive of dbm is used for the first conversion. This mixer provides good dynamic range with db lower LO drive than the more traditional dbm drive mixers. This provides power savings and reduces conducted and radiated LO leakage from the receiver. A highside mix is used for the 00 MHz receive band and a lowside mix is used for the 00 MHz receive band. This band plan reduces the tuning range requirements for the VCOs. A LO filter (including W and W) is used prior to LO port of the mixer to reduce the effect of wideband noise from the LO synthesizer on the receiver sensitivity. This filter is varactortuned with the center frequency tuned via a voltage from a D/A converter. IF Filter and Amplifier A fourpole. MHz crystal filter (U) is used to provide the desired level of adjacent channel and image rejection while providing minimal amplitude and phase distortion within the khz bandwidth. Shields are installed around the crystal filter to provide sufficient isolation in order to meet the second image response requirements and minimize noise pickup by the impedancematching inductors (L, L and L.) A transistor IF amplifier (Q and supporting circuitry) is used to boost the signal strength which reduces the overall noise figure. The noise figure, signal gain, intercept point and power consumption are optimized by this circuit. An LC circuit provides the required impedance matching between the output of the IF amplifier and the input of backend chip U. Back End IC An Analog Devices AD IF Digitizing Subsystem IC (U) provides the following receiver functions: Second Local Oscillator A varactortuned transistor (Q) oscillator is phaselocked to a fixed frequency of. MHz in order to convert the first IF of. MHz to a second IF frequency of. MHz. Phase Locked Loop circuitry inside of the AD operates with a phasedetector frequency of khz. Second Conversion Mixer and Filtering A mixer inside the AD converts from the first IF of. MHz to the second IF of. MHz. External filters L and L0 provide IF bandpass filtering. Additional filtering is provided by the inherent operation of the sigmadelta analog/digital converters. Gain Control This device provides up to db of AGC range via a combination of analog and digital controls. Additionally, there is a db attenuator in the front end. The optimum settings are controlled by the host microprocessor. Analog/Digital Conversion and Processing SigmaDelta Converters provide I and Q sampling directly from the second IF frequency. The resulting digital words are first filtered by internal programmable FIR filters and then clocked out of the AD via a serial data bus using a programmable data rate... SYNTHESIZER PLL IC A CX0 sigmadelta modulated PLL (U) is used as the main receive and transmit synthesizer. This PLL chip provides exceptional phase noise capabilities to reduce adjacent channel interference and quick switching between the receive and transmit modes. In the receive mode the PLL is programmed to a Local Oscillator frequency that is. MHz from the receive frequency. For the 00 MHz receive band, the LO frequency is higher than the receive frequency, and for the 00 MHz band, it is lower than the receive frequency. In transmit mode, the PLL is programmed directly to select the desired transmit frequency. Reference Oscillator A. MHz oscillator (Y) provides the frequency reference for the synthesizer and receiver

37 CIRCUIT DESCRIPTION backend IC. The center frequency of this oscillator is corrected using a DC tuning voltage from the digital board during receive and it is modulated with voice or data during transmit. Analog Switches and PLL Loop Filters Analog switches U, U, and U provide faster channel switching by changing the time constant of the PLL loop filters. VCOs 00/00 MHz RF BOARD (VERSION C) Three different VCOs are used. VCO U is used strictly in transmit mode. It's tuning range covers the entire transmit and receive frequency bands. Transmit modulation is provided to this oscillator's modulation port from the digital board through R. Two receive VCOs (U and U) are required to meet the phase noise requirements. Each VCO functions for only one of the two receive bands. An RF buffer amplifier (U0) provides the required level of drive for the receiver mixer's local oscillator signal as discussed above... TRANSMITTER Modulation A dualport modulation scheme is used to provide DC coupling of the signal for data modulation applications. Modulation applied to the PLL frequency reference provides lowfrequency modulation, and modulation applied to the PLL transmit VCO (U) provides highfrequency modulation. Signals for both modulation ports are provided from DACs on the digital board. Power Amplifier Power Amplifier U is a RA0M0M module. It provides the desired RF power output level and is stable over a wide range of VSWR conditions. The PA is driven by a SGA driver (U0) that typically provides dbm output power. The PA is turned on and off by switching the power to this driver via transistor D0. ALC RF BOARD OVERVIEW (VERSION A/B) To maintain the specified Transmitter output power level, Automatic Level Control (ALC) is provided to control the drive level to the PA. The detected forward power is compared to a reference level provided by the digital board via op amp UA. The resulting error voltage is applied to a powerlevel control port of the power amplifier module. Transmitter on/off splatter filtering is provided by RC network R, R, C and C. T/R Switching and Harmonic Filter The output of the power amplifier is applied to transmit/receive RF switch U. This is a high dynamicrange switch that is capable of passing the desired transmit power with minimal compression. Any harmonics generated by the PA module and the RF T/R switch are filtered by a harmonic filter that is between the RF T/R switch and the antenna jack.. RF BOARD OVERVIEW (VERSION A/B) NOTE: The following describes the earlier Version A and B RF boards described in Section... The RF Board is not field serviceable. It must be replaced as a unit with a new board. The receiver front end consists of a preselector, an RF amplifier, a second preselector, and a mixer (see Figure ). With VHF and UHF models, both preselectors are varactortuned, two pole filters controlled by the control logic. With 00 MHz models, these filters are fixedtuned. The RF amplifier is a dualgate, galliumarsenide based IC. The mixer is a doublebalanced, active mixer coupled by transformers. Injection is provided by the VCO through an injection filter. Refer to Table for local oscillator (LO) and first IF information. Table LO and First IF Frequencies LO Frequency range First IF Frequency VHF UHF 00 MHz.. MHz.. MHz.. MHz. MHz. MHz. MHz 0

38 CIRCUIT DESCRIPTION VHF/UHF RF BOARD (VERSION A/B) Figure RF Board Block Diagram (Version A/B) The frequency generation function is performed by three ICs and associated circuitry. The reference oscillator provides a frequency standard to the synthesizer/prescaler IC which controls the VCO IC. The VCO IC actually generates the first LO and transmitinjection signals and buffers them to the required power level. The synthesizer/prescaler circuit module incorporates frequencydivision and comparison circuitry to keep the VCO signals stable. The synthesizer/prescaler IC is controlled by the control logic through a serial bus. Most of the synthesizer circuitry is enclosed in rigid metal cans to reduce microphonic effects. The receiver back end consists of a twopole crystal filter, an IF amplifier, a second twopole crystal filter, and the digital backend IC (ABACUS). The twopole filters are wide enough to accommodate khz modulation. Final IF filtering is done digitally in the ADSIC. The digital backend IC (ABACUS) consists of an amplifier, the second mixer, an IF analogtodigital converter, a baseband downconverter, and a. MHz synthesis circuit. The second LO is generated by discrete components external to the IC. The output of the ABACUS IC is a digital bit stream that is current driven on a differential pair for a reduction in noise generation. The transmitter consists of an RF PA IC that gets an injection signal from the VCO. Transmit power is controlled by two custom ICs that monitor the output of a directional coupler and adjust PA control voltages correspondingly. The signal passes through a Rx/Tx switch that uses PIN diodes to automatically provide an appropriate interface to transmit or receive signals.. VHF/UHF RF BOARD (VERSION A/B) NOTE: The following describes the earlier Version A and B RF boards described in Section..... FREQUEY GENERATION UNIT (FGU) The frequency generation unit (FGU) consists of three major sections: the high stability reference oscillator (U0), the fractionaln synthesizer (U0,) and the VCO buffer (U0). A V regulator (U0), supplies power to the FGU. The synthesizer receives the V REG at U0, and applies it to a filtering circuit within the module and capacitor C. The wellfiltered volt output at U0, pin is distributed to the Tx and Rx VCOs and the VCO buffer IC. The mixer s LO injection signal and transmit frequency are generated by the Rx VCO and Tx VCO, respectively. The Rx VCO uses an external active

39 CIRCUIT DESCRIPTION VHF/UHF RF BOARD (VERSION A/B) device (Q0), whereas the VHF Tx VCO s active device is a transistor inside the VCO buffer. The UHF Tx VCO uses two active devices, one external (Q0) and the other internal to the VCO buffer. The base and emitter connections of this internal transistor are pins and of U0. The Rx VCO is a Colpittstype oscillator, with capacitors C and C providing feedback. The Rx VCO transistor (Q0) is turned on when pin of U0 switches from high to low. The Rx VCO signal is received by the VCO buffer at U0, pin, where it is amplified by a buffer inside the IC. The amplified signal at pin is routed through a lowpass filter (L0 and associated capacitors) and injected as the first LO signal into the mixer (U, pin ). In the VCO buffer, the Rx VCO signal (or the Tx VCO signal during transmit) is also routed to an internal prescaler buffer. The buffered output at U0, pin is applied to a lowpass filter (L0 and associated capacitors). After filtering, the signal is routed to a prescaler divider in the synthesizer at U0, pin. The divide ratios for the prescaler circuits are determined from information stored in memory during programming. The microcontroller extracts data for the division ratio as determined by the selected channel and sends that information to a comparator in the synthesizer via a bus. A. MHz reference oscillator, U0, applies the. MHz signal to the synthesizer at U0 pin. The oscillator signal is divided into one of three predetermined frequencies. A timebased algorithm is used to generate the fractionaln ratio. If the two frequencies in the synthesizer s comparator differ, a control (error) voltage is produced. The phase detector error voltage (V control) at pins and of U0 is applied to the loop filter consisting of resistors R, R, and R, and capacitors C, C, C, and C. The filtered voltage alters the VCO frequency until the correct frequency is synthesized. The phase detector gain is set by components connected to U0, pins and. In the Tx mode, U0, pin goes high and U0, pin goes low, which turns off transistor Q0 and turns on the internal Tx VCO transistor in U0 and the external Tx VCO buffer Q0 on the UHF circuit. The Tx VCO feedback capacitors are C and C0. Varactor diode CR0/CR0 sets the Tx frequency while varactor CR0 is the Tx modulation varactor. The modulation of the carrier is achieved by using a twoport modulation technique. The modulation of low frequency tones is achieved by injecting the tones into the A/D section of the fractionaln synthesizer. The digitized signal is modulated by the fractionaln divider, generating the required deviation. Modulation of the highfrequency audio signals is achieved by modulating the varactor (CR0) through a frequency compensation network. Resistors R0 and R0 form a potential divider for the higherfrequency audio signals. In order to cover the very wide bandwidths, positive and negative Vcontrol voltages are used. High control voltages are achieved using positive and negative multipliers. The positive voltage multiplier circuit consists of components CR0, C, C, and reservoir capacitor C. The negative multiplier circuit consists of components CR0, CR0, C, C, and reservoir capacitor C. Outofphase clocks for the positive multiplier appear at U0, pins and 0. Outofphase clocks for the negative multiplier appear at U0, pins and, and only when the negative Vcontrol is required (that is, when the VCO frequency exceeds the crossover frequency). When the negative Vcontrol is not required, transistor Q0 is turned on, and capacitor C discharges. The V supply generated by the positive multiplier is used to powerup the phase detector circuitry. The negative Vcontrol is applied to the anodes of the VCO varactors. The Tx VCO signal is amplified by an internal buffer in U0, routed through a low pass filter and routed to the Tx PA module, U0, pin. The Tx and Rx VCOs and buffers are activated via a control signal from U0, pin. The reference oscillator supplies a. MHz clock to the synthesizer where it is divided down to a. MHz clock. This divideddown clock is fed to the ABACUS IC (U0), where it is further processed for internal use.

40 CIRCUIT DESCRIPTION VHF/UHF RF BOARD (VERSION A/B).. ANTENNA SWITCH The antenna switch is a current device consisting of a pair of diodes (CR0/ CR0) that electronically steer RF between the receiver and the transmitter. In the transmit mode, RF is routed through transmit switching diode CR0, and sent to the antenna. In the receive mode, RF is received from the antenna, routed through receive switching diode CR0, and applied to the RF amplifier Q (VHF) or U (UHF). In transmit, bias current, sourced from U0, pin, is routed through L0, U0, CR0, and L (VHF) and L0, CR0, and L (UHF). Sinking of the bias current is through the transmit ALC module, U0, pin. In the receive mode, bias current, sourced from switched B, is routed through Q0 (pin to pin ), L (UHF), L, CR0, and L. Sinking of the bias current is through the volt regulator, U0, pin... RECEIVER FRONT END The RF signal is received by the antenna and coupled through the external RF switch. The UHF board applies the RF signal to a lowpass filter consisting of L, L, L, C, C0, and C. The VHF board bypasses the lowpass filter. The filtered RF signal is passed through the antenna switch (CR0) and applied to a bandpass filter consisting of (VHF) L L, CR CR, C, C, and C or (UHF) L0, L, L, L, L, CR CR, C, C, and C. The bandpass filter is tuned by applying a control voltage to the varactor diodes in the filter (CR CR VHF and CR CR UHF). The bandpass filter is electronically tuned by the D/A IC (U0), which is controlled by the microcomputer.the D/A output range is extended through the use of a current mirror consisting of Q0 and R and R. When Q0 is turned on via R, the D/A output is reduced due to the voltage drop across R. Depending on the carrier frequency, the microcomputer will turn Q0 on or off. Wideband operation of the filter is achieved by retuning the bandpass filter across the band. The output of the bandpass filter is applied to wideband GaAs RF amplifier IC U (UHF) or active device Q (VHF). The RF signal is then further filtered by a second broadband, fixedtuned, bandpass filter consisting of C, C, C, C0, C, C, C, C, C, L, L, L, and L0 (VHF) or C C, C C, C, and L L (UHF) to improve the spurious rejection. The filtered RF signal is routed through a broadband 0ohm transformer (T) to the input of a broadband mixer/buffer (U). Mixer U uses GaAs FETs in a doublebalanced, Gilbert Cell configuration. The RF signal is applied to the mixer at U pins and. An injection signal (st LO) of about 0 dbm supplied by the FGU is applied to U, pin. Mixing of the RF and the st LO results in an output signal that is the first IF frequency. The first IF frequency is. MHz for the VHF band and. for the UHF band. High side injection is used for VHF and low side for UHF. The first IF signal output at U, pins and is routed through transformer T and impedance matching components, and applied to a twopole crystal filter (FL), which is the final stage of the receiver front end. The twopole crystal filter removes unwanted mixer products. Impedance matching between the output of the transformer (T) and the input of the filter (FL) is accomplished by C0 and L0 (VHF) or C, C, and L0 (UHF)... RECEIVER BACK END The output of crystal filter FL is matched to the input of IF buffer amplifier transistor Q0 by C0 and L0 (VHF) and C0, C0, and L00 (UHF). Transistor Q0 is biased by the V regulator (U0). The IF frequency on the collector of Q0 is applied to a second crystal filter through a matching circuit. The second crystal filter (FL) input is matched by C0, C0, and L0 (VHF) and C0, L0, and L0 (UHF). The filter supplies further attenuation at the IF sidebands to increase the radios selectivity. The output of FL routed to pin of U0 through a matching circuit which consists of L0, L0, and C0 (VHF) and L0, C0, and C0 (UHF). In the ABACUS IC (U0), the first IF frequency is amplified and then downconverted to the second IF frequency of 0 khz. At this point, the analog signal is converted into two digital bit streams by a sigmadelta A/D converter. The bit streams are then digitally

41 CIRCUIT DESCRIPTION VHF/UHF RF BOARD (VERSION A/B) filtered, mixed down to baseband, and filtered again. The differential output data stream is then sent to the logic board where it is decoded to produce the recovered audio. The ABACUS IC (U0) is electronically programmable. The amount of filtering, which is dependent on the radio channel spacing and signal type, is controlled by the microcontroller. Additional filtering, which used to be provided externally by a conventional ceramic filter, is replaced by internal digital filters in the ABACUS IC. The ABACUS IC contains a feedback AGC circuit to expand the dynamic range of the sigmadelta converter. The differential output data contains the quadrature (I and Q) information in bit words, the AGC information in a bit word, imbedded word sync information, and fill bits dependent on sampling speed. A fractional N synthesizer is also incorporated on the ABACUS IC for nd LO generation. The nd LO/VCO is a Colpitts oscillator built around transistor Q0 (VHF) or Q (UHF). The VCO has a varactor diode, VR0 (VHF) or CR (UHF) to adjust the VCO frequency. The control signal for the varactor is derived from a loop filter consisting of C, C, and R... TRANSMITTER The transmitter consists of three major sections: Harmonic Filter RF Power Amplifier Module ALC Circuits Harmonic Filter With VHF versions, RF from PA module U0 is routed through coupler U0 and passed through the harmonic filtering network to antenna switch CR0. With UHF versions, RF from the PA module U0 is routed through coupler U0 and passed through transmit antenna switch CR0 and applied to a harmonic filtering network. The harmonic filtering circuit is composed of (VHF) L, L, L, C, C0, and C or (UHF) L, L, L, C, C0, C, C0, and C. Resistor R (VHF) or R (UHF) provides a currentlimited V to J. RF Power Amplifier Module RF power amplifier module U0 is a wideband, threestage (VHF) or fourstage (UHF) amplifier. Nominal input and output impedance of U0 is 0 ohms. The DC bias for U0 is on pins,,. In the transmit mode, the voltage on U0, pins and (close to the B level) is obtained via switching transistor Q0. Transistor Q0 receives its control base signal as follows: The microcomputer keys the D/A IC to produce a ready signal at U 0 pin, the ready signal at U0 pin is applied to the Tx ALC IC at U0 pin (V), and the synthesizer sends a LOC signal to the Tx ALC IC (U0 pin 0 to U0 pin ). When the LOC signal and the ready signal are both received, the Tx ALC IC (pin ) sends a control signal to turn on transistor Q0. ALC Circuits Coupler module U0 samples the forward and reverse power of the PA output voltage. Reverse power is present when there is other than 0 ohms impedance at the antenna port. Sampling is achieved by coupling some of the forward and/or reverse power, and applying it to CR0 (VHF) or CR0 (UHF) and CR0 for rectification and summing. The resultant DC signal is then applied to the Tx ALC IC (U0, pin ) as RFDET to be used as an RF strength indicator. The transmit ALC circuit, built around U0, is the heart of the power control loop. Circuits in the Tx ALC module compare the signals at U0, pins and. The resultant signal, C BIAS, at U0, pin is applied to the base of transistor Q0. In response to the base drive, transistor Q0 varies the DC control voltages applied to the RF PA at U0, pin, thus controlling the RF power of module (U0). Thermistor RT0 senses the temperature of the Tx ALC IC. If an abnormal operating condition exists that causes the PA temperature to rise to an unacceptable level, the thermistor forces the ALC to reduce the set power.

42 CIRCUIT DESCRIPTION 00 MHz RF BOARD (VERSION A/B). 00 MHz RF BOARD (VERSION A/B) NOTE: The following describes the earlier Version A and B RF boards described in Section.... FREQUEY SYNTHESIS The complete synthesizer subsystem consists of the reference oscillator (U0), the voltagecontrolled oscillator (VCO U0), a buffer IC (U0), and the synthesizer (U0). The reference oscillator contains a temperaturecompensated. MHz crystal. This oscillator is digitally tuned and contains a temperaturereferenced, fivebit, analogtodigital (A/D) converter. The output of the oscillator (pin 0 on U0) is applied to pin (XTAL) on U0 through capacitor C0 and resistor 0. Voltagecontrolled oscillator module U0 is varactor tuned. Therefore, as the voltage being applied to pins and of the VCO varies (V), so does the varactor's capacitance which changes the VCO output frequency. The 00 MHz VCO is a dualrange oscillator that covers the 0 MHz and the 0 MHz frequency bands. The lowband VCO ( MHz) provides the first LO injection frequencies ( MHz) that are. MHz below the carrier frequency. In addition, in the transmit mode when the radio is operated through a repeater, the lowband VCO generates the transmit frequencies (0 MHz) that are MHz below the receiver frequencies. The low band VCO is selected by pulling pin high and pin low on U0. When radiotoradio or talkaround operation is necessary, the high band VCO (0 MHz) is selected. This is accomplished by pulling pin low and pin high on U0. The buffer IC (U0) includes a Tx, Rx, and prescaler buffer which maintain a constant output level and provides isolation. The Tx buffer is selected by setting pin of U0 high, and the Rx buffer is selected by setting pin of U0 low. The prescaler buffer is always on. In order to select the proper combination of VCO and buffer, the following conditions must be true at pin of U0 (or pin of U0) and pin of U0 (or pin of U0): For first LO injection frequencies MHz, pins and must both be low. For Tx repeater frequencies 0 MHz, pins and must both be high. For talkaround Tx frequencies 0 MHz, pin must be low and pin must be high. The synthesizer IC (U0) consists of a prescaler, a programmable loop divider, a divider control logic, a phase detector, a charge pump, an A/D converter for lowfrequency digital modulation, a balance attenuator to balance the highfrequency analog modulation to the lowfrequency digital modulation, a V positivevoltage multiplier, a serial interface for control, and finally, a filter for the regulated volt supply. This filtered five volts is present at pin of U0, pin of U0, and pins,,, and of U0. It is also applied directly to resistors R0, R, and R. Additionally, the V supply generated by the positive voltage multiplier circuitry should be present at pin of U0. The serial interface (SRL) is connected to the microprocessor via the data line (pin of U0), clock line (pin of U0), and chipenable line (pin of U0). The complete synthesizer subsystem operates as follows: The output of the VCO, pin on U0, is fed into the RF input port (pin ) of U0. In the Tx mode, the RF signal is present at pin of U0; in the RX mode, the RF signal is present at pin of U0. The output of the prescaler buffer, pin of U0, is applied to the PREIN port (pin ) of U0. The prescaler in U0 is a dual modulus type with selectable divider ratios. This divider ratio is controlled by the loop divider, which in turn receives its inputs from the SRL. The loop divider adds or subtracts phase to the prescaler divider by changing the divide ratio via the modulus control line. The output of the prescaler is then applied to the loop divider. The output of the loop divider is then applied to the phase detector. The phase detector compares the

43 CIRCUIT DESCRIPTION 00 MHz RF BOARD (VERSION A/B) loop divider's output signal with the signal from U0 (that is divided down after it is applied to pin of U0). The result of the signal comparison is a pulsed DC signal which is applied to the charge pump. The charge pump outputs a current that is present at pin of U0. The loop filter (which consists of capacitors C, C, C, C, C, and C, and resistors R0, R0, and R) transforms this current into a voltage that is applied to pins and of U0 to alter the VCO's output frequency. In order to modulate the PLL, the twoport modulation method is utilized. The analog modulating signal is applied to the A/D converter as well as the balance attenuator, via U0, pin. The A/D converter converts the lowfrequency analog modulating signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. The balance attenuator is used to adjust the VCO's deviation sensitivity to highfrequency modulating signals... ANTENNA SWITCH An electronic PIN diode switch steers RF between the receiver and transmitter. The common node of the switch is at capacitor C0. In the transmit mode, RF is routed to the anode of diode CR0. In receive mode, RF is routed to pin of U0. In the transmit mode, bias current sourced from U0, pin, is routed through PIN diodes CR0 and CR0 which biases them to a lowimpedance state. Bias current returns to ground through U0, pin 0. In receive, U0, pin, is pulled down to ground and pin 0 is pulled up to B which reversebiases diodes CR0 and CR0 to a high impedance... RECEIVER FRONT END The 00 MHz receiver front end converts the received RF signal to the first IF frequency of. MHz and also provides spurious immunity and adjacent channel selectivity. The received RF signal is passed through antenna switch input matching components C0, L0, and C, through tank components C0 and L0 (which are antiresonant at the radios transmitter frequencies), and through output matching components C0 and L0. Both pin diodes CR0 and CR0 must be backbiased to properly route the received signal. The stage following the antenna switch is a 0 ohm, interdigitated, threepole, stripline preselector (U0). The preselector is positioned after the antenna switch to provide the receiver preamp with some protection against strong, outofband signals. After the preselector (U0), the received signal is processed through receiver preamp U0. The preamp is a dualgate, GaAs MESFET transistor which has been internally biased for optimum IM, NF, and gain performance. Components L0 and L0 match the input (gate ) of the amp to the first preselector, while at the same time connecting gate to ground potential. The output (drain) of the amp is pin, and is matched to the subsequent receiver stage by L0 and C. A supply voltage of V DC is provided to pin through RF choke L0 and bypass capacitor C0. The volt supply is also present at pin, which connects to a voltage divider network that biases gate (pin ) to a predefined quiescent voltage of.v DC. Resistor R0 and capacitor C0 are connected to pin to provide amp stability. The FET source (pin ) is internally biased at 0. to 0.VDC for proper operation with bypass capacitors C0 and C0, connected to the same node. The output of the amp is matched to a second threepole preselector (U0) of the type previously discussed. The next stage in the receiver chain is first mixer U0 which uses lowside injection to convert the RF carrier to an intermediate frequency (IF) of. MHz. Since lowside injection is used, the LO frequency is offset below the RF carrier by. MHz, or flo = frf. MHz. The mixer utilizes GaAs FETs in a doublebalanced, Gilbert Cell configuration. The LO port (pin ) incorporates an internal buffer and a phase shift network to eliminate the need for a LO transformer. The LO buffer bypass capacitors (C0, C, and C) are connected to pin 0 of U0, and should exhibit a nominal DC voltage of. to.v DC. Pin of U0 is LO buffer Vdd (V DC), with associated bypass capacitors C and C0 connected to the same node. An internal voltage divider network within the LO buffer is bypassed to virtual ground at pin of U0 through bypass

44 CIRCUIT DESCRIPTION 00 MHz RF BOARD (VERSION A/B) capacitor C. The mixer's LO port is matched to the radio's PLL by a capacitive tap, C0 and C0. A balun transformer (T0) is used to couple the RF signal into the mixer. The primary winding of T0 is matched to the preceding stage by capacitor C, with C providing a DC block to ground. The secondary winding of T0 provides a differential output, with a 0 phase differential being achieved by setting the secondary center tap to virtual ground using bypass capacitors C0, C, and C. The secondary of transformer T0 is connected to pins and of the mixer IC, which drives the source leg of dual FETs used to toggle the paralleled differential amplifier configuration within the Gilbert Cell. The final stage in the receiver front end is a twopole crystal filter (FL). The crystal filter provides some of the receiver's adjacent channel selectivity. The input to the crystal filter is matched to the first mixer using L0, C00, and C. The output of the crystal filter is matched to the input of IF buffer amplifier transistor Q0 by L00, C0, and C0... RECEIVER BACK END The IF frequency on the collector of Q0 is applied to a second crystal filter (FL) through a matching circuit consisting of L0, L0, C0, and C. The filter supplies further attenuation at the IF sidebands to increase the radio's selectivity. The output of FL is routed to pin of U0 through a matching circuit consisting of L0, C0, and C0, and DC blocking capacitor C. In the ABACUS IC (U0), the first IF frequency is amplified and then downconverted to the second IF of 0 khz. The analog signal is then converted into two digital bit streams by a sigmadelta A/D converter. The bit streams are then digitally filtered, mixed down to baseband, and filtered again. The differential output data stream is then sent to the ADSIC on the logic board, where it is decoded to produce the recovered audio. The ABACUS IC (U0) is electronically programmable. The amount of filtering is dependent on the radio channel spacing and signal type, and is controlled by the microcomputer. Additional filtering, which used to be provided externally by a conventional ceramic filter, is replaced by internal digital filters in the ABACUS IC. The ABACUS IC contains a feedback AGC circuit to expand the dynamic range of the sigmadelta converter. The differential output data contains the quadrature (I and Q) information in bit words, the AGC information in a bit word, imbedded word sync information, and fill bits which are dependent on sampling speed. A fractional N synthesizer is also incorporated on the ABACUS IC for nd LO generation. The second LO/VCO is a Colpitts oscillator built around transistor Q. The VCO has a varactor diode (VR0), which is used to adjust the VCO frequency. The control signal for the varactor is derived from a loop filter consisting of C, C, and R... TRANSMITTER The 00 MHz RF power amplifier (PA) is a fivestage amplifier (U0). The RF power amplifier has a nominal input and output impedance of 0 ohms. An RF input drive level of approximately dbm, supplied from the VCO buffer IC (U0), is applied to pin of U0. The DC bias for the internal stages of U0 is applied to pins and of the module. Pin is switched through Q0 and pin is unswitched B to the final amplifier stage. Power control is achieved by varying of the DC bias to pin, the third and fourth amplifier stages of the module. The amplified RF signal leaves the PA module at pin and is applied to the directional coupler (U0). The purpose of U0 is to sample both the forward power and the reverse power. Reverse power is present when a load other than 0 ohms exists at the antenna port. The sampling is achieved by coupling some of the reflected power, forward and/or reverse, to a coupled leg on the coupler. The sampled RF signals are applied to diode CR0 for rectification and summing. The resultant DC signal is applied to the ALC IC (U0, pin ) as RFDET, to be used as an indicator of the strength of the RF signal being passed through the directional coupler (U0). The transmit ALC IC (U0) is the main part of the power control loop. The REF V line (U0 pin ), a DC signal supplied from the D/A IC (U0), and the RF DET signal described earlier, are compared internally in the ALC IC to determine the amount of C BIAS, pin, to be applied to the base of transistor

45 CIRCUIT DESCRIPTION UI BOARD (ALL VERSIONS) Q0. Transistor Q0 responds to the base drive level by varying the DC control voltages applied to pin of the RF PA which controls the RIF power level of module U0. The ALC IC also controls the base switching to transistor Q0 via pin, BIAS. The D/A IC (U0) controls the DC switching of the transceiver board. Its outputs, SC and SC (pins and, respectively), control transistor Q0 which then supplies Tx V and Rx V to the transceiver board. The D/A also supplies DC bias to the detector diode (CR0) via pin, and the REF V signal to the ALC IC (U0).. USER INTERFACE BOARD (ALL) NOTE: The following describes all three logic versions described in Section.... INTRODUCTION The User Interface Board contains the main microcontroller which controls all functions of the transceiver. In addition, it contains memory (Flash, SRAM, and EEPROM), AD and DA converters, the interface to the graphic display, audio circuitry, and various other interfaces... MICROCONTROLLER (U) Microcontroller U is PowerPC based which gives this transceiver processing power equal to some current desktop computers. This microcontroller provides all transceiver control functions except signal processing which is provided by the DSP U on the logic board. Functions provided by U include detecting key and button presses, processing incoming and outgoing calls, displaying operational data to the user, and coordinating control of the other processor (DSP) located on the logic board. Communication with the DSP is via a bit host port. The operating speed of U is controlled by. MHz crystal Y. The internal clock is five times this frequency or. MHz ( MHz operational)... MEMORY Early Units (Versions A and B in Section.) Memory devices include Flash, SRAM, EEPROM, and DSP SRAM. There is megabyte of Flash that is used primarily for code storage but can can also be used for as nonvolatile memory. The SRAM (static RAM) consists of one K x and one K x device (U and U), each of which used a different chip select. A K x EEPROM (U) is used to store personality data. Later Units (Version C in Section.) Memory devices include Flash, SRAM, EEPROM, and DSP SRAM. There is megabyte of Flash that is used primarily for code storage but can can also be used for as nonvolatile memory. The SRAM (static RAM) consists of a M x device (U). A K x EEPROM (U) is used to store personality data... GRAPHICAL DISPLAY The graphical display is connected to J. This type of display allows text and icons to be positioned anywhere on the display and allows text to be displayed in various fonts (type styles).. LOGIC BOARD (VERSION C) NOTE: The following describes the Version C logic board described in Section.... INTRODUCTION The Digital Signal Processing (DSP) functions are performed by the DSP chip (U) and the CODEC (U) with the support of microcontroller U on the UI board. Functions previously performed in hardware like filtering and limiting are performed by software running in the DSP chip.

46 CIRCUIT DESCRIPTION LOGIC BOARD (VERSION C).. DIGITAL SIGNAL PROCESSING OVERVIEW The DSP section consists of a DSP chip (U) and the CODEC (U). The CODEC is a support chip for the DSP. It provides the interface between the DSP and the analog signal paths, and between the DSP and the Digital IF chip on the RF Board. Configuration of the Digital IF chip is handled primarily by microcontroller U. In receive mode, the DSP interfaces with the Digital IF chip IC on the RF Board. The DSP collects the I and Q samples from the Digital IF chip and performs channel filtering and frequency discrimination on the signals. The resulting demodulated signal is routed to the DSP via the serial port for further processing. After the DSP processing, the signal is sent to the CODEC Speaker D/A by writing to a memorymapped register. The CODEC then converts the processed signal from the DSP to an analog signal and then outputs this signal to a single ended to differential converter (UA/D). It is then routed to the UI board, amplified, and then sent to the speaker. In transmit mode the microphone signal is converted to a differential signal on the UI board and then routed to logic board, converted back to single ended, and then applied to the CODEC and digitized by an internal A/D converter. The DSP reads these values from a memorymapped register in the CODEC. After processing, the DSP sends the modulation signal to the CODEC via the serial port. In the CODEC, the VCO D/A converts the sampled modulation signal into an analog signal and then routes this signal to the VCO on the RF Board... RECEIVE SIGNAL PATH The Digital IF chip on the RF Board provides a digital back end for the receiver section. It provides a digital output of I (in phase) and Q (quadrature) samples which represent the IF signal at the receiver back end. These samples are routed to the DSP where the signal is filtered and frequency discriminated to recover the modulating signal. LOGIC BOARD (VERSION A/B).0 LOGIC BOARD (VERSION A/B) NOTE: The following describes the Version A and B logic board described in Section...0. INTRODUCTION The Digital Signal Processing (DSP) functions are performed by the DSP chip (U) and the ADSIC (U) with the support of microcontroller U on the UI board. Functions previously performed in hardware like filtering and limiting are performed by software running in the DSP chip..0. DIGITAL SIGNAL PROCESSING OVERVIEW The DSP section consists of a DSP chip (U) and the ADSIC (U). The ADSIC is a support chip for the DSP. It provides the interface between the DSP and the analog signal paths, and between the DSP and the ABACUS chip on the RF Board. Configuration of the ADSIC is handled primarily by microcontroller U. The DSP has access to a few memorymapped registers on the ADSIC. In receive mode, the ADSIC interfaces the DSP with the ABACUS IC on the RF Board. The ADSIC collects the I and Q samples from the ABACUS and performs channel filtering and frequency discrimination on the signals. The resulting demodulated signal is routed to the DSP via the serial port for further processing. After the DSP processing, the signal is sent to the ADSIC Speaker D/A by writing to a memorymapped register. The ADSIC then converts the processed signal from the DSP to an analog signal and then outputs this signal to a single ended to differential converter (UA/B). It is then routed to the UI board, amplified, and then sent to the speaker. In transmit mode the microphone signal is converted to a differential signal on the UI board and then routed to logic board, converted back to single ended, and then applied to the ADSIC and digitized by an internal A/D converter. The DSP reads these values from a memorymapped register in the ADSIC. After processing, the DSP sends the modulation signal to the

47 CIRCUIT DESCRIPTION LOGIC BOARD (VERSION A/B) ADSIC via the serial port. In the ADSIC, the VCO D/ A converts the sampled modulation signal into an analog signal and then routes this signal to the VCO on the RF Board..0. RECEIVE SIGNAL PATH The ABACUS IC on the RF Board provides a digital back end for the receiver section. It provides a digital output of I (in phase) and Q (quadrature) samples which represent the IF signal at the receiver back end. These samples are routed to the ADSIC where the signal is filtered and frequency discriminated to recover the modulating signal. The recovered signal is sent to the DSP chip for processing. The ADSIC interface to the ABACUS is comprised of four signals SBI, DIN, DIN*, and ODC. SBI is a programming data line for the ABACUS. This line is used to configure the operation of the ABACUS and is driven by the ADSIC. Microcontroller U programs many of the ADSIC operational features through the SPI interface. There are configuration registers in the ADSIC of which contain configuration data for the ABACUS. When these particular registers are programmed by the microcontroller, the ADSIC in turn sends this data to the ABACUS through the SBI. DIN and DIN* are the data lines in which the I and Q data words are transferred from the ABACUS. These signals make up a differentially encoded current loop. Instead of sending TTLtype voltage signals, the data is transferred by flowing current one way or the other through the loop. This helps reduce internally generated spurious emissions on the RF Board. The ADSIC contains an internal current loop decoder which translates these signals back to TTL logic and stores the data in internal registers. The ODC signal is a clock the ABACUS provides to the ADSIC. Most internal ADSIC functions are clocked by this ODC signal at a rate of. MHz and are available as soon as the power is supplied to the circuitry. This signal initially may be. or. MHz after powerup. It is programmed by the ADSIC through the SBI signal to. MHz when the ADSIC is initialized by the microcontroller through the SPI bus. For any functionality of the ADSIC to exist, including initial programming, the reference clock must be present. In the fundamental operating mode, the ADSIC transfers raw IF data to the DSP. The DSP then performs IF filtering and discriminator functions to produce a baseband demodulated signal. However, the ADSIC also includes a digital IF and discriminator function and can provide a baseband demodulated signal directly to the DSP. This is typically what occurs. The digital IF filter is programmable by the microcontroller with up to taps. The DSP processes this data through the SSI serial port. This is a sixport synchronous serial bus. The ADSIC transfers the data on the TxD line to the DSP at a rate of. MHz. This is clocked synchronously by the ADSIC which provides a. MHz clock on SCKT. In addition, a 0 khz interrupt is provided on TFS to signal the arrival of a data packet. This means a new I and Q sample data packet is available to the DSP at a 0 khz rate which represents the sampling rate of the received data. The DSP then processes this data to extract audio, signaling, and other information based on the 0 khz interrupt. In addition to the SPI programming bus, the ADSIC also contains a parallel configuration bus. This bus is used to access registers mapped into the DSP memory. Some of these registers are used for additional ADSIC configuration controlled directly by the DSP. Some of the registers are data registers for the speaker D/A. Analog speaker audio is processed through this parallel bus where the DSP outputs the speaker audio digital data words to this speaker D/A. In addition, an analog waveform is generated which is output to SDO (Speaker Data Out). In conjunction with speaker D/A, ADSIC contains a programmable attenuator to set the rough signal attenuation. However, the fine levels and differences between signal types are adjusted through the DSP software algorithms. The speaker D/A attenuator setting is programmed by the microcontroller through the SPI bus. The ADSIC provides an khz interrupt to the DSP on IRQB for processing the speaker data samples. This khz signal must be enabled through the SPI programming bus by the microcontroller and is necessary for any audio processing to occur. 0

48 CIRCUIT DESCRIPTION LOGIC BOARD (VERSION A/B).0. TRANSMIT SIGNAL PATH The ADSIC contains an analogtodigital (ADC) converter for the microphone. The microphone path in the ADSIC also includes an attenuator that is programmed by the microcontroller through the SPI bus. The microphone input in the ADSIC is on pin MAI (U). The microphone ADC converts the analog signal to a series of data words and stores them in internal registers. The DSP accesses this data through the parallel data bus. As with the speaker data samples, the DSP reads the microphone samples from registers mapped into its memory space. The ADSIC provides an khz interrupt to the DSP on IRQB for processing the microphone data samples. The DSP processes these microphone samples and generates and mixes the appropriate signaling and filters the resultant data. This data is then transferred to the ADSIC on the DSP SSI port. The ADSIC generates a khz interrupt so that a new sample data packet is transferred at a khz rate and sets the transmit data sampling rate at ksps. These samples are then input to a transmit D/A which converts the data to an analog waveform. This waveform is the modulation signal from the ADSIC and is connected to the VCO on the RF Board..0. ADSIC (U) The ADSIC is a complex custom IC which performs many analogtodigital, digitaltoanalog, and purely digital functions as previously described. The ADSIC has four internal registers accessible by the DSP. Two of these registers are readonly while the two others are writeonly. Therefore, they can be accessed as two locations in the I/O spaces. Crystal Y along with the internal oscillator in the ADSIC provide a 0 MHz clock. This clock signal is used internally by the ADSIC and is also multiplied by two to provide a 0 MHz clock to the DSP. The frequency of the clock can be electronically shifted a small amount by controlling varicap D through the OSCW pin (U). This removes interference created on some channels by the clock. The ADSIC and DSP exchange the sampled receive data and the sampled VCO modulation signal AUDIO CIRCUIT (VERSION A/B) through a serial port. This serial port consists of pins SCKR, RFS, RxD, TxD, SCKT, and TFS on the ADSIC. SDO is the output of the internal speaker DAC. MAI is the input of the internal microphone attenuator and is followed by the microphone ADC. The ADSIC is configured partially by the DSP through its data and address bus. However, most of the configuring is provided through an SPI compatible serial bus. This SPI serial bus consists of pins SEL*, SPD, and SCLK.. AUDIO CIRCUIT (VERSION A/B) NOTE: The following describes the Version A and B logic described in Section.... RECEIVE AUDIO CIRCUIT NOTE: A block diagram of the audio circuit is shown in Figure. In receive mode, the analog receive waveform created by ADSIC U (on the Logic Board) is fed out of that device on the SDO (Signal Data Out) pin. It is then converted to a differential signal by UC and UD to minimize noise. The signal is then fed to the UI board on the Audio_Out_P/M lines and converted back to a singleended signal by UB. It is then combined by UC with any tones from UA and applied to the audio amplifiers. Audio amplifier U provides amplification for the internal ohm speaker and U provides amplification for an external speakermicrophone connected to pins and of the accessory (UDC) connector. U and U provide 0 mw of power with an ohm load. The gain of U and U is controlled by the DC voltage on the Vin () pin. When this pin is grounded by mute switches Q0 or Q, no output is produced. Gain then increases as this DC voltage increases. The volume control signal is produced as follows: The top panel volume control produces a varying DC voltage that is buffered by U0 on the UI board. This voltage is then applied to A/D converter U and

49 CIRCUIT DESCRIPTION AUDIO CIRCUIT (VERSION A/B) RF Board Logic Board Tone Sig UA Tones Buffer UI Board Internal Speaker Amp U SPx ohms Rx Signal Data (SBI/DIN/DIN*/ODC) Modulation In U SDO ADSIC VVO MAI U DSP Rx Audio SDO Mute U Mute Switch UA UA/B SingleDiff Converter J Rx Audio Mute PD UB DiffSingle Converter Microcontroller U PA Volume Control Amp U Mute B UC Combiner Q0 Internal Spkr Mute External Speaker Amp U Q SingleEnd Control To Acc Jack (UDC) Pins, nseop Mute A Q External Spkr Mute.V UC/D DiffSingle Converter Audio_In_M Audio_In_P DC Vol Level U D/A Converter Volume Data Volume Data UA/D SingleDiff Converter U A/D Converter U Int/Ext Mic Sel Sw U0 Volume Lev Buffer UC Buffer UB Top Panel Volume Control External Mic In From Acc Jack (UDC) Pin SRC_SEL Buffer Microphone MKxx Figure Audio Circuit Block Diagram converted to serial data which is fed to microcontroller U. This allows the microcontroller to determine the volume level that is currently set by the user. To set the volume level, the microcontroller then programs D/A converter to produce a DC output voltage that sets the desired volume level. This arrangement allows the microcontroller to totally control the volume level. The volume control voltage is then buffered by U and applied to the volume control pin (Vin) of audio amplifiers U and U. Q is connected to the Head Phone Sense pin () of amplifier U. When Q is turned off by the nseop signal, pin goes high and U switches from the differential to the singleended output mode. This allows an external speakermicrophone to be connected from pin to ground instead of across pins and... TRANSMIT AUDIO CIRCUIT NOTE: A block diagram of the audio circuit is shown in Figure. In transmit mode, the audio for transmission can be selected from either the internal microphone or an external microphone connected to pin of the accessory (UDC) connector. Supply voltage is applied to the internal microphone through R with C providing DC blocking. UB provides buffering and lowpass filtering. UC and related components provide the same function for the external microphone signal. Analog switch U selects either the internal or external microphone signal, depending on the logic level on the CS input. The internal microphone pin () is selected when CS is low and the external microphone NO () is selected when it is high. Q provides inversion and buffering of the SRC_SEL signal. The singleended microphone signal is then converted to a differential signal by UA and UD to reduce noise. It is then fed to the logic board on the AUDIO_IN_P/M lines, converted back to a singleended signal by UC and UD, and applied to the MAI (Microphone Audio In) pin of ADSIC U.

50 ALIGNMENT PROCEDURE SECTION ALIGNMENT PROCEDURE DB Connect To Serial Port 00 Test Cable Part No Audio Out Cable Part No SINAD Meter/ AC Voltmeter Communication Monitor Figure Alignment Setup. GENERAL.. INTRODUCTION The following alignment procedure should be performed if repairs are made that could affect the factory alignment or if adjustments may have changed for some other reason. To verify radio operation, the performance tests in Sections. and. can be run. To perform transceiver alignment and performance tests, to following are required: PCTune Kit, Part No This kit includes the 0 test cable, 0 audio cable, and PCTune software and this manual on a CDROM. SMA (F) to B (F) adapter, Part No. 0 00, to connect test equipment to antenna jack. To operate the radio with the front cover assembly unplugged from the chassis, use UI Logic Extension Test Cable, Part No All adjustments are set digitally using the computer. Therefore, there is no need to disassemble the transceiver to access adjustment points. In addition, audio test signals are generated internally, so an audio generator is not required. The required test equipment is shown in Figure... TUNE SOFTWARE General The PCTune software is a Windows program. Minimum software and hardware requirements are as follows: Windows //NT/000 (. cannot be used) Pentium processor or equivalent MB of RAM A hard disk drive with at least MB of free space A CDROM drive An available serial port

51 ALIGNMENT PROCEDURE Menu Bar Tool Bar Radio Information Tune Category Buttons Adjusts Freq Tuning Instructions Select Next Adjustment Mode/Tool Tip Figure PCTune Main Screen (Version.0) Software Installation Proceed as follows to install this software:. Close all applications that are currently running (other than Windows).. Insert the CDROM containing the PCTune software into the drive.. From the Windows taskbar, choose RUN and open SETUP.EXE on the drive being used. Alternatively, use File Explorer and double click SETUP.EXE.. Follow the instructions on the screen. The program is automatically loaded on the hard drive and startup shortcuts or groups are created. Starting PCTune Select Start in the taskbar, then Programs > PCTune > PCTune. Exiting PCTune Select File > Exit or click the button. OnLine Help Online help is currently not available... PCTUNE VERSION REQUIRED PCTune, Version.0.0 or later is required to tune radios with the Version C RF board (see Section..). The PCTune version number can be displayed by selecting the Help > About menu. This information describes Version.0.0. Earlier versions have a different main screen, but function similarly.. MAIN SCREEN The main PCTune screen is shown in Figure. Information on the various parts of this screen follows: Menu Bar Used to select the menus described in Sections... Tool Bar These buttons are used to quickly select functions as follows: Displays the screen used to set serial port parameters (see Section..).

52 ALIGNMENT PROCEDURE Selects the Partial Tune mode the same as the Transfer > Tune Partial menu (see Section..) This mode allows manual selection of the desired Tune Category and then automatically steps through the various settings for that adjustment. Selects the Edit Mode which allows parameters in the selected screen to be changed without stepping through each adjustment. Reads and displays the current parameters programmed in the radio the same as the Radio > Read Tune Parameters menu (see Section..). Writes the current tune parameters to the radio the same as the Transfer > Write Tune Parameters menu (see Section..). This occurs automatically when a Partial Tune adjustment is completed. Tuning Categories These buttons select the tuning adjustment to be performed. Different functions are displayed for the xx and xx. If the Partial tune mode is selected, these buttons select the particular adjustment that is performed. Mode/Tool Tip Information on the bottom line of the screen indicates the current tune mode and information on the selected button on other information.. MENU BAR DESCRIPTION.. FILE MENU Selecting File > Exit closes the PCTune program... RADIO MENU Exits the current Tune Category without writing parameters to the radio. Radio Information When tuning parameters are read from a radio by clicking the button or selecting the Transfer > Read Parameters menu, the following information is displayed in the top part of the screen: Type The Radio Series selected by the Radio menu (see Section..). The correct series must be selected for communication with the radio to occur. The Radio menu shown above selects the radio type. Also select 00 for the SL and Ascend portable, and also select 00 for the SL and Ascend mobile. The correct radio type must be selected for communication with the radio to occur... TRANSFER MENU Band The radio frequency band of the radio displayed after information is read from radio. Do not select the band using Tools > Set Band (Section..) because this may make the radio nonfunctional. Software DSP The first number is the version number of the radio firmware (Flash/operating code), and the second number is the version number of the DSP software. ESN The Electronic Serial Number electronically stored in the radio. COM Ports Displays the following screen which selects the serial port () and baud rate (00/ 00) used for communication with the radio. Select the computer port to which the test cable is connected (see Section..), and 00 baud is normally

53 ALIGNMENT PROCEDURE selected. These parameters default to the last selected condition the next time the program is started. change the radio series or band or exit an adjustment before it is complete. Set Band Selects the operating band of the radio. All tuning values are reset to the factory defaults. CAUTION: Do not select this function because it can make the radio nonfunctional. Read Tune Parameters Selecting this function or clicking the button reads the tune parameters currently programmed in the transceiver and displays them in the various screens. NOTE: Values in the various screens are for reference only and adjustments should be done only by using the Partial Tune function. Write Tune Parameters Selecting this function or clicking the button writes the current tune parameters to the radio. This occurs automatically when a Partial Tune adjustment is completed. Tune Complete Currently not available. This function automatically steps through all the tests required to tune the radio. Tune Partial Selecting this function or clicking the button selects the Partial Tune mode. This mode automatically steps through all the adjustments of the currently selected Tune Category... TOOLS MENU Reset Passwords Erases all password information contained in the radio. This function can be used, for example, to allow reprogramming of passwords if they are lost. NOTE: Radio personality information is not erased by this function. Erase EEPROM CAUTION: This function erases important radio programming information as described below. Complete Erases all EEPROM information, including factory programmed parameters. CAUTION: Do not select this function because the radio must be returned to the factory to make it operational again. Parms Only Erases all personality information. NOTE: The radio must be reprogrammed after this function is selected. Tx/Rx Tests Selects a screen which is used to check digital (P) receive and transmit performance. Refer to Section. for more information. Restore Rx Front End Parameters Programs the radio with default receive front end tune parameters. Other parameters remain unchanged... HELP MENU Displays the version number of the PCTune software and other information.. TUNING PROCEDURE.. CONNECTING TEST SETUP Reset Radio Resets the radio control logic similar to cycling power. This can be used, for example, to. With transceiver power turned off, connect the 0 test cable to an unused serial port of the computer (see Section.). The 0 programming cable (see

54 ALIGNMENT PROCEDURE Section ) should not be used because it does not have the audio output jack.. Connect the other end of the test cable to the accessory (UDC) jack of the transceiver (see Figure ).. If the receiver squelch adjustment will be made, connect a SINAD meter to the Audio Out jack of the test cable (see Figure ). This is a. mm (/ ) mono phone jack. NOTE: The audio output signal at this jack is a singleended speakermicrophone signal and therefore at a lower level than the differential signal fed to a speakermicrophone. Refer to Audio Power Output and Distortion in Section.. for more information.. Connect a wattmeter and a suitable load to the antenna jack of the transceiver for the transmitter tests (an SMA to B adapter is listed in Section..). For the receiver tests, connect the signal generator to the antenna jack through a db or greater isolation pad... STARTING AND CONFIGURING PCTUNE. Start the program as described in Section.. and turn transceiver power on. Select Transfer > COM Port and make sure that the correct serial port and the 00 baud rate are selected (see Section..). To perform these tests, a Digital Communication Analyzer such as Motorola R0 or IFR is required. These tests follow the TIA0CAAAA Digital CFM/CQPSK Transceiver Measurement Methods specification. Refer to that document for more information. A P conventional channel preprogrammed by the PCConfigure software is used for testing. The PCTune software does not select a specific test channel. The test channel must be programmed with the following options: NAC (hex) TGID (Talk Group ID) Frequency Any frequency in radio operating band.. RECEIVE TEST SETUP. Connect the test setup and start and configure the PCTune software as described in Section.. Select the Tools > Tx/Rx Tests menu to display the Tx/Rx Tests screen. Then in the Test Type dropdown list select Receive to display the following screen.. Select the Radio menu and make sure the correct radio series (xx) is selected (see Section..).. Select Transfer > Partial Tune and click the button for the desired Test Category.. Follow the instructions displayed on the screen to complete the various adjustments required for a particular setting. Then repeat for other applicable Test Categories. (The Pendulum test sets the TCXO frequency.). DIGITAL PERFORMAE TESTS.. GENERAL This section describes how to check the performance of the radio on digital Project channels. The PCTune software includes a Tools > Tx/Rx Tests menu that displays the screen used for these tests.. Connect the Digital Communication Monitor to the antenna jack using a db or greater isolation pad. Set the Monitor output for the 0 test pattern... RECEIVE SENSITIVITY TEST. A tone should be heard from the radio speaker if the analyzer is set properly. Select the Short or Long test in the Test drop down list and the radio should mute.

55 ALIGNMENT PROCEDURE. Set the analyzer output level for 0. µv ( dbm) at the receiver antenna jack. The BER (Bit Error Rate) should be % or less. (This is a ratio of the receive bit errors to the total number of bits transmitted.). Increase the analyzer output level to 000 µv ( dbm). The BER rate should be less than 0.0%. This is the BER Rate Floor... TRANSMITTER TESTS. If applicable select the Tools > Tx/Rx Tests menu to display the Tx/Rx Tests screen. Then in the Test Type dropdown list select Transmit to display the following screen. Connect a dummy load to the radio antenna jack. Monitor the transmit signal with the Digital Communication Monitor. the receiving radio. This tone can also be used to test other radios.. Select Normal to transmit a standard voice signal by speaking into the radio microphone.. ANALOG PERFORMAE TESTS.. GENERAL The PCTune software is not used for analog channel performance testing. Simply program the desired channels using the PCConfigure software as described in Section. The test cable is still required to monitor the audio output signal from the radio. Depending on the application,. khz, khz, and (00 MHz) SPAC test channels may need to be programmed. Also, test channels programmed with or without Call Guard (CTCSS/DCS) squelch control may be required... RECEIVER PERFORMAE TESTS. Connect a signal generator to the antenna jack using a db or greater pad. Set the output for the channel frequency, modulated with khz at the following deviation:. Select the Low Deviation test and set the analyzer as required to measure transmitter deviation. This test generates continuous repetitions of bits Deviation should be 0 Hz.. Click the PTT button to transmit the tone. When finished, click that button again to turn the transmitter off.. Select the High Deviation test which transmits a standard transmitter test pattern. Deviation should be Hz.. The 0 Hz test transmits a standard 0 Hz tone similar to that used for the receiver test. This tone can be used to check the operation of other radios.. The Silence test transmits a standard silence test pattern which produces no receive audio output by. khz Channels. khz khz Channels.0 khz 00 MHz SPAC Channels. khz. Connect a ohm speaker load to the audio output jack of the test cable (see Figure ). Connect a SINAD meter across the speaker load. See Audio Power Output and Distortion which follows for more information. SINAD Sensitivity. Set the signal generator output level for 000 µv ( dbm) at the antenna jack. Adjust the radio volume control to mid range.. Decrease the signal generator output to obtain db SINAD. The signal generator output should be 0. µv ( dbm) or less for khz channels, or 0.0 µv ( dbm) or less for. khz channels.

56 ALIGNMENT PROCEDURE Squelch Sensitivity. Increase the signal generator output from zero and note the SINAD when unsquelching occurs. It should be approximately db. Audio Power Output and Distortion CAUTION: Test equipment connected across speaker leads must be floating because grounding either lead could damage the radio. This does not apply to the test cable audio jack (see following information). The internal speaker and external speakermicrophone are driven by separate audio amplifiers as follows: Internal Speaker The internal speaker does not have an external output. To measure the power and distortion of its amplifier, the meter must be connected across the speaker terminals (Extension Test Cable, Part No. 000, is then be required to operate the radio). This output is rated for 0. watt (. V rms) across a ohm load and distortion should be less than %. External SpeakerMic The external speakermicrophone amplifier outputs are pins and of the accessory connector. This output is rated for 0. watt (. V rms) across a ohm load. Test Cable Audio Jack This jack provides a single ended lowlevel audio output by tapping one of the external speakermic outputs. This allows the sleeve side of this jack to be connected to ground, but it does not provide the highlevel output required to check rated audio power output... TRANSMITTER PERFORMAE TESTS. Connect a wattmeter and dummy load to the antenna jack. Monitor the transmit signal with a communication monitor. Transmit Frequency. Monitor the transmit frequency and at room temperature it should ±00 Hz. At other temperatures ( 0 to 0 C), it must be within. PPM (VHF/UHF) or. PPM (00 MHz). This also checks the receive frequency. Transmit Power. Transmit power should be as follows in the high and low power modes: VHF Models W high, W low UHF Models W high, W low 00 MHz Mod..W high/ta, W low 00 MHz Models W std/.w TA high, W low Tolerance for all: 0W, 0.W high, ±0.W low Transmit Modulation. Monitor the transmit modulation with a modulation meter. Speak into the microphone with a normal voice. Modulation should be approximately as follows with no CTCSS/DCS signaling present:. khz Channels. khz khz Channels. khz 00 MHz SPAC Channels. khz. Select a channel programmed with Call Guard (CTCSS/DCS) signaling. Maximum total Call Guard and voice modulation should be approximately as follows:. khz Channels. khz khz Channels. khz 00 MHz SPAC Chan. khz

57 PARTS LIST SECTION PARTS LIST Ref No. Description Part No. CHASSIS, HARDWARE, MISC A 00 Rear housing assembly, std version Rear housing assembly, UCM ver 0000 includes CH 00, J 00 A 0 Battery contact assembly 000 A 00 Top switch assembly (includes EP0b, EP0, MP0, PC0, R0, S0) A 00 Front cover assembly (includes MP0, MP0, MP, MP, MP, MP, Limited keypad version Black standard 0000 Yellow standard 0000 Orange standard 0000 Black UCM models* 0000 Yellow UCM models* 0000 Orange UCM models* 0000 DTMF keypad version Black standard 0000 Yellow standard 0000 Orange standard 0000 Black UCM models* 0000 Yellow UCM models* 0000 Orange UCM models* 0000 A 00 Logic board assembly (see version info in Section.) EFJ SEM, Version C 0000 (see separate listing on page ) No module, Version A 0000 EFJ SEM, Version B 0000 Mot UCM, Version B 0000 (see separate listing on page ) Ref No. Description Part No. VHF MHz, Version B 0000 UHF 00 MHz, Version B 0000 UHF 00 MHz, Version B 0000 UHF 0 MHz, Version B MHz, Version B 0000 A 00 User interface (UI) board assembly (see version info in Section.) EFJ SEM, Version C 0000 (see separate listing on page ) No module, Version A 0000 EFJ SEM, Version B 0000 Mot UCM, Version B 0000 (see sep listing on page ) A 0 Backlight assembly, fiber optic 000 CH 00 Rear housing, metalized std See A 00 Rear housing, modified for UCM See A 00 DS 0 LCD assembly, x fsn EP 00 Flexible EMI gasket 0000 EP 0 Urethane foam, / x. x EP 0b Seal, top switch 000 EP 0 Seal, top switch 000 HW 0 Oring,.0 antenna connector 000 HW0 Nut, spanner M.h 000 (w/o HW0) Nut, spanner (w/ HW0) 000 HW 0 Nut, spanner M.h 000 HW 0 Screw, # plastite / 000 HW 0 Washer, nylon, volume control 00 J 00 Antenna connector, SMA press fit See A 00 A 00 RF module, complete w/flex, clip (see Section. for version info) VHF, Version C 0000 UHF 00 MHz, Version C 0000 UHF 0 MHz, Version C /00 MHz, Version C 0000 MK 0 Microphone cartridge 0000 MP 00 Accessory (UDC) jk water barrier 000 MP 00 Light pipe 00 MP 00 Light pipe sleeve 00 * Refer to Section. for UCM information.

58 PARTS LIST CHASSIS, HARDWARE, MISC (Cont d) LOGIC BOARD (VERSION C) Ref No. Description Part No. MP 00 RF shield, improved Ver A/B bds 0 RF shield, Version C RF boards 0 (see Section..) MP 0 Logic shield, nonucm versions 0 Logic shield, UCM versions 0 MP 0 RF shield insulator, upper 000 MP 0 Battery block comp spacer 000 MP 0 Logic shield gasket nonucm 000 Logic shield insulator, UCM only 000 MP 0 Gasket, rear housing 00 MP 00 Switch holder 00 MP 0 Bezel, limited keypad models 00 Bezel, DTMF keypad models 00 MP 0 Emergency button 00 MP 0 Selector ring, position switch 000 MP 0 Spacer, position switch 00 MP 0 Knob, select sw with Dclip hi ret 00 MP 0 Knob, volume with Dclip hi ret 00 MP 0 Water barrier, microphone 000 MP 0 Keypad, rubber for limited version 00 Keypad, rubber for DTMF ver. 00 MP Water barrier/foam ring, speaker 000 MP Foam ring, speaker See MP MP Speaker retention ring 0 MP Front lens attachment 000 MP LCD lens 00 MP Foam frame, lens 000 MP 0 Acsry jack (UDC) dust cover 00 MP 0 Foam frame, display backlight 000 MP 0 Optic locator,. x. x.0 thk Label, RF exposure caution Label, EFJ logo front Label, bottom for thru hole 000 PC 00 Flex circuit, access (UDC) conn PC 00 Flex circuit, top switch rev R 0 Volume/onoff switch revised 000 S 0 Select switch, pos/pos 000 SP 0 Speaker, mm ohm 000 RF BOARD (A00) Individual replacement parts are not available. Replace entire assembly. See A00. Ref No. Description Part No. LOGIC BOARD (A00) Part No (Version C, see Section.) C 00 0 pf ±0% V cer smd 000 C 00 0 pf ±0% V cer smd 000 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf 0V tantalum 0 C 0 0 µf 0V cer smd 00 C 0 µf ±0% XR V cer smd 00 C 0. µf V cer smd 0 C 00.0 µf V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 µf V tantalum smd 000 C 0 0 µf V tantalum smd 000 C 0. µf 0V tantalum 0 C 0 0 µf 0V cer smd 00 C 0. µf 0V tantalum 0 C 0 pf ±0% V cer smd 00 C 00 pf ±0% V cer smd 00 C 0 pf ±0% V cer smd 00 C 0 pf ±0% V cer smd 00

59 PARTS LIST LOGIC BOARD (VERSION C) Ref No. Description Part No. C 0 pf ±0% V cer smd 00 C 0 pf ±0% V cer smd 00 C 0 pf ±0% V cer smd 00 C 0 0 pf ±0% V cer smd 0 C 0 pf ±0% V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0 µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf 0V tantalum 0 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf 0V tantalum 0 C 0.0 µf ±0% 0V cer smd 00 C 0 µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C 0 pf ±0% V cer smd 000 C 0 pf ±0% V cer smd 000 C. µf 0/0% XR V cer smd 00 C. µf 0/0% XR V cer smd 00 C.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C. µf 0/0% XR V cer smd 00 C. µf 0/0% XR V cer smd 00 C. µf 0/0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 C. µf 0/0% XR V cer smd 00 C. µf 0/0% XR V cer smd 00 C. µf 0/0% XR V cer smd 00 C. µf 0/0% XR V cer smd 00 C 0. µf 0/0% XR V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C. µf 0/0% XR V cer smd 00 C 0 µf V tantalum smd 0000 CR 00 Dual diode, common anode 00 CR 00.V zener diode 0 Ref No. Description Part No. CR 00 Switching diode 000 CR 00.V zener diode 0 CR 00.V zener diode 0 J 00 Connector, pin ZIF 0.mm J 00 Connector, 0pin bd to bd 0 J 00 Spring clip 000 J 00 Spring clip 000 L 00 0 µh smd inductor 0000 L 00 0 µh smd inductor 0000 L 00 0 nh smd inductor 0 L 00 0 nh smd inductor 0 L 00 0 nh smd inductor 0 L 0 µh.a smd inductor 000 L 0 0 nh smd inductor 0 L 0 0 nh smd inductor 0 L 0 0 nh smd inductor 0 L 0 0 µh smd inductor 0000 PC 00 PC board, 00 logic rev 0000 Q 00 Power MOSFET pair 0 volt 000 Q 00 General purpose Q 00 Power MOSFET pair 0 volt 000 R 00 00k ohm ±% /W smd 00 R 00 0k ohm ±% /W smd 00 R 00 0k ohm ±% /W smd 00 R 00 00k ohm ±% /W smd 00 R 00 00k ohm ±% /W smd 00 R 00 0 ohm jumper 000 R 00 0 ohm jumper 000 R 00 0 ohm jumper 000 R 00 0 ohm jumper 000 R 00 0 ohm jumper 000 R 0 k ohm ±% /W smd 00 R 00 k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0

60 PARTS LIST LOGIC BOARD (VERSION C) Ref No. Description Part No. R 0.k ohm ±% /W smd 0 R 00.k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 00.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 00.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 00 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0 ohm jumper 000 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0 ohm ±% /W smd 000 R 0 00 ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 00 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 Ref No. Description Part No. R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 00 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 0 R k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0 ohm ±% /W smd 000

61 PARTS LIST LOGIC BOARD (VERSION C) Ref No. Description Part No. R 0 ohm ±% /W smd 000 R 0 ohm ±% /W smd 000 R 0 ohm ±% /W smd 000 R 0 ohm ±% /W smd 000 R 0 0 ohm ±% /W smd 000 R 0 ohm ±% /W smd 000 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 U 00 Op amp, quad OPA0 000 U 00 Analog switch, SPDT NLAS 0000 U 0 Regulator, V 00 ma REGEA 00 U 0 Regulator,.V, 0 ma LP 00 U 0 DSP TMS00AGGWA 00 U 0 Analog switch, SPDT NLAS 0000 U 0 Analog switch, SPDT NLAS 0000 U 0 Regulator, V 00 ma REGEA 00 U 0 Schmitt trig, inv TCSFTEL 0 U 00 Programmable logic 000 U 0 D flipflop, single SP 000 U 0 SEM encryption module U 0 Op amp, quad OPA0 00 U 0 CODEC bit TLV0AIC 00 U 0 Regulator, adj 00mA REG0UA 00 U 0 Regulator, adj 00mA REG0UA 00 U 0 Regulator,.V 00m REGEA 00 U 0 Converter, step down TPS0 000 U 0 Converter, step down TPS0 000 U 0 Converter, step down TPS Y 00 Oscillator, MHz SMD 0000 Y 00 TCXO. MHz 000 LOGIC BOARD (A00) Part No (early w/o module) Part No (for EFJ SEM) Part No (for Mot UCM) (Version A and B, see Section.) A 0 SEM encryption module (0 EFJ SEM bd only) UCM encrpt module NNTNA 000 (0 UCM bd only) C 00.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 LOGIC BOARD (VERSION A/B) Ref No. Description Part No. C 00.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00. µf V cer smd 00 (All except 0 bd).0 µf ±0% XR V cer smd 00 (0 bd only) C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0 0 pf ±0% V cer smd 0 C 0. µf ±0% XR V cer smd 00 C 0. pf ±. pf O cer smd 0 C 0. pf ±.pf O cer smd 0 C 0 0 pf ±.pf O cer smd 000 C 0 0 pf ±0% V cer smd 0 C 0. pf ±0% V cer smd 0 C 00.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00

62 PARTS LIST LOGIC BOARD (VERSION A/B) Ref No. Description Part No. C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.pF /.pf O cer smd 0 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf V cer smd 0 C 0 0 µf 0V cer smd 00 C 0 0 µf 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf V cer smd 0 C 00.0 µf V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 µf V tantalum smd 000 C 0 0 µf V tantalum smd 000 C 0 0 µf 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0 0 pf ±0% V cer smd 0 C 00 0 pf ±0% V cer smd 0 C 0 0 pf ±0% V cer smd 0 C 0 0 pf ±0% V cer smd 0 C 0 0 pf ±0% V cer smd 0 C 0 pf ±0% V cer smd 00 C 0 pf ±0% V cer smd 00 C 0 0 pf ±0% V cer smd 0 C 0 0 pf ±0% V cer smd 0 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 µf 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf V cer smd 0 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0 0 pf ±. pf O cer smd 000 Ref No. Description Part No. C 0 0 pf ±. pf O cer smd 000 CR 00 Dual diode, common anode 00 CR 00.V zener diode 0 CR 00 Switching diode 000 CR 00.V zener diode 0 CR 00.V zener diode 0 D 00 PIN diode 000 J 00 Connector, 0pin ZIF. mm 0 J 00 Connector, 0pin bd to bd 0 (all except 0 bd) Connector, 0pin bd to bd (0 bd only) J 00 Spring clip 000 J 00 Spring clip 000 J 0 Socket, pin (0 bd only) 0 L 00. µh smd inductor 0 L 00 0 µh smd power inductor 0000 L 00 0 µh smd power inductor 0000 L 00 0 nh smd inductor 0 L 00 0 nh smd inductor 0 L 00 0 nh smd inductor 0 L 00 0 nh smd inductor 0 L 00 0 nh smd inductor 0 L 00 0 nh smd inductor 0 L 0 Ferrite bead 000 PC 00 PC board, 0 rev PC board, 0 EFJ SEM rev 0000 PC board, 0 Mot UCM rev 0000 Q 00 Power MOSFET pair 0 volt 000 Q 00 General purpose Q 00 Power MOSFET pair 0 volt 000 Q 00 N general purpose 000 R 00 0k ohm ±% /W smd 00 R 00.k ohm ±% /W smd 0 R 00.k ohm ±% /W smd 0 R 00.k ohm ±% /W smd 0 R ohm ±% /W smd 00 R 00 00k ohm ±% /W smd 00 R 00 00k ohm ±% /W smd 00

63 PARTS LIST LOGIC BOARD (VERSION A/B) Ref No. Description Part No. R 00 00k ohm ±% /W smd 00 R 00 0k ohm ±% /W smd 0 R 00 0k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 0 ohm smd jumper 000 R 0 M ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 00 ohm ±% /W smd 00 (all except 0 bd) 0k ohm ±% /W smd 00 (0 bd only) R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 (all except 0 bd) k ohm ±% /W smd 00 (0 bd only) R ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 (all except 0 bd) 0k ohm ±% /W smd 00 (0 bd only) R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 Ref No. Description Part No. R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 00 ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 00 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 00 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 00.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0 0 ohm ±% /W smd 000 R 0 00 ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 (0 board) k ohm ±% /W smd 0 (0 EFJ SEM board) R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 00 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00

64 PARTS LIST LOGIC BOARD (VERSION A/B) Ref No. Description Part No. R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 U 00 DSP TI TMS0VC 00 U 00 ADSIC 0000 U 00 bit transceiver LVTH 00 U 00 Transceiver, state ACT 00 U 00 state buffer, quad ACT U 00 state buffer ACT U 00 Programmable logic 00 U 00 Op amp, quad OPA0 000 U 00 Analog switch, SPDT NLAS 0000 U 00 Op amp, dual OPA0 00 U 0 Regulator, V 00 ma REGEA 00 U 0 DCDC converter TPS U 0 Regulator,.V, 0 ma LP 00 U 0 DCDC converter TPS U 0 Analog switch, SPDT NLAS 0000 U 0 Analog switch, SPDT NLAS 0000 U 0 Regulator, V 00 ma REGEA 00 U 0 Bus xcvr, octal LVCC 000 U 00 Bus xcvr, octal LVCC 000 U 0 Tri state buffer,.v SZP U 0 state buffer, quad ACT U 0 Reg, dual./.v TPS0 00 U 0 Prog logic array CPLD 0 00 U 0 Schmitt trig, inv TCSFTEL 0 U 0 Regulator, V 00 ma REGEA 00 Y MHz crystal USER INTERFACE BOARD (A00) Part No (Version C, see Section.) C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 USER INTERFACE BOARD (VERSION C) Ref No. Description Part No. C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 µf 0V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0 00 pf ±0% 0V cer smd 0 C 0 pf 0V cer smd 00 C 0 pf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 pf ±0% XR V cer smd 0 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0.00 µf ±0% XRF 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00

65 PARTS LIST USER INTERFACE BOARD (VERSION C) Ref No. Description Part No. C 0. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0 pf ±% O cer smd 00 C 0 pf ±% O cer smd 00 C 0. µf 0V tantalum 00 C 0. µf 0V tantalum 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 pf ±0% XR V cer smd 0 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 pf ±0% O V cer smd 0 C 00.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf 0/0% XR V cer smd 00 C 0. µf 0/0% XR V cer smd 00 C 0. µf 0/0% XR V cer smd 00 C 0. µf 0/0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf 0/0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0 0 pf ±% O cer smd 0 C 0.00 µf ±0% V cer smd 00 C 0.0 µf V cer smd 00 C 0.0 µf V cer smd 00 Ref No. Description Part No. C 0.0 µf V cer smd 00 C 0.0 µf V cer smd 00 C 0.0 µf V cer smd 00 C 0. µf V cer smd 0 C 0. µf V cer smd 0 C 0. µf V cer smd 0 C. µf V cer smd 0 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.00 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C 0 pf ±% O V cer smd 0 C. µf ±0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 C.0 µf ±0% 0V cer smd 00 C 00 pf ±0% V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 00 pf ±0% V cer smd 00 C 00 pf ±0% V cer smd 00 C 00 pf ±0% V cer smd 00 C 00 pf ±0% V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.00 µf ±0% V cer smd 00 CR 00.V zener diode 0 CR 00.V zener diode 0 CR 00.V zener diode 0 CR 00.V zener diode 0 CR 00 LED, dual color red/green 00 CR 0 Dual diode, common cathode 00 CR 0 LED, green high intensity 000 CR 0 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 00 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000

66 PARTS LIST USER INTERFACE BOARD (VERSION C) Ref No. Description Part No. CR 0 LED, green RG0 smd 000 CR 0.V zener diode 0 DS 0 See DS0 on page J 00 Connector, pin ZIF. mm J 00 Connector, pin ZIF. mm J 00 Connector, pin ZIF. mm J 00 Connector, pin ZIF mm J 00 Connector, 0pin bd to bd J 00 Ground clip 000 J 00 Spring clip 000 J 00 Spring clip 000 L 00. µh ±% chip inductor 000 L 00. µh smd inductor 00 L 00. µh smd inductor 00 PC 00 PC board, user interface rev Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 0 General purpose Q 0 General purpose R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 k ohm ±% /W smd 00 R 00 0M ohm ±% /W smd 00 R 00 0 ohm jumper 000 R 00 0k ohm ±% /W smd 0 R 00 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 Ref No. Description Part No. R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 00.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 00 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 00 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 00 0k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 ohm ±% /W smd 000 R 00 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 0

67 PARTS LIST USER INTERFACE BOARD (VERSION C) Ref No. Description Part No. R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 M ohm ±% /W smd 00 R ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 0 ohm jumper 000 R 0 0k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 00 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 00 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 00 k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 Ref No. Description Part No. R 0 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R.k ohm ±% /W smd 0 R.k ohm ±% /W smd 0 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0

68 PARTS LIST USER INTERFACE BOARD (VERSION C) Ref No. Description Part No. R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R.k ohm ±% /W smd 0 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 0 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R ohm ±% /W smd 000 R ohm ±% /W smd 000 R 0 ohm ±% /W smd 000 R 00k ohm ±% /W smd 00 R k ohm ±% /W smd 0 R 00k ohm ±% /W smd 00 R.k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R.k ohm ±% /W smd 0 R 0 ohm smd jumper 000 R 0 ohm smd jumper 000 R 00k ohm ±% /W smd 00 R 0 ohm ±% /W smd 000 R.k ohm ±% /W smd 0 U 00 Microcontroller PowerPC MPC0 00 U 00 A/D converter, 0 bit LTC 000 U 00 Flash M x AMDL0G0 00 U 00 Prog logic XCCCP 000 U 00 SRAM M x CYDV0L 0 U 00 D/A converter, bit TLV 00 U 00 Audio amp, 0 mw LM 000 USER INTERFACE BOARD (VERSION A/B) Ref No. Description Part No. U 00 A/D converter, 0 bit LTC 000 U 00 Op amp, quad OPA0 000 U 0 Buffer, quad LCX U 0 Programmable logic 00 U 0 AND gate, input TCS0FU 00 U 0 Op amp, quad OPA0 000 U 0 EEPROM k x M 0 U 0 Op amp, quad OPA0 000 U 0 Op amp, quad OPA0 000 U 0 Op amp, quad OPA0 000 U 00 Op amp, quad OPA0 000 U 0 Audio amp, 0 mw LM 000 U 0 Buffer, state.v U 0 Analog switch, SPDT NLAS 0000 U 0 Triple supply monitor LT 00 U 0 Buffer, state.v U 0 Diff comparator, dual TLCD 00 U 0 RS bus xcvr MAXEAE 00 Y 00 Crystal,. MHz 000 Y 00 Osc, khz to 0 MHz resistor set 000 USER INTERFACE BOARD (A00) Part No (early w/o module) Part No (for EFJ SEM) Part No (for Mot UCM) (Version A and B, see Section.) EP 0a Grounding finger 000 EP 0 Grounding finger 000 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0 00 pf ±0% V cer smd 00

69 PARTS LIST USER INTERFACE BOARD (VERSION A/B) Ref No. Description Part No. C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 µf 0V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0 00 pf ±0% 0V cer smd 0 C 0 pf 0V cer smd 00 C 0 pf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 pf ±0% XR V cer smd 0 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0.00 µf ±0% XRF 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 Ref No. Description Part No. C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0 00 pf ±0% V cer smd 00 C 0. µf 0V tantalum 0 C 0. µf 0V tantalum 0 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00. µf ±0% XR V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 pf ±0% XR V cer smd 0 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0 0 pf ±0% O V cer smd 0 C 00.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00 C 0. µf ±0% XR V cer smd 00 C 00.0 µf ±0% 0V cer smd 00 C 0 0 pf ±% O cer smd 0 C 0.0 µf V cer smd 00 C 0.0 µf V cer smd 00 C 0.0 µf V cer smd 00 C 0.0 µf V cer smd 00 C 0.0 µf V cer smd 00 C 0. µf V cer smd 0 C 0. µf V cer smd 0 C 0. µf V cer smd 0 C. µf V cer smd 0 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C 0.0 µf ±0% 0V cer smd 00

70 PARTS LIST USER INTERFACE BOARD (VERSION A/B) Ref No. Description Part No. C.0 µf ±0% 0V cer smd 00 C.00 µf ±0% 0V cer smd 00 C.0 µf ±0% 0V cer smd 00 C 0 pf ±% O V cer smd 0 C. µf ±0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 C. µf ±0% XR V cer smd 00 CR 00.V zener diode 0 CR 00.V zener diode 0 CR 00.V zener diode 0 CR 00.V zener diode 0 CR 00 LED, dual color red/green 00 CR 0 Dual diode, common cathode 00 CR 0 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 00 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 0 LED, green RG0 smd 000 CR 0.V zener diode 0 CR 0.V zener diode 0 CR 0.V zener diode 0 CR 0.V zener diode 0 EP00 Grounding clip 0000 J 00 Connector, pin ZIF. mm J 00 Connector, pin ZIF. mm J 00 Connector, pin ZIF. mm J 00 Connector, pin ZIF mm J 00 Connector, 0pin bd to bd (all except 0 bd) Connector, 0pin bd to bd (0 bd only) J 00 Spring clip 000 J 00 Spring clip 000 L 00. µh ±% chip inductor 000 L 00. µh smd inductor 00 L 00. µh smd inductor 00 L L 0 Ferrite smd inductor 00 Ref No. Description Part No. PC 00 PC board, user interface rev 0 (0 bd) PC board, user interface revision (0 EFJ SEM board) PC board, user interface revision (0 UCM board) Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 00 General purpose Q 0 General purpose Q 0 General purpose R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 0 ohm ±% /W smd 000 R 00 k ohm ±% /W smd 00 R 00 0M ohm ±% /W smd 00 R 00 0k ohm ±% /W smd 0 R 00 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 00.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 k ohm ±% /W smd 00

71 PARTS LIST USER INTERFACE BOARD (VERSION A/B) Ref No. Description Part No. R 0.k ohm ±% /W smd 0 R 00 k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 00 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 00 0k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 ohm ±% /W smd 000 R 00 k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 M ohm ±% /W smd 00 R ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0.k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 00 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 Ref No. Description Part No. R 0 00k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 0 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 00 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R.k ohm ±% /W smd 0 R k ohm ±% /W smd 0 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 0 00k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0

72 PARTS LIST USER INTERFACE BOARD (VERSION A/B) Ref No. Description Part No. R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R 0k ohm ±% /W smd 00 R 0 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R 00k ohm ±% /W smd 00 R ohm ±% /W smd 00 R 0 k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R k ohm ±% /W smd 00 R 0k ohm ±% /W smd 00 R 0k ohm ±% /W smd 0 R 00k ohm ±% /W smd 00 Ref No. Description Part No. R 00k ohm ±% /W smd 00 R ohm ±% /W smd 000 R ohm ±% /W smd 000 R 0 ohm ±% /W smd 000 R 00k ohm ±% /W smd 00 R k ohm ±% /W smd 0 R 00k ohm ±% /W smd 00 R.k ohm ±% /W smd 0 R 0k ohm ±% /W smd 0 R 0 ohm jumper 000 R 0k ohm ±% /W smd 0 R 0k ohm ±% /W smd 00 R 0 ohm ±% /W smd 0 R 0 ohm ±% /W smd 0 R k ohm ±% /W smd 0 U 00 Microcontroller PowerPC MPC0 00 U 00 SRAM k x CYV 00 U 00 Flash M x.0v 00 U 00 SRAM k x CYCV0 00 U 00 D/A converter, bit TLV 00 U 00 Audio amp, 0 mw LM 000 U 00 A/D converter, 0 bit LTC 000 U 00 Op amp, dual OPA0 00 U 0 Buffer, quad LCX U 0 Programmable logic 00 U 0 EEPROM k x M 0 U 0 Op amp, quad OPA0 000 U 0 Op amp, quad OPA0 000 U 0 Op amp, quad OPA0 000 U 00 Op amp, quad OPA0 000 U 0 Audio amp, 0 mw LM 000 U 0 Analog switch, SPDT NLAS 0000 U 0 Triple supply monitor LT 00 U 0 Serial bus USB xcvr USBTAM 0 U 0 Buffer, state.v U 0 Diff comparator, dual TLCD 00 U 0 RS bus xcvr MAXEAE 00 Y 00 Crystal,. MHz 000 Y 00 Osc, khz to 0 MHz resistor set 000

73 PARTS LIST EXPLODED VIEWS MP0 MP0 MP00 MP0 MP0 HW0 A00 MP00 MP0 PC00 MP00 HW0 MP MP MP 0 MP0 MP0 A00 (Complete Assembly) MP Front Cover Assembly

74 PARTS LIST EP0b EP0 MP0 R0 S0 PC00 MP00 Top Switch Assembly HW0 J00 CH00 MP0 A0 Rear Housing Assembly

75 PARTS LIST A00/A00 DS0 MP0 A00 Short Lead on Top A0 J/J W0 ( Case) W0 () MK0 MP0 SP0 0 HW0 MP W0/W0 EP0 MP

76 PARTS LIST MP0 A00 MP00 Part of A00 Part of A00 MP0 EP00 () J MP0 MP0 EP0 A00 J A00 0

77 SECTION SCHEMATIC DIAGRAMS AND COMPONENT LAYOUTS J0 Antenna Jack.V Battery Pack B J RF Input/ Output P B P Bat Status P A00 RF BOARD RF_CLK RF_DAT RF_FS LOCK_ENA ADDR ADDR SPI_ENA SPI_CLK SPI_MOSI SPI_MISO PLL_LOCK.V.V UNSW_BAT TX_NAP TEMP nt/r TX_MOD TX_MOD UNSW_BAT Flex Cir J A00 LOGIC BOARD RF_CLK_CPLD HCNTL0 HCNTL RF_DATA_CPLD SCD RF_FS_CPLD TEMP SYNTH_EN IB_D0 SPI_ADDR_ SPI_ADDR_ SCL RF_SPI_ENA SW_VA_0 SPICLK IB_D MOSI MISO SYNTH_LOCK nhrdy RF_SW_V_D IB_D SW_V_RF UNSW_BAT AUDIO_OUT_P IB_D ntxnap TEMP nt/r TXMOD TXMOD UNSW_BAT AUDIO_OUT_M IB_D AUDIO_IN_M IB_D AUDIO_IN_P IB_D SW_BATT UNSW_VD_ IB_D SPICLK MISO H_R/nW MOSI HDS FIPS_CS SYNTH_EN ON_OFF_SW SPI_ADDR_ nt/r LOGBRD_nRST ntxnap FIPS IRQ RX_AUDIO_MUTE HDS SW_VD_0 H_nCS SPI_ADDR_ SYNTH_LOCK RF_SPI_ENA nhreset nhint POWER_HOLD SW_VD_ MK0 Microphone SP0 Speaker J J MIC MIC Ext Spkr Ext Spkr A00 USER INTERFACE (UI) BOARD HCNTL0 HCNTL SCD TEMP IB_D0 SCL SW_VA_0 IB_D nhrdy IB_D AUDIO_OUT_P IB_D AUDIO_OUT_M IB_D AUDIO_IN_M IB_D AUDIO_IN_P IB_D SW_BATT UNSW_VD_ IB_D SPICLK MISO H_R/nW MOSI HDS FIPS_CS SYNTH_EN ON_OFF_SW SPI_ADDR_ nt/r LOGBRD_nRST ntxnap FIPS IRQ RX_AUDIO_MUTE HDS SW_VD_0 H_nCS SPI_ADDR_ SYNTH_LOCK RF_SPI_ENA nhreset nhint POWER_HOLD SW_VD_ OPT_SEL EXTSPKR_P EXT_MIC SW_BATT OPT_SEL EXTSPKR_M RX_DATA TX_DATA Unused Keyfill EMER CHNL_ CHNL_0 CHNL_ SW_VD_ ON_OFF_SW TOG_ CHNL_ Volume Control TOG_0 PTT Aux Aux Aux DSD DSD0 DSCK nhreset nsreset IP_B0 IP_B SW_VD_ LCD_ LCD_ LCD_ SPICLK MOSI SW_VD_ J 0 J 0 J 0 J 0 PC0 UDC Flex Circuit PC0 Top Flex Circuit PTT Flex Circuit Volume Pot R0 Opt Sel Ext Spkr Ext Mic Sw B Opt Sel Ext Spkr Rx Data D Tx Data Unused Keyfill DS0 DISPLAY (LCD) OnOff Sw 0 UDC (ACCESSORY) CONNECTOR A B SW Emergency Sw S0 Rotary Channel/Toggle Sw SW PTT Sw SW Opt Sw SW Opt Sw SW Opt Sw C C C For Version C Boards (see Section.) INTERCONNECT SCHEMATIC (FOR VERSION C)

78 J0 Antenna Jack.V Battery Pack B J RF Input/ Output J B Bat Status A RF BOARD D Out D Out* SB Reset Bat Status ODC DA CE SPI Clk SPI Data Ref Osc En Synth CE Lock Detect Mod In Unsw B Sw B Unsw B 0 0 PC0 Flex Cir J 0 0 A00 LOGIC BOARD D Out D Out* SB Reset Bat Status ODC DA CE SPI Clk SPI Data Ref Osc En Synth CE Lock Detect Mod In Unsw B Sw B Unsw B HCNTL0 HCNTL HBIL HPI_D SW_VA_0 HPI_D HRDY HPI_D AUDIO_OUT_P HPI_D AUDIO_OUT_M HPI_D AUDIO_IN_M HPI_D0 AUDIO_IN_P HPI_D SW_BATT UNSW_VD_ HPI_D SPICLK H_R/nW MOSI HDS nsynsel ON_OFF_SW ndacsel ISW_IRQ LOGBRD_nRST RX_AUDIO_MUTE HDS SW_VD_0 H_nCS nroscsel ADSIC_nSEL RF_nLOCK RFSPIEN nhreset HINT POWER_HOLD SW_VD_ MK0 Microphone SP0 Speaker J J A00 USER INTERFACE (UI) BOARD EB_A EB_A0 EB_A EB_D SW_VA_0 EB_D EB_WAIT EB_D AUDIO_OUT_P EB_D AUDIO_OUT_M EB_D AUDIO_IN_M EB_D0 AUDIO_IN_P EB_D SW_BATT UNSW_VD_ EB_D SPICLK EB_R/nW MOSI EB_nOE GPIO_ ON_OFF_SW GPIO_ ISW_IRQ GPIO_ GPIO_ EB_WE0 SW_VD_0 EB_CS GPIO_ GPIO_0 nlock_n RFSPIEN nhreset DSP_HINT POWER_HOLD SW_VD_ MIC MIC Ext Spkr Ext Spkr OPT_SEL EXTSPKR_P EXT_MIC SW_BATT OPT_SEL EXTSPKR_M RX_DATA TX_DATA E_RCLK E_TCLK TENA RENA E_RXD E_TXD EMER CHNL_ CHNL_0 CHNL_ SW_VD_ ON_OFF_SW TOG_ CHNL_ Volume Control TOG_0 PTT Aux Aux Aux TP TP0 TP TP0 TP TP TP SW_VD_ GPIO_ GPIO_ GPIO_ SPICLK MOSI SW_VD_ J 0 J 0 J J 0 0 PC0 UDC Flex Circuit PC0 Top Flex Circuit PTT Flex Circuit Volume Pot R0 Opt Sel Ext Spkr Ext Mic Sw B Opt Sel Ext Spkr Rx Data D Tx Data E_RCLK E_TCLK TENA RENA DS0 DISPLAY (LCD) OnOff Sw 0 UDC (ACCESSORY) CONNECTOR A B SW Emergency Sw S0 Rotary Channel/Toggle Sw SW PTT Sw SW Opt Sw SW Opt Sw SW Opt Sw C C C For Version A and B Boards (see Section.) INTERCONNECT SCHEMATIC (FOR VERSION A/B)

79 E VR IF FILTER R 0 C.uf SHIELDIF LRG C C0 C L E R K R 0.0uf U 0nH 00 IF FROM PG C pf C pf L 0nH % 00 U G V IN G V OUT DSF C L IN OUT C L Q C 0pf L 00 C0 0nH % 0pf DSF L L 00pf 00 nh.0uf R C 00 0nH % C K 00 0pf 00 V G V G SHIELDIF SM E C C 000pf R 0 SHIELDBACKEND.V.V C uf U nshtdn IN OUT BYP ILC0AIMx.0uf C C.uf L.VXR VCO C.uf L C0.0uf U nshtdn OUT IN BYP ILC0AIMx.V C uf C uf U nshtdn IN OUT BYP ILC0AIM0x C.0uf VR C.uf L TP TestPoint C 00pf R L 0uH 0 C L0 0uH 0 C0.0uf C.0uf C0.0uf FB FB C0.0uf.V C 0uf C0 C.0uf C0.0uf C0.0uf C.0uf DEMOD TP TP C 00pf SHIELDED AREA C.0uf C 000pf VR R 0 C 00pf 0 TP C.uf.uf TP R K C 000pf R K 0uf C.nf TP0 TestPoint C.0uf C 00pf C 00pf C 00pf R 00K C 00pf SPI_CLK SPI_MOSI RXBE_CS VCO MXOP IFIN MXON CXIF IFN CXVL FP U LOP GPC LON GCN CXVM VREFP AD VREFN IOUTL VREF IOUTC FREF CLKP SYB 0 CLKN FS 0 PC DOUTB PD DOUTA PE CLKOUT G VDD VDD VDD VDD VDD VDD VDD VDD VDD 0 R C.0uf C0 000pf R 00 R 0 R 0 R0 0 RF_FS RF_DAT TP C0.0uf R.K C.uf R K LO_RF R K C0 000pf C00 0pf D MV0 C0 pf L 0nH 00 R K C pf C pf C pf Q R K TP R C L R0.K 0 RF_CLK SHIELDED AREA 00 pf 0uH 0 C C C C0.uf NOTE: Individual replacement Parts are not available for the RF board, so the entire board must be replaced if it is defective..mhz VHF RF BOARD SCHEMATIC VER C (PAGE OF )

80 EPROM DAC MUX N/C ncs SPI_CLK SPI_MOSI natten ADDR RF_CLK RF_DAT RF_FS ADDR SPI_ENA SPI_CLK SPI_MISO SPI_MOSI RX_PLL_LOCK nt/r TX_MOD TX_MOD SPI_MISO TEMP PWR_CTL LOCK_ENA ntx_nap ADDR ADDR PLL_CS SPI_ENA RXBE_CS PLL_CS TX_PLL_LOCK ATTEN.V.V.V UNSW_BAT UNSW_BAT VR.V.V.V UNSW_BAT J CON 0 0 CP pf CP pf TP TP R 0K U AT00 CS Q WP D CLK HOLD VCC TP TestPoint R 0K TP P STPAD C pf C.0uF TP0 U HC 0 Y0 Y Y Y Y Y Y Y A B C GB GA G VCC P STPAD U VG P STPAD RP K CP pf TP C.uf P PAD C.0uF FB FB0SO TP CP pf P STPAD C.0uf P PAD R 0K TP C00.0uF P STPAD TP F FUSE00 P PAD TP U AD0 0 VCC VoutA VoutC VoutB SCLK nsy DIN REFabcd VoutD VoutE VoutF VoutG VoutH REFefgh LDAC RP K VHF RF BOARD SCHEMATIC VER C (PAGE OF )

81 PLL VCO PLL TX_MOD SPI_MOSI TX_MOD SPI_CLK RX_PLL_LOCK PLL_CS.MHz LOCK_ENA T/nR RX_LO TX_LO nt/r nt/r.v VA VA.V.V VA.V VA.V.VXR FB FB C.uF C.0uf C.uf C 00pf R 00 R 0 R U RF RFIN VDP RFOUT G G C.uF L C.uF R L nh C pf R K C 0pf C.00uf L0 00nH C 000pF C0.uf FB FB C 000pf U CX0 0 0 CLK MOD_IN MUXOUT VSUBD cm VCCcm FVCO nfvco LD/PS VCCcp CPOUT cp XTALG XTALIN XTALO VCCx x LD/PSa VCCca CPout cp nfvcoa FVCOa VCCcm d VCCd DATA ncs G C 00pf R 0 C.0uf C.uf R 0 C0 pf R 00 TP C uf C 00pf R 00 C 0uf U LTES IN OUT BYP nshtdn C 000pf U AS J J V J V C 0pf C.uf R0 0 R 0 C.uF C.0uF C.uf C 0pf C0 0pf FB FB TP C 0pf C 00pf R0 0K C.uF R 0 C0 00pf C uf C 000pf C 000pf R 0 C pf U ILC0AIM0x IN OUT BYP nshtdn C.uf R 00K C 00pf C0.uf E SHIELDPLL C 000pf R K C.uf R0 0 R 0 R K TP TestPoint Y VTX0C..0 Vcc Out Vtune G U ADG S S IN V G D C.uF R K U VCOD RF_o V IN G R 0 C 00pf C 000pF C 00pf VHF RF BOARD SCHEMATIC VER C (PAGE OF )

82 .V R 0K.V U0 SWV C uf D0 SI ntx_nap C0 uf nshtdn IN OUT BYP ILC0AIM0x C.0uF C.uF L C.0uf R 0 C 0pF C 00pf L 0nH Q N00 UNSW_BAT R. TX_RF FROM PG R R 0 dbm R C 00pF U0 SGA dbm C 00pF R0 0 R R FB FB0SO.V J db db dbm TP FB FB0SO C.uf V C pf C 00pf R 0 C C.V U VCC VOUT LM0/SOT TEMP C.0uf U RFin Vgg POWER AMP Vdd RFout C 00pf L C 00pf D MAP00 L 0nH L 0nH 00pf D MAP00 L 0nH C 00pf C 00pf L TO PG RX_IN SWV C C UB LM SWV SWV C 00pf R00 0 R0 0 00pf UNSW_BAT.0uf TP C U C 00pf R0 0k R0 0k SWV R 0K C.0uf SREF VPOS VRMS IREF FLTR RFIN COMM PWDN AD TP C 00pf R 0 R0.k Q N00 C Q N00 R0.k nt/r 00pf Q N00 R K UA LM C R 0 PWR_CTL R.K R M C0.0uf.uf.V C.0uF U VG.V T/nR C0 C.pf L.pf L L L L nh 00 nh 00 nh 00 C C C C R K J ANTENNA pf L pf L pf L.pf L nt/r E SHIELD SHIELDHARMONIC VHF RF BOARD SCHEMATIC VER C (PAGE OF )

83 R ntx_nap K.VXR natten R0 0 C D SI ATTEN R pf C R 0 000pf FROM PG RX_IN MHz C pf L L C W=, S=, N=. C L C pf L C V RF RF V C 00pf U AT C 00pf W=0, L=0 L W=0, L=0 U LNA MGA IN OUT W=0, L=0 L.0uf C 00pf C0 W=0, L=0 L nh C MHz C0 pf L L0 W=, S=, N=. C C L C pf L 0nH 00.pf L.pf L 0nH 00pf nh nh 00pf 0nH 0nH.pf L.pf L G G W=, S=, N=. C pf L W=, S=, N=. L C0 C W=, S=, N=. C pf L W=, S=, N=. nh 00pf 00pf C0 C C 00pf R 0 00pf 00pf R 0 C 00pf R TP TP U MX natten R R C S D G G D S FDG0ALT R C R 0 R R G LO G G RF IF ADEX0L R R0 0 R C IF TO PG R R TP R 0 R RX_LO L C C L FROM LO BUFFER nh.pf.pf nh R0 C 0nH pf 00 L 00 R C VHF RF BOARD SCHEMATIC VER C (PAGE OF )

84 PLL VCO SPI_CLK PLL_CS TX_MOD TX_MOD SPI_MOSI TX_PLL_LOCK TX_LO T/nR T/nR TX_RF.V.V.V VA VA.VXR FB FB C 00pf C0 uf C 00pf L nh TP L nh C 00pf C0.00uf R K C.0uf R 0 C0 0pf R K C0 000pf R 0 FB0 FB U VCOD RF_o V IN G R K C0 00pf C.pf Y VTX0C..0 Vcc Out Vtune G C00 00pf C 0pf C 00pf R R 0 R0 0K C 00pf C0.uf C0 000pF C0.uF R 0 C0.uf C pf C.uF R C.uf U MAX LO nshdn VCC IFIN RFOUT C 0uf R 0 C.uf R 0 TP C 00pf C 000pf C.uF R 00 C.pf L nh C0.0uf R0 C.pf C.pf R 0 L 0nH U LTES IN OUT BYP nshtdn C0.0uf FB FB C0.uf R C 0pf R0 0 C 00pf C.pf C.uF U CX0 0 0 CLK MOD_IN MUXOUT VSUBD cm VCCcm FVCO nfvco LD/PS VCCcp CPOUT cp XTALG XTALIN XTALO VCCx x LD/PSa VCCca CPout cp nfvcoa FVCOa VCCcm d VCCd DATA ncs C.uF VHF RF BOARD SCHEMATIC VER C (PAGE OF )

85 Version C Board (see Section.) VHF RF BOARD VER C LAYOUT

86 NOTE: Individual replacement parts are not available for the RF board, so the entire board must be replaced if it is defective. VHF RF BOARD SCHEMATIC VER B (PAGE OF ) Version B Board (see Section.) 0

87 VHF RF BOARD SCHEMATIC VER B (PAGE OF )

88 VHF RF BOARD SCHEMATIC VER B (PAGE OF )

89 U0 TOP VIEW S0 S0 S J BOTTOM VIEW S0 S0 S0 Version B Board (see Section.) VHF RF BOARD VER B LAYOUT

90 VR E E E C R 0.uf SHIELDIF LRG SHIELDIF SM SHIELD C C0 C L EC EC EC R K R 0.0uf U 0nH 00 SHLDCOVERIFLRG SHLDCOVERIFSM SPRING IF FROM PG C 00pf C pf L 0nH % 00 U IN G V G V OUT DSF C L 00pf 0nH % 00 C R K L 0nH % 00 C 0pf Q C 0pf C 0pf L nh % 00 IN V G V OUT G DSF L 00 C0.0uf L 00 E SHIELDSPRING CLP E SHIELDLO C C 000pf R 0.V U nshtdn.vxr VCO U nshtdn.v.v U nshtdn VR C uf IN OUT BYP ILC0AIMx C.0uf C.uf L C.uf L C0.0uf OUT IN BYP ILC0AIMx C uf C uf IN OUT BYP ILC0AIM0x C.0uf C.uf L C0 SHIELDED AREA TP TestPoint C 00pf R L 0uH 0 C L0 0uH 0 C0.0uf C.0uf C0.0uf FB FB.0uf.V C 0uf C0 C.0uf C0.0uf C0 C.0uf.0uf DEMOD TP C 0pf TP C.0uf C 000pf VR R 0 C 0pf 0 TP C.uf.uf TP R K C 000pf R K 0uf C 00pf C 00pf VDD VDD VDD VDD VDD VDD VDD VDD VDD LO_RF C.nf TP0 TestPoint C 00pf C.0uf C 00pf R 00K SPI_CLK SPI_MOSI RXBE_CS VCO MXOP IFIN MXON CXIF IFN CXVL FP U LOP GPC LON GCN CXVM VREFP AD VREFN IOUTL VREF IOUTC FREF 0 CLKP SYB CLKN FS 0 PC DOUTB PD DOUTA PE CLKOUT G 0 R C.0uf C0 000pf R 00 R 0 R 0 R 0 RF_FS RF_DAT TP C0.0uf R.K C.uf R.K C0.0uf R K C0 00pf C00 pf D MV0 C0 pf L 0nH 00 R K C pf C pf C pf Q R K TP R C L R0 0 RF_CLK SHIELDED AREA 00 pf 0uH 0 C0.uf NOTE: Individual replacement parts are not available for the RF board, so the entire board must be replaced if it is defective..mhz Version C Board (see Section.) UHF RF BOARD VER C SCHEMATIC (PAGE OF )

91 EPROM DAC MUX N/C ncs BAND BAND SPI_CLK SPI_MOSI ATTEN ADDR RF_CLK RF_DAT RF_FS ADDR SPI_ENA SPI_CLK SPI_MISO SPI_MOSI PLL_LOCK nt/r TX_MOD TX_MOD SPI_MISO TEMP PWR_CTL LOCK_ENA ntx_nap ADDR ADDR PLL_CS SPI_ENA RXBE_CS natten TUNE TUNE.V.V.V UNSW_BAT UNSW_BAT UNSW_BAT VR.V.V.V P SPRINGCLIP J 0PD 0 0 P SPRINGCLIP P SPRINGCLIP P SPRINGCLIP P SPRINGCLIP CP pf CP pf TP TP R 0K U AT00 CS Q WP D CLK HOLD VCC TP TestPoint U VG R 0K TP C pf C.uf C.0uF TP0 U HC 0 Y0 Y Y Y Y Y Y Y A B C GB GA G VCC RP K CP pf TP C.uf P PAD C.0uF FB FB0SO TP CP pf C.0uf P PAD R 0K TP C00.0uF C.uf TP F FUSE00 P PAD TP U AD0 0 VCC VoutA VoutC VoutB SCLK nsy DIN REFabcd VoutD VoutE VoutF VoutG VoutH REFefgh LDAC RP K UHF RF BOARD VER C SCHEMATIC (PAGE OF )

92 PLL 0MHz 0dBm 0MHz VCO PLL TX_MOD SPI_MOSI TX_MOD SPI_CLK PLL_LOCK PLL_CS.MHz LOCK_ENA TX_LO RX_LO BAND BAND BAND BAND nt/r T/R.V VA VA.V.V VA.V VA.V.V.VXR.VXR FB FB C.uF C.uf C.uf R 00 R 0 R C.uF L U AS J J V J V C.uF R C 0pf L nh C.uf E SHIELDPLL U LTES IN OUT BYP nshtdn C pf R K U AS J J V J V C.0uf C 000pF C0.uf FB FB C 0pf U CX0 0 0 CLK MOD_IN MUXOUT VSUBD cm VCCcm FVCO nfvco LD/PS VCCcp CPOUT cp XTALG XTALIN XTALO VCCx x LD/PSa VCCca CPout cp nfvcoa FVCOa VCCcm d VCCd DATA ncs G C 0pf R 0 EC SHLDCOVERPLL C.uf C 0pf C 0uf R 0 C0 0pf C 0pf R 00 TP C uf C pf C 0pf R 00 C 0uf C 0pf U LTES IN OUT BYP nshtdn C 00pf C 000pf C.uf U RF RFIN VPDN RFOUT G G R0 0 R 0 C.uF C.0uF C 0pf C0 0pf FB FB TP C 0pf C 0pf R0 0K C.uF R 0 C 000pf C0 00pf C.pf C uf C uf C 0pf R 0 C.pf U VCODL RF_o V IN G U ILC0AIM0x IN OUT BYP nshtdn C.uf R 00K C 0pf C0.uf L nh C0 0pf C.uf C 000pf R 0 C.uf R0 R 0 R K TP TestPoint Y VTX0C..0 Vcc Out Vtune G C.uF R K U VCODH RF_o V IN G R 0 C 0pf U ADG S S IN V G D C 0pf C 000pF C 0pf UHF RF BOARD VER C SCHEMATIC (PAGE OF )

93 .V R 0K.V U0 SWV C uf D0 SI C ntx_nap C0 uf nshtdn IN OUT BYP ILC0AIM0x C.0uF C.uF L.0uf R 0 Q N00 C 0pF C 000pf L nh 00 UNSW_BAT R. TX_LO R dbm C U0 SGA C R0 FB FB0SO.V FROM PG R 0 0 R 0 0pF dbm 0pF R 00 R 00 R 0 db TP db dbm FB FB0SO C.uf V C 0pf C 000pf C J 0pF L Locate close to PA module C.0uf U 0nH 00 C SWV.V U VCC VOUT LM0 TEMP EC SHLDCOVERPA U SHIELD, P/N M00 RFin Vgg MODRFAMP RA0M0M0 FOR 00 RA0MM0 FOR 00 Vdd RFout C 0pf L 00 C 0pf C D MAP00 L 0nH 00 D MAP00 00 L 0nH C 0pf C RX_IN TO PG UB LM SWV EC0 SPRING TP C.0uf R 0K SWV C 000pf U SREF VPOS VRMS IREF FLTR RFIN COMM PWDN AD TP SWV C.0uf C 00pf C 0pf R 0 0pF R0 0k Q N00 R00 0 R0.V C R0 0 0pF UNSW_BAT R0 0k R Q R0 N00.K.V TX_NAP nt/r Q N00 R.K R K UA LM C0.0uf R M C.uf R0 0K C.uf R 0K PWR_CTL R.K 0pf SHIELD L nh 00 C.pf L KEEP THIS TRACE SHORT C.pf L L nh 00 nh 00 R C C C pf L pf L.pf L R K J ANTENNA.V (.pf) (0pf) (0pf) (.pf) E U (HIGH BAND VALUES) ntx_nap TX_NAP SHIELD VG C.0uF UHF RF BOARD VER C SCHEMATIC (PAGE OF )

94 R0 natten R ATTEN R0 ntx_nap K.VXR TUNE FROM PG RX_IN C R0 0 C0 0pf U V J C0 pf L (pf) J (0 MHz) (0 MHz) C 0 MHz 0 MHz C TP D.pf L R C SI R (.pf).pf L TP 0 0 (.pf) L0 L C0 L L L C L C nh 00 nh nh R 00.0pf L 00 nh 00 nh nh 0 C (pf) 00.pf L 00 C C C.pf L (pf) U C.pf L (.pf).pf L.pf L C TP (.pf) AT L W=, L=0 C.0uf pf L nh W=, L=0 (pf) 00 C C0 L C 0pf C.pf L C0 nh.pf L 0pf 00 C LNA 0pf 0pf C L C C.pf U MGA nh 0pf 0pf U U U0 V RF RF V W=0, L=0 W=0, L=0 W=0, L=0 W=0, L=0 J V C C L L C V J J V J IN OUT J J R 0 FROM PG 0pf V AS C 0pf J C 0pf (W=, L=) (W=, L=) W=, L=0 W=, L=0 C 0pf L J V AS C 0pf 0pf 0pf L nh nh nh G G C C0 C pf 0pf 0pf.pf V AS J C 0pf (W=, L=) (W=, L=) W=, L=0 W=, L=0 C 0pf L J V AS FROM PG TUNE R 0 C pf L C pf L L (pf) L nh (nh) nh (.nh) C C0 pf L pf L (pf) W=, L=0 (W=, L=0) C pf L (0 MHz) 0 MHz R 0 C 0pf R 0 000pf C0 R0 C uf C pf L C 0pf R 0 (0 MHz) 0 MHz L0 nh (nh) 00 C pf L W=, L=0 (W=, L=0) C pf L (pf) L nh (.nh) 00 C pf L (pf) C pf L C 0pf R 0 C 0pf LOW / HI BAND VALUE CHART REF LOW HI RANGE R 0. UHF HIGH BAND VALUES ARE NOTED IN PARENTHESESE (XXX). NOTES: UNLESS OTHERWISE SPECIFIED C.pf.pf C.pf.pf C0.pf.0pf C.pf.0pf C.pf.pf C.pf.pf C pf pf C0 pf pf C pf pf C pf pf C0 pf pf C pf pf L uh uh L nh.nh L0 uh uh L nh.nh UPPER 0 MHz (0 MHz) LOWER 0 MHz (0 MHz) TP L 00 R 0 R 0 R R 0 R0 0 R R 0 G LO G G RF IF ADEA MX R R 0 R R0 0 C R TP IF TO PG L 0nH 00 R C0 R 0 R R0 R R R R RX_LO 0 0 C L L 00 R 0 R C R UHF RF BOARD VER C SCHEMATIC (PAGE OF )

95 TOP VIEW BOTTOM VIEW Version C Board (see Section.) UHF RF BOARD VER C LAYOUT

96 J J J J GROUND TX_OUT BAT_STATUS RAW B BUSS_0 BUSS_0 BUSS_0 *C* pf TP0 L.0nH C 00pF L.0nH *C0* pf C 0.uF L.0nH *C* pf *C*.pF VR 0V C0.0uF R K C 00pF F V C 00pF C0.0uF T_V C pf A C0 00pF C0 0uF E0 R0 OMIT E0 R0 C0 00pF OMIT C0 00pF C0.uF OMIT C0 00pF OMIT R0.K C.uF *U0* RF_OUTPUT RF_IUT VS VS VS VS VCONT SHW0 R0 0 C0 00pF OMIT L0 0nH L0 C0 0nH 00pF OMIT R00 0nH C0.uF R C.pF OMIT R 0 Q0 *C*.pF C C R R RF_IN RF_OUT 0 U0 0J C.pF R0.K C 00pF L0 0nH CR0 R K CR0 CR0 CR0 C 00pF L0 0nH C 00pF L 0nH R K C0 00pF E R0 C 00pF R MEG L0 0nH C0.uF C 00pF C0 00pF BAT_STATUS BUSS_0 DIG_B VR 0V R MEG J J 0 J0 J J J J L 0nH C 00pF R K E R0 Q0 C0 uf C0 00pF OMIT T_V RAWB RAWB T_V J J0 0 SW_B REG_V RESET_ BUSS_0 DA_CE TP BUSS_0 CLOCK R0 0K CLOCK DA_CE DATA D C CLK_CLK CE E EN_BIAS D EN_ANT E D B V E DAT RESET R_T A B Q SC B SC C SC C SC D D REF_DA B TX_DA C RX_DA C SW_C A SW A SW B *U0* U0 R K R 0K C0 pf Q0 C0 pf C 00pF C.uF C 0.uF L 0nH SW_B C0 pf U0 LPC IUT OUTPUT FEEDBACK ERROR SHUTDOWN SENSE V_TAP R 0K C 0.uF RX_V C uf C0 pf C pf OMIT C 00pF RT0 0K R0.K C 00pF B C.0uF C RX_V A TX_V BIAS_EN A CATH_ C ANODE E RF_DET A E PA_BIAS IN_CAP B TEMP_SEN CATH_ RX_I D B B BPOS REF_V C *U0* SCC D ANODE E TX_I D TX_I B BIAS_RT C INT_CAP C C_BIAS D V_CTRL D R0 MEG R0.K R.K C 00pF LOCK_DETECT J TP BUSS_0 L0 SPI_DATA 0nH CLOCK DATA CLOCK DATA C 00pF OMIT C 00pF C 00pF Q0 C uf C 00pF RX_V RX_V R CR *L0*.nH CR 0K *L*.nH *C*.pF L.0nH *C*.pF OMIT *C*.pF OMIT C pf CR *L*.nH R 0K CR *L*.nH *L* nh L.0nH *C0* pf *C*.pF *L* nh VCC RF_IN RF_OUT ABP AG U MX00A 0 R K OMIT C pf *L* nh C.0uF R 0 R C.K.0uF OMIT *L* nh *L0* nh C.pF *C* pf *C*.pF *C*.pF L.0nH C pf C.pF L.nH *C*.pF *C* 0pF L.nH *C0* pf L.0nH *C*.pF *C* pf L.0nH *C*.pF *C* pf *C* pf T XFMR C 00pF R 00 C 00pF C 0uF RFN RFP VCC U00 MX0A LOIN IFN IFP BBP 0 BDIV C.0uF C.0uF T XFMR IF_FREQ RX_INJ NOTE: Individual replacement parts are not available for the RF board, so the entire board must be replaced if it is defective. UHF RF BOARD VER A/B SCHEMATIC (PAGE OF ) Version A/B Board (see Section.) 0

97 J SYNTH_CE TP L 0nH BUSS_0 R0.K R0 K *C0* 00pF C 0uF SUPER_FILTER_VOLTAGE C 00pF MOD_OUT C0.pF OMIT *L0* nh C0.pF C0.pF OMIT C0 00pF *C* pf C0 pf OMIT *L* nh C 0.uF MOD_OUT RX_INJ TX_OUT REF_.MHz *L* nh C 00pF C0.pF OMIT *L* 00nH L0 C pf *C* pf CR0 C 00pF CR0 *L*.nH VEE CR0 *C*.pF *C*.pF CR0 C.pF LASER TRIM R K *C* 0pF *L0* 0nH *C0*.pF *L0*.nH *C*.pF L nh C.pF C0.pF LASER TRIM R0 0K R0 K *R* 0 R0 0K *C*.pF L nh C.0uF *R0* Q0 Q0 L0 0nH C B E R0 0 0 VSF VI VC R K *U0* U 00MHz RX TX PS TRB RBY S S R0 0 L 0nH L0 0nH *L0* nh R0 K C0.0uF C0 00pF *L0* nh SYNTH_CE C.uF C 00pF *C*.pF C 00pF SUPER_FILTER_VOLTAGE C0 000pF C 00pF C 0uF C 00pF R K R K VCC VEE VCC VEE VCC XTAL XTAL *U0* CLK FREFOUT 0 EN_CE MODOUT 0 MODIN VMULT DATA VMULT 0 SUPFIN VMULT VMULT PVREF VBPASS AUX AUX CPBIAS AUX CPBIAS AUX 0 TST SUPFCAP TST SUPFBASE PREIN IOUT IADAPT LOCK ADAPTSW SUPFOUT R 0 R.K 0.uF C R 0 C 00pF R 0 C C 000pF.uF C CR0.0uF K A K A K A C.0uF R C 00K C.0uF.0uF CR0 CR0 K A K A K A C 0.uF S Q0 C0.0uF L 0nH 0nH CR0 CR0 *C*.pF L 0nH SUPER_FILTER_VOLTAGE C 0.uF C.0uF VEE D C.0uF C 00pF C0 000pF C 00pF C0 00pF R K TP V_CTRL LOCK_DETECT BUSS_0 BUSS_ VEE VEE V_CTRL LOCK_DETECT MOD_IN BUSS_ LOCK_DETECT J J J J MOD_IN CLOCK DATA REF_OSC_EN TP SW_B C0.0uF BUSS_0 BUSS_ C0.uF C0 pf SW_B C.uF U0 LPC IUT OUTPUT FEEDBACK ERROR SHUTDOWN SENSE V_TAP C00 pf R 00K C0.0uF REG_V C.0uF C.uF C 0.uF CLOCK DATA REF_OSC_EN L0.uH C0.0uF C0 0.uF C 0.uF 0 CKL_S EN_CE SS SI DE VOPT DCWARP BG VDD CEXT VREG DET_SINE FO_SQWAVE 0 SO 0 *U0* Y.MHz C.0uF L0.uH C 00pF R0 0 REG_V BUSS_ RESET C0 pf J RESET_ SW_B UHF RF BOARD VER A/B SCHEMATIC (PAGE OF )

98 REF_.MHz C0.0uF.MHZ REG_V R C 0.uF R0 0 C0 R0 0K R0 K C0 0pF BUSS_ DOUTx J C 0.uF C.0uF C0 0uF C.uF L0.uH pf VR0 C 00pF BUSS_ DOUT BUSS_ J C.0uF R0 0 ODC J J SBI BUSS_ R0. C0.0uF C0.0uF C 00pF RX_V IF_FREQ L.uH L0 0nH C 0pF C.pF C0 0uF FL J OUT RX V IN L00 0nH C0.pF C0 pf C0 0.uF R0 K R0 K R0.K Q0 R0 00 R0 C0 K 0.uF L0 0nH C0.pF R 0 L0.uH C0.pF R 0K C 0.uF R C 0.uF FL J C0 pf C 0.uF IN OUT CR C 00pF C0.0uF C0.pF RX V C.0uF C pf R0 0K L0.uH R K C0.uF R K C pf C0 0pF C0 0.uF C0 000pF C.pF Q C0 pf C0 0.uF R K C 0.uF R0 0K C0.0uF 0 0 VCC SBI OTBY OT REF NLS IFIN IFIN LOX LO COL BASE FLAG FLAG 0 FLAG FLAG FLAG LVCC VDDH OVCC VCCP VCCP TC 0 TC FLAG FLAG FLAG FLAG FLAG FLAG0 FLAG FLAG FLAG IOUT DOUTX DOUT ODC VDD 0 OB SSL DAF *U0* SC00ZP DAF DAFG BYP BYP O O O O I I O O O O 0 TIX T TC TX T CAPX CAP L D VSSR SUB IFI C 0.uF MOX MO EMIT 0 VPP R0.K C.uF C.0uF C pf R C pf R0 FL0 MIAAR FL0 MIAAR C.uF C pf OMIT L0 0nH C pf R.K RX V R0 C 0.uF GROUND CLIP G GROUND CLIP G S0 SHIELD *S0* SHIELD S0 SHIELD S0 SHIELD S0 SHIELD S0 SHIELD S0 SHIELD TH TOOLHOLE GROUND CLIP G GROUND CLIP PIN G J UHF RF BOARD VER A/B SCHEMATIC (PAGE OF )

99 C C C C C C C C C C C0 C C C C0 C0 C0 C0 C0 C C C C C C0 C C C C C0 C C C0 C0 C0 C0 C0 C C0 C C C C C C C C0 C C C C0 C0 C0 C0 C0 C0 C C C C0 C C C C C C0 C C C C C0 C00 C0 C0 C C C C C0 C0 C0 C0 C C C0 CR CR0 CR0 CR0 CR0 E E E0 E0 F FL FL FL0 FL0 0 0 J J L L L L L0 L L L L L L0 L L L L L L0 L0 L L L L0 L L0 L0 L0 L0 L0 Q0 R R R R0 R R R0 R0 R R R0 R R R0 R0 R0 R0 R0 R0 R R R R R R R R0 R0 S0 S0 S0 S0 T T 0 U U0 U0 U0 U0 0 0 U0 VR VR0 C C C C C0 C C C C C C C C C C C C C0 C0 C0 C0 C0 C C C C C C C0 C C C C C C C C C C0 C0 C0 C0 C0 C C C C C C C C C C0 C C C C C C C0 C C C C C C0 C C C C C0 C C0 C C C C0 C C C C0 C C C C C0 C0 C0 C0 C0 C0 C0 C0 C C C C C C C C C C C0 C0 C0 C0 C0 C C0 C C0 C0 C0 C0 CR CR CR CR CR0 CR0 CR0 CR0 CR0 CR0 CR0 CR0 CR0 G G G G J L L L L L0 L L L0 L0 L0 L0 L L0 L0 L0 L0 L0 L0 L L L L L L L0 L0 L0 L00 Q Q0 Q0 Q0 Q0 Q Q0 Q0 Q0 R R R R00 R0 R0 R0 R0 R R R R R R R R R R R0 R R0 R0 R0 R0 R0 R0 R R R R R R R R0 R0 R0 R R R0 R0 R0 R0 R0 R0 RT0 S0 S0 S0 TP TP TP TP0 TP TP 0 U00 E E A A D B B D U0 E E A A D B B D U0 U U U0 VR BOTTOM VIEW TOP VIEW UHF RF BOARD VER A/B LAYOUT Version A/B Board (see Section.)

100 IF Filter VR C R 0.uf. MHz Crystal Filter C C0 C L. MHz Crystal Filter R K R 0.0uf U 0nH 00 IF From Page C pf C pf U IN L G V G V C OUT L 00pf 0nH % 0nH % DSF C R K L 0nH % 00 IF Amp C 0pf Q C 0pf C 0pf L nh 00 IN V G V OUT G DSF L 00 C0.0uf L 00 C R 0 C 000pf.V V Regulator U nshtdn VR.V.V Regulator U nshtdn.vxr VCO.V Regulator U nshtdn.v C uf IN OUT BYP ILC0AIM0x C.0uf C.uf L C uf IN OUT BYP ILC0AIMx.0uf C C.uf L C.uf L C0.0uf OUT IN BYP ILC0AIMx C uf C0 SHIELDED AREA TP TestPoint C 00pf R L 0uH 0 C L0 0uH 0 C0.0uf C.0uf C0.0uf FB FB.0uf.V C 0uf C0 C.0uf C0.0uf C0 C.0uf.0uf DEMOD TP TP C0 00pf TP TP C.0uf C 000pf VR R 0 C C.nf TP0 TestPoint C.0uf C 00pf C 00pf 00pf C 00pf R 00K C 00pf SPI_CLK SPI_MOSI RXBE_CS VCO Digital IF VDD VDD 0 VDD VDD VDD VDD VDD VDD VDD MXOP IFIN MXON CXIF IFN CXVL FP U LOP GPC LON GCN CXVM VREFP AD VREFN IOUTL VREF IOUTC FREF CLKP SYB 0 CLKN FS 0 PC DOUTB PD DOUTA PE CLKOUT 0.uf C.uf C.0uf C0 000pf R 0 R 0 R R 00 TP0 RF_FS RF_DAT TP C0.0uf R.K R.K C.uf C0.0uf R K C0 00pf LO_RF C00 pf D MV0 C 00pf C0 pf L 0nH 00 R K R K C 000pf C pf C pf C pf R K Q R K 0uf TP RF_CLK R 00 C pf L 0uH 0 R0.K 0 C C C SHIELDED AREA C0.uf NOTE: Individual replacement parts are not available for the RF board, so the entire board must be replaced if it is defective. Version C Board (see Section.).MHz From Page 00/00 MHZ RF BOARD VER C SCHEMATIC (PAGE OF )

101 UNSW_BAT TP UNSW_BAT P F FB PAD P PAD N/C FUSE 00 C pf FB0S0 C.uf C.0uf.V P PAD TP Multiplexer C00 ADDR ADDR SPI_ENA U HC A B C G GA GB VCC.0uF Y0 Y Y Y Y 0 Y Y Y RXBE_CS PLL_CS P P.V EPROM STPAD STPAD U AT00 CS CLK D HOLD WP VCC.0uF Q CP SPI_CLK SPI_MOSI SPI_MISO pf STPAD C P P P STPAD STPAD LOCK_ENA CP pf VR U C.0uF DA Converter TP TestPoint J.V.V UNSW_BAT RF_CLK RF_DAT RF_FS LDAC VCC nsy SCLK DIN REFabcd VoutA VoutB VoutC VoutD VoutE VoutF ADDR ADDR SPI_ENA SPI_CLK SPI_MOSI SPI_MISO.V R 0K.V R 0K TX_NAP TEMP NnT/R TX_MOD TX_MOD.V U VG PLL_LOCK PWR_CTL TUNE_LO BAND BAND RP K AD0 TP TP TP TP TP0 TP TP REFefgh VoutG VoutH CON CP pf CP pf R 0K TUNE TUNE ATTEN RP K 00/00 MHZ RF BOARD VER C SCHEMATIC (PAGE OF )

102 .V.V U Regulator U Regulator U0 Regulator ntx_nap BAND nshtdn nshtdn TUNE nshtdn C TP TestPoint C uf IN OUT BYP LTES C0 00pf C 0uf C uf IN OUT LTES BYP C 00pf C 0uf IN OUT BYP LTES C 00pf C 0uf 000pF.MHz To Page U Switch FB.V J J V J V C 00pf ntx_nap TO PG TX_NAP TX_MOD 00 R R SPI_CLK 0 R TP 0 VA. MHz TCXO Y Vtune C 0pf Vcc Out IVT00B FB FB C VA C.uf C 00pf R C.uF C 00pf TP C 00pf C.uF CX0 000pF 00 C0 C.uf 000pf 0 C.uf PLL U VCCcp VCCcm VCCd ncs FB CLK DATA MOD_IN d MUXOUT VSUBD VCCcm cm FVCOa nfvcoa FVCO nfvco cp LD/PS 0 CPout CPOUT VCCca LD/PSa cp x XTALG VCCx XTALIN XTALO C 00pf FB FB C.uF R 0 C0.uf R 0 C.uF.V C 00pf PLL_CS SPI_MOSI TX_MOD R 0K C 0pf R 00 C.uf R 00 TRANSMIT C.0uf MOD IN V G U RF_o VCOF C 000pf C 00pf 0dBm C pf R 0 R C0 00pf TX_LO AS.VXR C0 00pf C 00pf C.0uf R0 00 C 00pf R 0 R L nh R 0 00 U0 RF RFIN RFOUT VPDN G G R Switch U L.nH 00 C.pf C0 00pf TO PG C C 00pf.0uf RX_LO TO PG Q N00 ntx_nap J V BAND C J J V TO PG TUNE VCO.uf C 000pf C pf AS TO PG PLL_LOCK.V VA R 00K Switch U S V VA LOCK R0 0 R0 C.uf R0 0 C0 00pf Rx VCO MHz IN V G U RF_o UMX0D C0 00pf LOCK_ENA S IN G D ADG CPOUT U Switch V S D S IN G ADG C.0uf R 0 C Rx VCO 0 MHz V U C 000pf C C pf IN RF_o.0uf G 00pf VA Switch U R 0 UMX0D LOCK D V S S LOCK R.V V Regulator U VA G IN ADG TX_NAP 0 C0 uf C uf nshtdn IN OUT BYP ILC0AIM0x C.0uF C.uF L 00/00 MHZ RF BOARD VER C SCHEMATIC (PAGE OF )

103 .V R D 0K D0 SI C.0uf R 0.V SWV U0 C 00pF C.uF R. Q N00 UNSW_BAT ntx_nap C0 uf nshtdn IN OUT BYP ILC0AIM0x C.0uF C.uF L Driver L nh TX_LO From Page R R 0 dbm R C 00pF U0 SGA dbm C 00pF R0 0 R R FB FB0S0 FB C C pf C pf db db dbm FB0S0.uf V R J PA Module U RFin Vgg Vdd RFout C R RX_IN.V U VCC VOUT TEMP RA0M0M.pf HS L 00nH C 00pf HS 0 LM0/SOT SWV UB LM Q N00 TP R.K R 0 TP C.0uf R 0K SWV Power Control UA LM C0 TP SWV SWV C.0uf C C Detector 00pf U SREF VPOS C VRMS IREF FLTR RFIN C COMM PWDN 00pf.0uf AD R R PWR_CTL 0K 0K C C.uf.uf.V R 0 T/R Switch U J V J J V AS.V U C 00pf HS L C.pf L 0nH SHIE LD L C.pf L nh Harmonic Filter L 0nH C.pf L TO PG C.pf L R K From Page J ANTENNA NnT/R R.0uf C.0uF ntx_nap To Page M VG TX_NAP 00/00 MHZ RF BOARD VER C SCHEMATIC (PAGE OF )

104 RX_IN C0 Bandpass Filter C C C TO LNA U V J Switch J C C 00pf.VXR L.VXR.VXR From Page.pf L D BBY.pf L 0 D BBY.pf L V AS J 00pf R K nh 00 C0 00pf C0.0uf C.0uf C0.uF BAND L0 0nH D BBY C.0uf W Resonator C PF W Resonator C pf D BBY C.0uf L 0nh C.0uf TX_NAP C0.0uf U VG00.VXR C 00pf C.0uf Q N00 LowNoise Amp U RF RFIN RFOUT VPDN G G L.nH 00 C.pf Switch U J V J J V AS TP C0.0uf ATTEN TUNE.VXR U C0.0uf VG TUNE C pf BFP C.0uf Switch U V J V J J AS C.pf L C0.pf L L nh C.pf L C C.pf L Bandpass Filter C C0 C.pf L.pf L.pf L C C L.pf L.pf L nh C C 0 MHz Bandpass Filter L C.pf L L nh C.pf L C.pf L C C.pf L L nh C.pf L C.0uf Switch U J V J J V AS C pf TP L nh 00 R C0 pf R 0 R G LO G G Mixer MX ADEX0L R0 RF IF 0 R R R R C pf TP R 0 TP IF To Page TP R R 0 R nh C C R C RX_LO C C C C C C From Page.pf.pf 0.pf C.0uf.0pf L C.0pf L L nh.pf L C.pf L C L nh C C.pf L.0pf L C.pf L C.pf L L nh C.pf L C.0pf L L nh C0.0pf L.0uf L 0nH D BBY D BBY W Resonator W Resonator D BBY D BBY L0 0nH L nh 00 R C pf C.0uf C pf C pf C.0uf BAND NOTES: TUNE_LO. FOR C INSTALL A 0 OHM RESISTOR 00/00 MHZ RF BOARD VER C SCHEMATIC (PAGE OF )

105 TOP VIEW BOTTOM VIEW Version C Board (see Section.) 00/00 MHZ RF BOARD VER C LAYOUT

106 J J J J J0 TX_OUT BUSS_ BAT_CAST G BUSS_ RAW_B BUSS_ RESET_ BUSS_ R SPI_DATA 0 BUSS_ R SPI_CLOCK 0 C pf C pf C0 pf V F00 A E R0 C0.uF E R0 U0 CR0 R0 0K V RF_OUT RF_IN COUPLER C R C R 0 R0.K E R0 C.0uF VR 0V C.0uF E C uf C pf R0 C0 pf Q0 RFOUT C0.0uF C.0uF U0 VCONT RAWB_POS SWB_POS RFIN SHW00 Power Amp C0 C pf 0.uF C0 Q0 pf C R0 K R0.K C pf C pf VR 0V BUSS_ RAW B RAW B BAT_STATUS RAW B BUSS_0 GROUND GROUND GROUND GROUND J J0 J J J J J DA_CE REG_V LOCK_DET BUSS_ C pf C0 pf R0 K C0 pf R0 K C pf.uf C pf J Q0 J L0 0nH C VR 0V OMIT R0 K C0.pF L0.nH CR0 C.0uF C0 pf L0 nh L0 0nH C0 pf C.0uF C0 0uF V E D CLK_CLK C CE E D EN_BIAS EN_ANT E DAT D RESET B R_T A B SC B SC C SC C SC D D DAC SW_C A *U0* U0 SW A SW B REF_DA B TX_DA C C RX_DA C0 pf R0 0K CR0 R 0K RT0 0K C pf C pf B BIAS_EN C A TX_V RX_V BPOS B C REF_V A CATH_ *U0* D TX_I C ANODE SCC B TX_I E RF_DET BIAS_RT C A PA_BIAS C ALC INT_CAP E IN_CAP D C_BIAS B TEMP_SEN D V_CTRL C 0.uF D CATH_ B RX_I D ANODE E R K Ant pf C0.pF L0 0nH C0.pF OMIT C0 pf L0 0nH R00 MEG CR0 DATA CLOCK C0 pf C0 0pF C.0uF C pf C0.0uF C0.pF C0.0uF U0 L0 MX0A L0.nH 0nH L0 C C L0.0nH RF_OUT IN U0 OUT IN U0 OUT RF_IN.nH V V.pF P Filter.pF T0 P Filter RF AMP ABP L0 C0 XFMR AG.0uF.nH C0 C0 pf 0uF 0 AVDD 0 R0 0 0 C 0pF RFN RFP LOIN VCC IFN U0 IFP MX0A 0 BBP MIXER BDIV T0 V0 C 0uF C.0uF C0 pf IF_FREQ C0 00pF C0 pf C0 pf C.0uF C.0uF R0 00 C0 0uF C.0uF C pf RX_INJ NOTE: Individual replacement parts are not available for the RF board, so the entire board must be replaced if it is defective. 00 MHZ RF BOARD VER A/B SCHEMATIC (PAGE OF ) Version A/B Board (see Section.) 0

107 J C 0.uF C 0.uF C.0uF VCO MODULE L0 0uH U IN TX TX_BIAS RX RBY U SP VCO 0 TRB SP FLIP BUFFER PRE C pf XTAL FracN XTAL CLK *U0* U FREFOUT 0 0 EN_CE MODOUT MODIN VMULT DATA VMULT 0 SUPFIN VMULT VMULT PVREF VBPASS AUX AUX AUX CPBIAS CPBIAS AUX 0 SUPFCAP TST SUPFBASE TST PREIN IOUT IADAPT LOCK ADAPTSW SUPFOUT C 0.uF C.0uF C0 0.uF C0.pF C0 0.uF C 0.uF EN_CE SS CEXT DCWARPVREG DE DET VOPT FO 0 SCK SO SI Pendulum BUSS_ TX_OUT SYNTH_CE RX_INJ._MHz R0 K C 00pF C0 0.uF C0.uF C.0uF BUSS_ 0 RFOUT BPOS U CNTRL CNTRL SW SW 0 C.0uF C 0pF U0 VCC C pf 0MHz C0 pf C0 pf R K C.0uF C.pF C0 pf C00 C0 00pF 00pF C R R0 K K 0uF C L0 pf nh C0 0uF C.0uF C0 00pF VCC VEE VCC VEE VCC C0.0uF R0 K VSSA_VSSD TP0 C 00pF C0 0.uF R C 0.uF R0 K C 0.uF C 0.uF CR0 A A A K K K C.0uF C0 0.uF VR 0V J LOCK_DET LOCK_DET LOCK_DET BUSS_ MOD_IN J J J MOD_IN CLOCK DATA REF_OSC_EN SW_B BUSS_ BUSS_ C.0uF C.uF SW_B C.0uF R0 U0 K LPC REG_V IUT OUTPUT FEEDBACK ERROR SHUTDOWNSENSE V Reg V_TAP C.0uF C.0uF C.0uF C 0uF C pf C 0.uF CLOCK DATA REF_OSC_EN C pf C.0uF VDD VDD *U0* V R0.K BUSS_0 REG_V RESET_ J RESET_ 00 MHZ RF BOARD VER A/B SCHEMATIC (PAGE OF )

108 ._MHz C.0uF.MHZ REG_V R C0 0uF R0 0 C.0uF C0 0uF C.uF L0.uH C0 pf R0 0K VR0 R0 K C 00pF C0 0pF BUSS_ BUSS_ BUSS_ DOUTx DOUT J J C.0uF ODC J J SBI BUSS_ R0. C0.0uF C0.0uF IF_FREQ C00.pF L0 0nH C.pF J Crystal F IN OUT FL L00 0nH C0.pF C0 pf C0 0.uF R0 K R0 K R0.K R0 00 R0 K Q0 C0.pF R 0 L0.uH L0 0nH C.pF C0.pF R 0K C 0.uF R C 0.uF Crystal F C0 0pF C 00pF C 0.uF IN OUT VR0 FL J C.0uF C pf C0.0uF REG_V R0 K R K C0.pF C0.uF L0.uH R.K C pf C0 0.uF C0.pF Q C0 000pF C 0.uF R K C.pF C 0.uF R0 0K C0.0uF SBI OTBY OT 0 REF NLS IFIN IFIN LOX LO COL BASE FLAG FLAG 0 FLAG FLAG VCC 0 LVCC VDDH OVCC VCCP VCCP TC 0 TC FLAG FLAG FLAG FLAG FLAG FLAG FLAG0 FLAG FLAG FLAG IOUT DOUTX DOUT ODC VDD 0 OB SSL DAF *U0* SC00ZP ABACUS IC DAF DAFG BYP BYP O O O O I I O O O O 0 L D VSSR SUB IFI VPP C 0.uF MOX MO TIX T TC TX T CAPX CAP EMIT 0 R0.K C.uF C.0uF R R0 FL0 MIAAR C pf FL0 MIAAR C pf C.uF C0 pf L0 0nH C pf R.K REG_V R0 C 0.uF G SH SHIELD SH SHIELD SH SHIELD SH SHIELD SH SHIELD SH SHIELD *SH* SHIELD G G G 00 MHZ RF BOARD VER A/B SCHEMATIC (PAGE OF )

109 0 J E F00 VR 0 E C0 C C C0 C C E R C R R R VR0 C0 C L0 C0 R C R0 C0 C FL C C R0 C FL0 C0 R0 R0 R VR0 R0 FL0 C R0 C C C0 FL C C R0 C00 L0 C0 T0 C SH C C0 C T0 U0 C0 C SH R0 E CR0 U0 0 C C R0 C0 SH R0 C TOP VIEW SH U C R0 R0 C R C0 C00 C C C0 R0 C C0 L0 C0 C C C C C0 C U0 0 0 U0 0 C0 L0 L0 J C0 C L0 C C C C0 L0 C L0 R0 VR C0 Q0 C C0 C0 L0 C0 L0 C0 L0 L0 CR0 C0 CR0 C0 RT0 C0 U0 A 0 SH C C0 B C0 L0 L0 L0 C0 C0 C0 C C0 R0 C0 C0 C C0 0 C C C C0 C0 C0 R0 C C SH R0 C0 C C C0 R0 C0 A A C C 0 C Q0 R0 C0 C C0 C G C0 VR C0 C0 C R0 R C C C C C0 L0 C C C C R0 C C0 C R C J G C U0 C C C C C R C R D A E U0 E B D U0 0 G C R00 C G E E D D Q0 U0 CR0 B B R0 U0 CR0 C C0 C 0 C0 C0 L00 C0 R0 R0 R0 C0 C0 C0 R0 Q0 C U0 0 R C C C0 C R0 R0 R0 L0 L0 C C R C0 C0 C0 C0 SH C TP0 C C0 0 R C U0 C 0 U0 0 L0 R Q C R C0 G R C VR BOTTOM VIEW Version A/B Board (see Section.) 00 MHZ RF BOARD VER A/B LAYOUT

110 HPI_D[0:] HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D0 HPI_D HPI_D HPI_D HPI_D HPI_D0 SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ RF_CLK_DSP 0 RF_DATA_DSP 0 RF_FS_DSP 0 SEM_CLKR SEM_DR SEM_FSR SEM_DX SEM_CLKX SEM_FSX DEC_RXD XD 0 DSP_DS HCNTL0 0 0 DSP_TMS DSP_TDI DSP_TCK DSP_TD HCNTL 0 B _0 _ 0 DSP_CLK I 0 HPI_D[0:] 0 R0.K C.uF R K TMS0VC0 UA TMS0VC0 SDRAS A SDCAS A XF B CLKMEM B SDA0 B0 SDWE B HDRY B HDS B HR/W C HCS C TRST C HDS D CE E BOOTM E RSVD E RST_MODE E RSVD F CLKIN F CE G RSVD G RESET G CE H RSVD H CLKOUT H CE0 J RSVD J IO K BE0 K BE K IO0 K RSVD K TMS K HBE0 K IO L BE L BE L RSVD L EMU/OFF L TDO L TDI L TCK L IO M SSWE M SSOE M IO/BOOTM0 M RSVD M HBE M IO N SSADS N RSVD N HINT N HCNTL0 N HMODE N IO/BOOTM P CLKS P DR P CLKS P FSX0 P INT P ARDY P HOLDA P TIN/TOUT0 P CLKMD P FSR R CLKR R FSR R DR R FSX R DX0 R0 INT R INT0 R INT R ARE R CLKX R EMU0 R TIN/TOUT R IO/BOOTM T CLKR T FSR0 T DR0 T NMI T AWE T INT T FSX T DX T CLKR0 U CLKS0 U CLKX0 U CLKX U DX U INT U AOE U HOLD U C.uF Y.MHz Vref Output Enable VS VC 0 C.0uF R.K C.uF C.0uF R 0K C.0uF R.K TMS0VC0 UC TMS0VC0 A A A A A A D A HD0 A D B D B D B D B A B A0 B HD B HD B HD B HD0 B A0 C D C D0 C A C A C A C A C D0 C HD C HD C0 HD C HD C HD C HD C D D D D D D D D D D D D A D HD D HD D0 HD D HD D HD D HA D HA0 D A E D E D E N N G N HA E HA0 E HA/HCNTL E A F A F A F HA F HA/HAS F A G A G A G E HA G HA G HA G A H A H N HA H HA H A J A0 J N HA J HA J HA J HA K HA K M L HA M HA M D N E N T E J E HA N D P D P D P D P D P0 D P D R D0 R D R D T D T D T D T D T D0 T0 H R 0K U TCSFTEL I O VCC C.uF C.0uF R K C.uF C.0uF R.K R 0 C.uF R K C.uF C.0uF TMS0VC0 UB TMS0VC0 VSS J DVDD U CVDD N0 DVDD U VSS A VSS A DVDD F CVDD L VSS A VSS A VSS B DVDD A DVDD D CVDD K CVDD A CVDD U DVDD D CVDD P CVDD R VSS U VSS H VSS J VSS H CVDD E CVDD F DVDD N DVDD M CVDD N CVDD A CVDD E0 CVDD F VSS A0 VSS U0 VSS U CVDD E DVDD A VSS T VSS U CVDD U DVDD A VSS U C0.0uF R 00K Digital Signal Processor (DSP). MHz TCXO Digital Signal Processor (DSP) Digital Signal Processor (DSP) 000 LOGIC BOARD VER C SCHEMATIC (PAGE OF ) NOTE: The number from next to a node label indicates the page number of the circuit to which it connects. NOTE: Pages and are not used.

111 DSP_CLK TXMOD TXMOD AUDIO_OUT_ SW_VA_0 SW_VA_ SW_VA_ SW_VD_ SW_VD_ SW_VA_ SW_VD_ SW_VA_0 SW_VA_ SW_V_RF DSP_CLK,0 CODEC_RXD CODEC_TXD CODEC_FS CODEC_CLK CODEC_nRESET 0 TXMOD AUDIO_IN_P 0 AUDIO_IN_M 0 AUDIO_OUT SCD 0 SCL 0 TXMOD IN CONFIGURED ODEC C E MOD MASTER UDIO_OUT_ A d use not R K R K R K 0 R K 0 R K 0 0.0uF C R K 0.uF C R K 0 0 R 0 R0 0K R K 0 R K 0 0.0uF C0 R K 0 0 C F.u R K C0.uF R00 K 0.0uF C R K 0 R K 0 R K.uF C R K 0 R K U TLV0AIC HDSI HDSI HDSO HDSO AVDD AVSS TESTTP PWRDN SDA 0 SCL IOVDD IOVSS FSD DVDD DVSS DOUT DIN FS SCLK 0 M/S MCLK RESET VSS DRVSS SPK0 DRVDD DRVSS SPK0 CIDI 0 CIDI AVSS AVDD MICI MICI MICBIAS LCDAC HNSO HNSO HNSI 0 AVDD HNSI AVSS LINEI LINEI LINEO LINE0 0.0uF C C 0pF C0.0uF R K UB OPA0 R K 0 R0 K R K 0 R K R K U REGEA. EN VIN NR VOUT R K 0.uF C WO C 0pF 0.0uF C R K R K R K 0 R K 0 R 0.uF C 0 R K 0 0.uF C UA OPA0 0.0uF C0 R K 0 R K 0 R0 K CODEC 000 LOGIC BOARD VER C SCHEMATIC (PAGE OF ) Version C Board (see Section.)

112 SEM Module 000 LOGIC BOARD VER C SCHEMATIC (PAGE OF )

113 Analog Switch 000 LOGIC BOARD VER C SCHEMATIC (PAGE OF )

114 SW_BATT C 0.uF SW_VD_0 Regulator U VIN VOUT EN NR REGEA/A C 0.0uF C.uF SW_VD_0 R 0 SW_BATT R 0 C 0uF SW_VD_ Supply 0 U VIN PG EN SW LBI FB SY P LBO TPS0X SW_VD_ Supply 0K R L 0uH 0K R C UF 0.0uF C SW_VD_ CR BZXCVLT SW_BATT C00 0.uF R 0 SW_VD_0 Regulator U VIN VOUT EN NR REGEA/A C0 0.0uF SW_VA_0 C0.uF SW_BATT SW_BATT R 0 C.uF C 0uF 0 U VIN PG EN SW LBI FB SY P LBO TPS0X SW_VD_ Supply 0 U VIN PG EN SW LBI FB SY P LBO TPS0X L 0uH 0K R L 0uH R 00K % R 0K C UF CR BZXCVLT C0 UF SW_VD_ PS_SY_CLK SW_VD_ CR BZXCVLT 0.V Regulator VIN ON/OFF BYPASS U VOUT LPSOT/A.V C.uF CR BASTT.V R 00 UNSW_VD_ UNSW_BATT TP C0 0.uF L INDUCTOR FERRITE C0 0.uF DUALMOSFETCHANNEL/B R 00K C0 uf C 0.0uF R 0 C 0uF C 0uF TP0 0 ON_OFF_SW TP CR BAW QB SW_BATT J CONTACT STRIP J CONTACT STRIP 0 POWER_HOLD TP R 00K Q MMBT0TT DUALMOSFETCHANNEL/B QB RF_SW_BATT 000 LOGIC BOARD VER C SCHEMATIC (PAGE OF ) NOTE: Page is not used.

115 To RF Board J 0 RF_CLK_CPLD 0 RF_DATA_CPLD 0 RF_FS_CPLD 0 SYNTH_EN 0 SPI_ADDR_ 0 SPI_ADDR_ 0 SPI_ADDR_,0 MISO 0 SYNTH_LOCK 0 ntxnap 0 TEMP 0 nt/r TXMOD TXMOD R0 R0 R0 R R0 R R R R R0 R RF_SW_V_D K K K K K K K K K K L K L L 0nH 0nH 0nH C 0pF C 0pF C0 0pF C 0pF C 0pF C 0pF C pf C pf C RF_SW_V_D SW_V_RF UNSW_BATT 0pF C 0pF C 0pF C.uF C.uF C.uF 0 0 ZIFCON Analog Switch,0 SPICLK U NO COM CS VCC NLAS/A C.0uF Analog Switch L 0nH RF_SW_BATT L 0nH C.uF SW RF Regulator U VIN VOUT VIN VOUT EN ADJ/NR ERROR REG0UA R K R0 K C0.0uF C.uF SW_V_RF,0 MOSI 0 RF_SPI_ENA U NO COM CS VCC C0 NLAS/A.0uF L0 0nH C.uF RF_SW_V_D Regulator VIN VIN EN U VOUT VOUT ADJ/NR ERROR REG0UA R0 K R0 0K C.0uF C.uF RF_SW_V_D R 0 R 0K Not Placed 000 LOGIC BOARD VER C SCHEMATIC (PAGE OF )

116 0 HDS HDS HPI_D HPI_D HPI_D HPI_D0 HPI_D HPI_D IB_D0 IB_D IB_D IB_D IB_D IB_D IB_D IB_D H_nCS H_R/nW HDS DS H HPI_D HPI_D HPI_D HPI_D0 HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D nhreset LOGBRD_nRST SW_VD_0 SW_VD_ UNSW_VD_ SW_BATT SW_VA_0 SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ HCNTL0 AUDIO_OUT_P nhint HCNTL TEMP HPI_D[0:] H_nCS AUDIO_OUT_M SYNTH_LOCK AUDIO_IN_M AUDIO_IN_P, MISO POWER_HOLD SPICLK, nt/r RX_AUDIO_MUTE SPI_ADDR_ RF_SPI_ENA nhrdy H_R/nW SPI_ADDR_ ON_OFF_SW SYNTH_EN SPI_ADDR_ ntxnap, MOSI SCD SCL CPLD_TDI CPLD_TMS CPLD_TCK CPLD_TDO FIPS_CS DSP_DS0 FIPS_IRQ DSP_CLK, RF_CLK_CPLD RF_DATA_CPLD RF_FS_CPLD RF_CLK_DSP RF_DATA_DSP RF_FS_DSP CODEC_nRESET nhreset LOGBRD_nRST PS_SY_CLK C.uF 0 R 0 C.uF R.K R 0 C.uF J CON0_OE/A U SP D CK CLR PR Q Q VCC C.uF C0.uF U0 XCC C F H IO K IO H VCCIO C VCCIO H VCC G VAUX D TDI J0 TCK K0 TMS K TDO A I/O K I/OGCK K IO K I/OGCK K I/OGCK0 J I/O G I/O H I/O F I/O G I/O C I/O A I/OGSR B I/OGTS A I/OGTS A I/OGTS0 C I/OGTS D I/O E I/O E I/O F I/O C I/O A I/O C I/O C I/O A I/O A I/O A I/O A0 I/O B0 I/O C0 I/O D I/O E I/O D0 I/O K I/O H I/O K I/O H I/O H I/O K I/O H0 I/O G0 I/O F0 I/O E0 I/O A To UI Board D FlipFlop Programmable Logic 000 LOGIC BOARD VER C SCHEMATIC (PAGE 0 OF )

117 SW_VD_ TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP SW_BATT DSP_EMU0 DSP_EMU/nOFF DSP_nTRST CPLD_TMS CPLD_TCK CPLD_TDI CPLD_TDO DSP_TMS DSP_TCK DSP_TDI SW_VD_ DSP_TDO R0.K R.K R.K R.K R.K R.K R.K R.K R.K R0.K R.K R.K R.K R.K R.K IO_0 IO_ IO_ IO_ IO_ IO_ IO_ BOOT_ nint_0 nint_ nint_ nint_ nint_ nint_ nint_nmi IO_ R.K 000 LOGIC BOARD VER C SCHEMATIC (PAGE OF )

118 TOP VIEW BOTTOM VIEW 000 LOGIC BOARD VER C LAYOUT Version C Board (see Section.)

119 U LVTH/A T/R OE T/R OE R 0K R 00 U XCR0XLBGA/A I/O0 A VDD C I/O A I/O C I/O C I/O C I/O D VDD G I/O D I/O E I/O F I/O G VDD B I/O0 E I/O F I/O G I/O F I/O C I/O A A I/O B I/O D I/O C I/O D I/O0 D I/O E E I/O F I/O G I/O G I/O F I/O G I/O F A B G F E CLK0/IN0 A CLK/IN B TDI B TDO B TCK E TMS D VDD E CLK/IN A CLK/IN B PORT_EN C UC ACT 0 U ACT/A T/R OE T/R OE 0 VCC VCC VCC VCC B0 B B B B B B B B B B0 B B B 0 B B A0 A A A A A 0 A A A A A0 A A 0 A A A ADSIC_D DSP_D DSP_A DSP_D ADSIC_A ADSIC_D0 DSP_D ADSIC_D DSP_A DSP_D DSP_D ADSIC_D DSP_D ADSIC_A DSP_A ADSIC_D DSP_D ADSIC_A DSP_D DSP_A0 ADSIC_D DSP_A ADSIC_D0 ADSIC_A ADSIC_D ADSIC_D DSP_D ADSIC_D DSP_D DSP_D ADSIC_A0 DSP_D ADSIC_D DSP_D0 ADSIC_D ADSIC_D ADSIC_D DSP_D0 DSP_A DSP_D ADSIC_A ADSIC_D DSP_D ADSIC_D SW_VD_ SW_VD_0 SW_VD_ SW_VD_0 SW_VD_ ADSIC_RXD SCLK ADSIC_nWR RF_nSYNSEL RF_nRESET SIGCLK GL_TDO ADSIC_SCKR RF_ADSIC_nSEL RF_nDACSEL ADSIC_RFS SPD ADSIC_IRQA ADSIC_TFS RF_nROSCSEL ADSIC_nRST ADSIC_PS ADSIC_TXD ADSIC_SCKT ADSIC_nRD nlock_det ISW_SIG ADSIC_IRQB ADSIC_nSEL R 00K R 00K R.K R 00K R.K TMS0VCBGA/A TCK H TDO H0 A0 A TDI H TMS G A A R/W H CLKMD K A B EMU0 J EMU/OFF J TRST H CLKMD K0 A E TOUT J CLKMD K X F0 X/CLKIN E A B A B A C A E A A A E A0 D A B A B D B A A A C A A D B D C D D A B A D A D A0 C A D A A A D D C D0 D D A0 D B0 D C0 D D0 D C D D D D D D D E0 D0 E CLKOUT F DSP_A DSP_A DSP_A0 DSP_A DSP_A DSP_A SW_VD_ DSP_R/nW TCK TMS EMU0 DSP_TDO DSP_TDI EMU/nOFF ntrst DSP_D DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D R.K IAQ K IACK N INT0 K INT N0 HPI K XF J BIO K RS E DS H BCLKR0 K BCLKR N BCLKR L BDR0 K BDR M BDR M BFSR0 M HOLDA J MSC J INT M0 INT L0 PS G IS H MSTRB H NMI L READY G HOLD K IOSTRB J MP/MC L BFSR M BFSR N BCLKX0 N BCLKX N BCLKX K BDX0 L BDX M BDX K BFSX0 M BFSX N BFSX N SW_VD_ HD F HD A HD C HD D HPIENA G0 HD0 M HD A HD J0 HD M HR/W G HDS C HDS A HCS G HBIL M HCNTL0 M HCNTL L HRDY L HINT M HAS F HPI_D HPI_D HPI_D0 HPI_D HPI_D HPI_D HPI_D HPI_D SW_VD_ R0 0K R 0K U CVDD E CVDD F CVDD G CVDD N CVDD N CVDD B CVDD C CVSS A CVSS C CVSS F CVSS L CVSS N CVSS L CVSS L CVSS G DVDD L DVDD K DVDD A DVDD B DVSS F DVSS L DVSS F DVSS C DVSS N DVSS N DVSS M DVSS D DVSS B DVDD L CVSS B DVDD C CVSS0 A SW_VD_ R 0K SW_VD_ SW_VD_ TP TP TP TP0 TP TP TP TP A0 A A A A A A A A A A0 A A A A A VCC VCC VCC VCC B0 B B B B B B B B B B0 B B B B B R R R R R R R R R R R R R R R R R 00 R 00 R 00 R 00 R 00 R 00 R 00 R 00 R 00 R0 00 R0 00 R 00 R0 00 R 00 R 00 R 00 U ACT/A I0 I I I I I 0 I I I I I0 I I 0 I I I O0 O O O O O O O O O O0 O O O 0 O O OE OE OE OE 0 VCC VCC VCC VCC C SW_VD_0 SW_VD_ 0.0uF 0.0uF 0.uF 0.0uF 0.uF 0.0uF 0.uF 0.uF C C C C C C C0 C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF C 0.uF C 0.uF C 0.0uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C0 0.0uF C 0.0uF C 0.uF SW_VD_ SW_VD_ To/From Sheet RFSPIEN SDO_MUTE J CON0_OE/A HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D0 HPI_D UNSW_VD_ SW_VD_0 SW_BATT SW_VD_ HCNTL0 HCNTL HBIL DSP To UI Board BUS TRANSCEIVER BUS TRANSCEIVER STATE BUFFER TP H_nCS HCNTL0 HINT HCNTL HDS H_R/nW HDS HBIL HINT POWER_HOLD ISW_IRQ RX_AUDIO_MUTE ADSIC_nSEL HDS SPICLK H_nCS RF_nLOCK nroscsel nsynsel ndacsel MOSI AUDIO_OUT_P nhreset ON_OFF_SW AUDIO_OUT_M LOGBRD_nRST H_R/nW HRDY nroscsel SPICLK ndacsel MOSI nsynsel DSP_BCLKX0 DSP_nRST DSP_INT0 ISW_IRQ RF_nLOCK DSP_nIS DSP_BDR0 DSP_nIOSTRB DSP_BFSR0 LOGBRD_nRST DSP_CLKIN DSP_BCLKR0 nhreset DSP_BFSX0 DSP_BDX0 DSP_R/nW DSP_INT ADSIC_nSEL Programmable Logic DSP_HRDY HRDY DSP_HRDY SW_VA_0 AUDIO_IN_P AUDIO_IN_M HDS UA ACT SW_VD_0 QB SiDL Q MMBT0TT R 00K TP0 CR BAW TP R 00K Source UNSW_BATT_FILT Source SW_BATT POWER_HOLD ON_OFF_SW TP Power Switching QB SiDL Source RF_SW_BATT Ferrite Inductor L L C0 0.uF C0 0.uF Ferrite Inductor UNSW_BATT TP LOGIC BOARD VER A SCHEMATIC (PAGE OF ) Revision Board, version w/o encryp module Version A Board (see Section.)

120 D MMBV0 R K C 0pF C.pF C 0pF R R.K K C0 0.uF R 0 C C.pF 0pF R M L Y.uH 0MHz C.pF ADSIC_A0 ADSIC_A ADSIC_A ADSIC_A ADSIC_A ADSIC_A ADSIC_PS ADSIC_nRD ADSIC_nWR ADSIC_IRQA ADSIC_IRQB SIGCLK ADSIC_nRST R0.K SW_VD_0 SW_VA_0 R 0K SW_VD_0 R.K ADSIC U VDDD VAGB 0 VAGOb VDD VAGOm VDD VAGOs VDD VB VDDA VB VDDAb V0b V0m ABI V0s GCB0 OSCW GCB EXTL GCB XTL GCB D D D0 D A0 D 0 A D A D A D 0 A D A D D PS D RD D0 WR D D IRQA D IRQB DCLK 0 SBI RST DIN C C C C C C C C C 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF ISW_SIG ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D SBI DIN RF_nDACSEL nlock_det RF_nROSCSEL RF_nSYNSEL RF_nRESET RFSPIEN L 0nH R0 K R K R K R K R K L 0nH L 0nH CR BZXCVLT C 0pF C0 0pF C 0pF C 0pF C 0pF C pf C pf C 0pF Source UNSW_BATT RF_SW_BATT To RF Boar d J D Out* D Out Lock Det SB R.K Bat Status DA_CE Ref Osc En Synth_CE 0 SPI_Clk ODC Reset Mod In Unsw B SPI_Data Sw B 0 Unsw B C 0FKZ 0pF L 0nH ADSIC_TFS ADSIC_RFS ADSIC_TXD ADSIC_RXD ADSIC_SCKR ADSIC_SCKT RF_ADSIC_nSEL SCLK SPD ADSIC_SDO ADSIC_MAI TFS RFS TXD RXD 0 RSEL SCKR SCKT 0 TP TP SELx SDO MAI SCLK SPD 0 0 DIN IDC VVO VRO EPSb GDRN VSS VSS DAA DAB DAAm 0 DA VSSA VSSAb VSSD 00 VSS 0 SW_VD_0 C 0.0uF 0.uF C C0 0.0uF C C 0.uF 0.uF ndin IDC SW_VA_0 VVO C 0.0uF SW_VD_0 R 0K SCLK SPD UB ACT SPST ANAL OG SW U NO COM CS VCC NLAS/A SPST ANAL OG SW U NO COM CS VCC NLAS/A L 0nH L0 0nH * * C 0uF SW_VD_ REGULATOR U VIN PG EN L ILIM FB SY 0 P FC TPS00X/B C 0.uF R 00K L 0uH R K % R 00K % C0 0pF C0 0pF Source SW_VD_ C 0uF CR BZXCVLT To/From Sheet SW_VD_0 REGULATOR U Source SW_VD_0 C 0.uF R0 00K R 00K AUDIO_IN_M SW_BAT C 0.uF VIN VOUT EN NR REGEA/A C 0.0uF C.uF C 0.uF SW_VD_ REGULATOR R 00K ADSIC_MAI 0 UC OPA0 R 00K R 00K DIFFERENTIAL TO SINGLE ENDED CONVERTER C 0.0uF R 00K UD OPA0 R 00K R 00K C 0.0uF AUDIO_IN_P C00 0.uF SW_VA_0 REGULATOR U VIN VOUT EN NR REGEA/A C0 0.0uF Source SW_VA_0 C0.uF C 0.0uF C 0.0uF C 0uF U VIN PG EN L ILIM FB SY 0 P FC TPS00X/B C 0.uF L 0uH R K % R 00K % C.pF Source SW_VD_ C CR 0uF BZXCVLT VA_REF ADSIC_SDO R 00K SPST Analog Sw C 0.0uF VA_REF R 00K SW_VA_0 SINGLE ENDED TO DIFFERENTIAL CONVERTER R 00K SDO_MUTE AUDIO_OUT_M UNSW_BATT_FILT C0 uf C 0.0uF UNSW_VD_ REGULATOR U VIN VOUT.V C.uF ON/OFF BYPASS R LPSOT/A 0 Source UNSW_VD_ CR R BASTT 00 VA_REF SOURCE SW_VA_0 R 00K R 00K SW_VA_0 Source VA_REF U0A OPA0 U NO COM CS VCC SW_VA_0 NLAS/A C 0.0uF R0 00K UA OPA0 C0 0.0uF R 00K UB OPA0 AUDIO_OUT_P C C 0uF 0uF R 00K R 00K VA_REF 000 LOGIC BOARD VER A SCHEMATIC (PAGE OF ) Revision Board, version w/o encryption module

121 000 LOGIC BOARD VER A TOP VIEW 000 LOGIC BOARD VER A BOTTOM VIEW Version A Board (see Section.) Revision Board, version w/o encryption module

122 R 0K R 00 U XCR0XLBGA/A I/O0 A VDD C I/O A I/O C I/O C I/O C I/O D VDD G I/O D I/O E I/O F I/O G VDD B I/O0 E I/O F I/O G I/O F I/O C I/O A A I/O B I/O D I/O C I/O D I/O0 D I/O E E I/O F I/O G I/O G I/O F I/O G I/O F A B G F E CLK0/IN0 A CLK/IN B TDI B TDO B TCK E TMS D VDD E CLK/IN A CLK/IN B PORT_EN C DSP_A ADSIC_A DSP_A ADSIC_D ADSIC_A DSP_A ADSIC_D ADSIC_A DSP_A0 ADSIC_D0 DSP_A ADSIC_D ADSIC_A ADSIC_D ADSIC_D ADSIC_A0 ADSIC_D DSP_A ADSIC_A ADSIC_D SW_VD_ SW_VD_ SW_VD_0 ADSIC_RXD SCLK ADSIC_nWR RF_nSYNSEL RF_nRESET SIGCLK GL_TDO ADSIC_SCKR RF_ADSIC_nSEL RF_nDACSEL ADSIC_RFS SPD ADSIC_IRQA ADSIC_TFS RF_nROSCSEL ADSIC_nRST ADSIC_PS ADSIC_TXD ADSIC_SCKT ADSIC_nRD nlock_det ISW_SIG ADSIC_IRQB ADSIC_nSEL R 00K R 00K R.K R 00K R.K TMS0VCBGA/A TCK H TDO H0 A0 A TDI H TMS G A A R/W H CLKMD K A B EMU0 J EMU/OFF J TRST H CLKMD K0 A E TOUT J CLKMD K X F0 X/CLKIN E A B A B A C A E A A A E A0 D A B A B D B A A A C A A D B D C D D A B A D A D A0 C A D A A A D D C D0 D D A0 D B0 D C0 D D0 D C D D D D D D D E0 D0 E CLKOUT F DSP_A DSP_A DSP_A0 DSP_A DSP_A DSP_A SW_VD_ DSP_R/nW TCK TMS EMU0 DSP_TDO DSP_TDI EMU/nOFF ntrst DSP_D DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D R.K IAQ K IACK N INT0 K INT N0 HPI K XF J BIO K RS E DS H BCLKR0 K BCLKR N BCLKR L BDR0 K BDR M BDR M BFSR0 M HOLDA J MSC J INT M0 INT L0 PS G IS H MSTRB H NMI L READY G HOLD K IOSTRB J MP/MC L BFSR M BFSR N BCLKX0 N BCLKX N BCLKX K BDX0 L BDX M BDX K BFSX0 M BFSX N BFSX N SW_VD_ HD F HD A HD C HD D HPIENA G0 HD0 M HD A HD J0 HD M HR/W G HDS C HDS A HCS G HBIL M HCNTL0 M HCNTL L HRDY L HINT M HAS F HPI_D HPI_D HPI_D0 HPI_D HPI_D HPI_D HPI_D HPI_D SW_VD_ R0 0K R 0K U CVDD E CVDD F CVDD G CVDD N CVDD N CVDD B CVDD C CVSS A CVSS C CVSS F CVSS L CVSS N CVSS L CVSS L CVSS G DVDD L DVDD K DVDD A DVDD B DVSS F DVSS L DVSS F DVSS C DVSS N DVSS N DVSS M DVSS D DVSS B DVDD L CVSS B DVDD C CVSS0 A SW_VD_ R 0K SW_VD_ SW_VD_ TP TP TP TP0 TP TP TP TP U ACT/A I0 I I I I I 0 I I I I I0 I I 0 I I I O0 O O O O O O O O O O0 O O O 0 O O OE OE OE OE 0 VCC VCC VCC VCC C SW_VD_0 SW_VD_ 0.0uF 0.0uF 0.uF 0.0uF 0.uF 0.0uF 0.uF 0.uF C C C C C C C0 C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF C 0.uF C 0.uF C 0.0uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C0 0.0uF C 0.0uF C 0.uF SW_VD_ SW_VD_ To/From Sheet RFSPIEN SDO_MUTE J CON0_OE/A HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D0 HPI_D UNSW_VD_ SW_VD_0 SW_BATT SW_VD_ HCNTL0 HCNTL HBIL DSP To UI Board STATE BUFFER TP H_nCS HCNTL0 HINT HCNTL HDS H_R/nW HDS HBIL HINT POWER_HOLD ISW_IRQ RX_AUDIO_MUTE ADSIC_nSEL HDS SPICLK H_nCS RF_nLOCK nroscsel nsynsel ndacsel MOSI AUDIO_OUT_P nhreset ON_OFF_SW AUDIO_OUT_M LOGBRD_nRST H_R/nW HRDY nroscsel SPICLK ndacsel MOSI nsynsel DSP_BCLKX0 DSP_nRST DSP_INT0 ISW_IRQ RF_nLOCK DSP_nIS DSP_BDR0 DSP_nIOSTRB DSP_BFSR0 LOGBRD_nRST DSP_CLKIN DSP_BCLKR0 nhreset DSP_BFSX0 DSP_BDX0 DSP_R/nW DSP_INT ADSIC_nSEL Programmable Logic DSP_HRDY HRDY DSP_HRDY SW_VA_0 AUDIO_IN_P AUDIO_IN_M HDS UA ACT SW_VD_0 QB SiDL Q MMBT0TT R 00K TP0 CR BAW TP R 00K Source UNSW_BAT T_FILT Source SW_BATT POWER_HOLD ON_OFF_SW TP Power Switching QB SiDL Source RF_SW_BATT L C0 0.uF C0 0.uF Ferrite Inductor UNSW_BATT TP 0 0 FIPS_CS MISO FIPS_IRQ A DN DP DR DX CLKX FSX Reset IO_IRQ CLKX DX FSX CLKR DR FSR 0MHz Clk 0 0 FIPS 0 CRYPTO MODULE DSP_CLKIN FSX DX CLKX FSR DR CLKR SW_VD_ SW_VD_.VDC.VDC.VDC.VDC MOSI MISO SPICLK FIPS_CS nhreset FIPS_IRQ IO_Key R 00k R 00k ADSIC_D ADSIC_D ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D BUS TRANSCEIVERS U DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D B0 B B B B B B B A A A A A A 0 0 R 00 R 00 R 00 R 00 R0 00 R 00 R0 00 R 00 SW_VD_ SW_VD_0 DIR A A0 OE VccA VccB U0 DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D0 DSP_D DSP_D B0 B B B B B B B A A A A A A 0 0 R 00 R 00 R 00 R0 00 R 00 R 00 R 00 R 00 SW_VD_ SW_VD_0 DIR A A0 OE VccA VccB SNLVCC SNLVCC UC ACT 0 U SZPX SW_VD_ R 0K 000 LOGIC BOARD VER B SCHEMATIC (PAGE OF ) Version with EFJ SEM Version B Board (see Section.)

123 D MMBV0L/A R K C 0pF C.pF C 0pF R R.K K C0 0.uF R 0 C C.pF 0pF R M L Y.uH 0MHz C.pF ADSIC_A0 ADSIC_A ADSIC_A ADSIC_A ADSIC_A ADSIC_A ADSIC_PS ADSIC_nRD ADSIC_nWR ADSIC_IRQA ADSIC_IRQB SIGCLK ADSIC_nRST R0.K SW_VD_0 SW_VA_0 R 0K SW_VD_0 R.K ADSIC U VDDD VAGB 0 VAGOb VDD VAGOm VDD VAGOs VDD VB VDDA VB VDDAb V0b V0m ABI V0s GCB0 OSCW GCB EXTL GCB XTL GCB D D D0 D A0 D 0 A D A D A D 0 A D A D D PS D RD D0 WR D D IRQA D IRQB DCLK 0 SBI RST DIN C C C C C C C C C 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF ISW_SIG ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D SBI DIN RF_nDACSEL nlock_det RF_nROSCSEL RF_nSYNSEL RF_nRESET RFSPIEN L 0nH R0 K R K R K R K R K L 0nH L 0nH CR BZXCVLT C 0pF C0 0pF C 0pF C 0pF C 0pF C pf C pf C 0pF Source UNSW_BATT RF_SW_BATT To RF Board J D Out* D Out Lock Det SB R.K Bat Status DA_CE Ref Osc En Synth_CE 0 SPI_Clk ODC Reset Mod In Unsw B SPI_Data Sw B 0 Unsw B C 0FKZ 0pF L 0nH ADSIC_TFS ADSIC_RFS ADSIC_TXD ADSIC_RXD ADSIC_SCKR ADSIC_SCKT RF_ADSIC_nSEL SCLK SPD ADSIC_SDO ADSIC_MAI TFS RFS TXD RXD 0 RSEL SCKR SCKT 0 TP TP SELx SDO MAI SCLK SPD 0 0 DIN IDC VVO VRO EPSb GDRN VSS VSS DAA DAB DAAm 0 DA VSSA VSSAb VSSD 00 VSS 0 SW_VD_0 C C 0.0uF 0.uF C0 0.0uF C C 0.uF 0.uF ndin IDC SW_VA_0 VVO C 0.0uF SW_VD_0 R 0K SCLK SPD UB ACT SPST ANALOG SW U NO COM CS VCC NLAS/A SPST ANALOG SW U NO COM CS VCC NLAS/A L 0nH L0 0nH C 0uF SW_VD_ REGULATOR U VIN PG EN L ILIM FB SY 0 P FC TPS00X/B C 0.uF R 00K L 0uH R K % R 00K % C0 0pF C0 0pF Source SW_VD_ C 0uF CR BZXCVLT To/From Sheet SW_VD_0 REGULATOR U Source SW_VD_0 C 0.uF R0 00K R 00K AUDIO_IN_M SW_BAT C 0.uF VIN VOUT EN NR REGEA/A C 0.0uF C.uF C 0.uF SW_VD_ REGULATOR R 00K ADSIC_MAI 0 UC OPA0 R 00K DIFFERENTIAL TO SINGLE ENDED CONVERTER C 0.0uF R 00K UD OPA0 R 00K C 0.0uF AUDIO_IN_P C00 0.uF SW_VA_0 REGULATOR U VIN VOUT EN NR C0 0.0uF Source SW_VA_0 C0.uF C 0.0uF C 0.0uF C 0uF U VIN PG EN L ILIM FB SY 0 P FC TPS00X/B C 0.uF L 0uH R K % R 00K % C.pF Source SW_VD_ C CR 0uF BZXCVLT R 00K R 00K REGEA/A VA_REF ADSIC_SDO R 00K SPST Analog Sw C 0.0uF VA_REF R 00K SW_VA_0 SINGLE ENDED TO DIFFERENTIAL CONVERTER R 00K SDO_MUTE AUDIO_OUT_M UNSW_BATT_FILT C0 uf C 0.0uF UNSW_VD_ REGULATOR U VIN VOUT.V C.uF ON/OFF BYPASS R LPSOT/A 0 Source UNSW_VD_ CR R BASTT 00 VA_REF SOURCE SW_VA_0 R 00K R 00K SW_VA_0 Source VA_REF U0A OPA0 U NO COM CS VCC SW_VA_0 NLAS/A C 0.0uF R0 00K UA OPA0 C0 0.0uF R 00K UB OPA0 AUDIO_OUT_P C C 0uF 0uF R 00K R 00K VA_REF 000 LOGIC BOARD VER B SCHEMATIC (PAGE OF ) Version with EFJ SEM

124 000 LOGIC BOARD VER B TOP VIEW 000 LOGIC BOARD VER B BOTTOM VIEW Version B Board (see Section.) Version with EFJ SEM

125 R 0K R 00 U XCR0XLBGA/A I/O0 A VDD C I/O A I/O C I/O C I/O C I/O D VDD G I/O D I/O E I/O F I/O G VDD B I/O0 E I/O F I/O G I/O F I/O C I/O A A I/O B I/O D I/O C I/O D I/O0 D I/O E E I/O F I/O G I/O G I/O F I/O G I/O F A B G F E CLK0/IN0 A CLK/IN B TDI B TDO B TCK E TMS D VDD E CLK/IN A CLK/IN B PORT_EN C DSP_A ADSIC_A DSP_A ADSIC_D ADSIC_A DSP_A ADSIC_D ADSIC_A DSP_A0 ADSIC_D0 DSP_A ADSIC_D ADSIC_A ADSIC_D ADSIC_D ADSIC_A0 ADSIC_D DSP_A ADSIC_A ADSIC_D SW_VD_ SW_VD_ SW_VD_0 ADSIC_RXD SCLK ADSIC_nWR RF_nSYNSEL RF_nRESET SIGCLK GL_TDO ADSIC_SCKR RF_ADSIC_nSEL RF_nDACSEL ADSIC_RFS SPD ADSIC_IRQA ADSIC_TFS RF_nROSCSEL ADSIC_nRST ADSIC_PS ADSIC_TXD ADSIC_SCKT ADSIC_nRD nlock_det ISW_SIG ADSIC_IRQB ADSIC_nSEL R 00K R 00K R.K R 00K R.K TMS0VCBGA/A TCK H TDO H0 A0 A TDI H TMS G A A R/W H CLKMD K A B EMU0 J EMU/OFF J TRST H CLKMD K0 A E TOUT J CLKMD K X F0 X/CLKIN E A B A B A C A E A A A E A0 D A B A B D B A A A C A A D B D C D D A B A D A D A0 C A D A A A D D C D0 D D A0 D B0 D C0 D D0 D C D D D D D D D E0 D0 E CLKOUT F DSP_A DSP_A DSP_A0 DSP_A DSP_A DSP_A SW_VD_ DSP_R/nW TCK TMS EMU0 DSP_TDO DSP_TDI EMU/nOFF ntrst DSP_D DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D R.K IAQ K IACK N INT0 K INT N0 HPI K XF J BIO K RS E DS H BCLKR0 K BCLKR N BCLKR L BDR0 K BDR M BDR M BFSR0 M HOLDA J MSC J INT M0 INT L0 PS G IS H MSTRB H NMI L READY G HOLD K IOSTRB J MP/MC L BFSR M BFSR N BCLKX0 N BCLKX N BCLKX K BDX0 L BDX M BDX K BFSX0 M BFSX N BFSX N SW_VD_ HD F HD A HD C HD D HPIENA G0 HD0 M HD A HD J0 HD M HR/W G HDS C HDS A HCS G HBIL M HCNTL0 M HCNTL L HRDY L HINT M HAS F HPI_D HPI_D HPI_D0 HPI_D HPI_D HPI_D HPI_D HPI_D SW_VD_ R0 0K R 0K U CVDD E CVDD F CVDD G CVDD N CVDD N CVDD B CVDD C CVSS A CVSS C CVSS F CVSS L CVSS N CVSS L CVSS L CVSS G DVDD L DVDD K DVDD A DVDD B DVSS F DVSS L DVSS F DVSS C DVSS N DVSS N DVSS M DVSS D DVSS B DVDD L CVSS B DVDD C CVSS0 A SW_VD_ R 0K SW_VD_ SW_VD_ TP TP TP TP0 TP TP TP TP U ACT/A I0 I I I I I 0 I I I I I0 I I 0 I I I O0 O O O O O O O O O O0 O O O 0 O O OE OE OE OE 0 VCC VCC VCC VCC C SW_VD_0 SW_VD_ 0.0uF 0.0uF 0.uF 0.0uF 0.uF 0.0uF 0.uF 0.uF C C C C C C C0 C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF C 0.uF C 0.uF C 0.0uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C0 0.0uF C 0.0uF C 0.uF SW_VD_ SW_VD_ To/From Sheet RFSPIEN SDO_MUTE J CON0_OE/A HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D HPI_D0 HPI_D SW_VD_ SW_VD_0 SW_BATT SW_VD_ HCNTL0 HCNTL HBIL DSP To UI Board STATE BUFFER TP H_nCS HCNTL0 HINT HCNTL HDS H_R/nW HDS HBIL HINT POWER_HOLD ISW_IRQ RX_AUDIO_MUTE ADSIC_nSEL HDS SPICLK H_nCS RF_nLOCK nroscsel nsynsel ndacsel MOSI AUDIO_OUT_P nhreset ON_OFF_SW AUDIO_OUT_M LOGBRD_nRST H_R/nW HRDY nroscsel SPICLK ndacsel MOSI nsynsel DSP_BCLKX0 DSP_nRST DSP_INT0 RF_nLOCK DSP_nIS DSP_BDR0 DSP_nIOSTRB DSP_BFSR0 LOGBRD_nRST DSP_CLKIN DSP_BCLKR0 nhreset DSP_BFSX0 DSP_BDX0 DSP_R/nW DSP_INT ADSIC_nSEL PROGRAMMABLE LOGIC DSP_HRDY HRDY DSP_HRDY SW_VA_0 AUDIO_IN_P AUDIO_IN_M HDS UA ACT SW_VD_0 QB SiDL Q MMBT0TT R 00K TP0 CR BAW TP R 00K Source UNSW_BATT_FILT Source SW_BATT POWER_HOLD ON_OFF_SW TP Power Switching QB SiDL Source RF_SW_BATT L C0 0.uF C0 0.uF Ferrite Inductor UNSW_BATT TP 0 0 FIPS_CS MISO ADSIC_D ADSIC_D ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D BUS TRANSCEIVERS U DSP_D DSP_D0 DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D B0 B B B B B B B A A A A A A 0 0 R 00 R 00 R 00 R 00 R0 00 R 00 R0 00 R 00 SW_VD_ SW_VD_0 DIR A A0 OE VccA VccB U0 DSP_D DSP_D DSP_D DSP_D DSP_D DSP_D0 DSP_D DSP_D B0 B B B B B B B A A A A A A 0 0 R 00 R 00 R 00 R0 00 R 00 R 00 R 00 R 00 SW_VD_ SW_VD_0 DIR A A0 OE VccA VccB SNLVCC SNLVCC UC ACT 0 U SZPX SW_VD_ R 0K U CPLD 0 I/O0 C VDD C I/O A I/O A I/O B I/O D I/O C VDD G I/O D I/O D I/O A I/O A VDD B I/O0 C I/O B I/O C I/O C I/O F I/O G A I/O0 G I/O F I/O G I/O F I/O E I/O F E I/O G I/O E I/O F I/O G I/O0 E I/O G D D E F E CLK0/IN0 A CLK/IN B TDI B TDO B TCK E TMS D VDD E CLK/IN A CLK/IN B PORT_EN C SW_VD_ PROGRAMMABLE LOGIC I/O I/O I/O I/O TP TP TP TP TP TP TP TP0 TP TP DSP_CLKIN TP TP TP TP TP TP TP TP TP0 TP TP TP U SW_VD_0 MODULE_RX_DATA MODULE_TX_DATA DES_TDI DES_TDO TCK TMS PORESET BCLKR BDR BFSR BCLKX BDX BFSX DES_TDO TCK TMS GL_TDI DES_TDI TMS TCK J 0 0 SW_BATT R 00k Vcc U SW_VD_0 TCSFTEL UNSW_BATT UC 0 ACT UD ACT TO DESXL UCM Module EMC Wakeup FIPS CS SPD Keyloader EMC Request SCLK MISO Module Rx Data Module Tx Data FIPS_CS SPD SCLK MODULE_RX_DATA MODULE_TX_DATA PORESET ISW_IRQ Tamper Sw PORESET PORESET Q VD_ R 0K 000 LOGIC BOARD VER B SCHEMATIC (PAGE OF ) Version with Motorola UCM

126 D MMBV0L/A R K C 0pF C.pF C 0pF R.K L.uH C.pF R K C0 0.0uF ADSIC_A0 ADSIC_A ADSIC_A ADSIC_A ADSIC_A ADSIC_A ADSIC_PS ADSIC_nRD ADSIC_nWR ADSIC_IRQA ADSIC_IRQB SIGCLK ADSIC_nRST R 0 C 0pF R M Y 0MHz C.pF R0.K SW_VD_0 SW_VA_0 R 0K SW_VD_0 R.K ADSIC U VDDD VAGB 0 VAGOb VDD VAGOm VDD VAGOs VDD VB VDDA VB VDDAb V0b V0m ABI V0s GCB0 OSCW GCB EXTL GCB XTL GCB D D D0 D A0 D 0 A D A D A D 0 A D A D D PS D RD D0 WR D D IRQA D IRQB DCLK 0 SBI RST DIN C C C C C C C C C 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF ISW_SIG ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D0 ADSIC_D ADSIC_D ADSIC_D ADSIC_D ADSIC_D SBI DIN RF_nDACSEL nlock_det RF_nROSCSEL RF_nSYNSEL RF_nRESET RFSPIEN L 0nH R0 K R K R K R K R K L 0nH L 0nH CR BZXCVLT C 0pF C0 0pF C 0pF C 0pF C 0pF C pf C pf C 0pF Source UNSW_BATT RF_SW_BATT To RF Board J D Out* D Out Lock Det SB R.K Bat Status DA_CE Ref Osc En Synth_CE 0 SPI_Clk ODC Reset Mod In Unsw B SPI_Data Sw B 0 Unsw B C 0FKZ 0pF L 0nH To/From Sheet ADSIC_TFS ADSIC_RFS ADSIC_TXD ADSIC_RXD ADSIC_SCKR ADSIC_SCKT RF_ADSIC_nSEL SCLK SPD ADSIC_SDO ADSIC_MAI TFS RFS TXD RXD 0 RSEL SCKR SCKT 0 TP TP SELx SDO MAI SCLK SPD 0 0 DIN IDC VVO VRO EPSb GDRN VSS VSS DAA DAB DAAm 0 DA VSSA VSSAb VSSD 00 VSS 0 SCLK SPD SW_VD_0 C0 0.0uF C 0.0uF0.uF C C C 0.uF 0.uF ndin IDC SW_VA_0 VVO C 0.0uF SW_BAT SW_VD_0 R 0K SCLK SPD V REGULATOR U VIN VOUT EN NR UB ACT SPST ANALOG SW U NO COM CS VCC NLAS/A SPST ANALOG SW U NO COM CS VCC NLAS/A L 0nH L0 0nH * * SW_BAT C 0.uF R K SW_VD_ 0.uF SW_VD_0 REGULATOR U VIN VOUT EN NR REGEA/A SW_VA_0 REGULATOR U VIN VOUT EN NR REGEA/A C 0.0uF C0 0.0uF C.uF Source SW_VA_0 C0.uF Source SW_VD_0 C 0.0uF C 0.uF C 0.0uF REGEA/A C 0.uF ADSIC_MAI 0 R0 00K UC OPA0 R 00K R 00K R 00K DIFFERENTIAL TO SINGLE ENDED CONVERTER C 0.0uF R 00K UD OPA0 R 00K R 00K C 0.0uF PORESET AUDIO_IN_M SW_VD_ R R 00k 00k DUAL REGULATOR SW_VD_ SW_VD_ U VIN VOUT VIN VOUT VIN VOUT 0 VOUT VIN0 MR Vsense/FB MR Vsense/FB EN Reset SEQ PG 0 0 TPS0PWP SOURCE SW_VD_ C0 0uF SOURCE R SW_VD_ 0k C0 0uF SW_VA_0 R 00K R 00K VA_REF SOURCE SW_VA_0 Source VA_REF U0A OPA0 VA_REF ADSIC_SDO R 00K R 00K SINGLE ENDED TO DIFFERENTIAL CONVERTER SDO_MUTE AUDIO_OUT_M SPST Analog Sw C 0.0uF VA_REF SW_VA_0 R 00K U NO COM CS VCC SW_VA_0 NLAS/A C 0.0uF R0 00K UA OPA0 C0 0.0uF R 00K UB OPA0 AUDIO_OUT_P R 00K R 00K VA_REF 000 LOGIC BOARD VER B SCHEMATIC (PAGE OF ) Version B Board (see Section.) 0 Version with Motorola UCM

127 000 LOGIC BOARD VER B TOP VIEW 000 LOGIC BOARD VER B BOTTOM VIEW Version with Motorola UCM

128 ,, SW_VD_ L.uH C 0uF C0 0.uF,, DSDO,,, DSDI PPC_TMS,,, DSCK PORESET RSTCONF,,,,,,, nhreset,,, nsreset IRQ0, IRQ, DSP_HINT, UIB_IRQ, IRQ IRQ IRQ, FIPS_IRQ, MODCK MODCK WAIT_B, EB_WAIT UPWAITB, EB_nOE, DSP_DS0, DSP_DS,,, IP_B0,,, IP_B IP_B IP_B IP_B IP_B IP_B IP_B C.nF SW_VD_ UA XPC0DEPBGA/A EB_WE, EB_WE0 Power PC Microprocessor A KAPWR WE0/BS_AB0/IORD D B VDDSYN WE/BS_AB/IOWR E A VSSSYN WE/BS_AB/PCOE D A VSSSYN WE/BS_AB/PCWE F N TDO/DSDO R TDI/DSDI D0 M R TMS D L T TCK/DSCK D J P TRST D J B PORESET D L C RSTCONF D H B HRESET D F B SRESET D E D TEXP D M N IRQ0 D K N IRQ D0 K D IRQ/RSV D K C IRQ/DP0 D M D IRQ/DP D M D IRQ/DP D J C IRQ/DP D J N IRQ D H A0 FRZ/IRQ D K D OP/MODCK/STS D H B OP/MODCK/DSDO D G C WAIT_B D0 G B KR/RTY/IRQ/SPKO D F D UPWAITA/GPL_A/AS D H B UPWAITB/GPL_B D L E GPL_A0/GPL_B0 D F C OE/GPL_A/GPL_B D G C GPL_A/GPL_B/CS D E D GPL_A/GPL_B/CS D L C GPL_A D F A IP_B0/IWP0/VFLS0 D E C IP_B/IWP/VFLS D0 D D IP_B/IOIS_B/AT D E A IP_B/IWP/VF E B IP_B/LWP0/VF0 J C IP_B/LWP/VF N C IP_B/DSDI/AT0 N D IP_B/PTR/AT P B ALE_B/DSCK/AT P0 D CLKOUT A EXTCLK VDDL A B XFC VDDL G A XTAL VDDL J A EXTAL VDDL T EB_WE0 EB_WE EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D SW_VD_ EB_CS0 EB_CS EB_CS, EB_CS EB_A EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A0 LOGBRD_nRST FS_DAC_VOL FIPS_CS LCD_ LCD_ LCD_ SPI_ADDR_ SPI_ADDR_ SPI_ADDR_ L CS_DAC_VOL C 0.uF C 0.uF C 0.uF C 0.uF C 0.uF C 0.uF C 0.uF C 0.uF C 0.uF C0 0.uF C 0.uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C0 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF Power PC Microprocessor UB D CS0 TSIZ0/REG F A CS TSIZ E B CS RD/WR C A CS BURST B0 B CS BDIP/GPL_B A D CS TS D0 C CS/CE_B TA A B CS/CE_B TEA C M A BI B N A BR B N A BG C0 M A BB A L A0 M A M A TIN/TOUT/CLK/PA R L A TIN/LTCLKA/BRGO/CLK/PA T L A TIN/TOUT/CLK/PA P L A TIN/LRCLKA/BRGO/CLK/PA T K A SMTXD/LRXDA/PA T K A SMRXD/LTXDA/PA N0 G A TXD/PA R K A RXD/PA R J A0 USBOE/PA R J A USBRXD/PA P G A LRQA/LST/PB R H A LST/PB N H A RTS/LST/PB P H A LST/PB R F A SMSYN/SDACK/PB R K A SMSYN/SDACK/PB T0 G A RXD/SMRXD/PB T H A TXD/SMTXD/PB N G A0 BRGO/ICSCL/PB P F A BRGO/ICSDA/PB T A BRGO/SPIMISO/PB T C RXD/SPIMOSI/PB P C TXD/SPICLK/PB0 P N PD SPISEL/PB N P PD CD/LRSYA/PC T P PD CTS/SDACK/LTSYA/PC P R PD USBTXN/PC N R PD USBTXP/PC T T PD TGATE/CD/PC N P PD CTS/PC R T PD0 USBRXN/TGATE/PC0 P N PD USBRXP/PC R0 R PD LST/LRQA/PC T P PD RTS/LST/PC P T PD LST/RTS/DREQ/PC T R PD LST/DREQ0/PC R XPC0DEPBGA/A SW_VD_ Power PC Microprocessor UC E VDD F E VDD F E VDD F nw,, E VDD F E VDD F0 E0 VDD F TS E VDD G TA E VDD G TEA F VDD G BI F VDD0 0 G BR G VDD G0 G VDD G BB H VCC H H VDD H J VDD H TONE_SIG J VDD H OPT_SEL, K VDD H0 K VDD H L VDD J TRM L VDD0 0 J M VDD J M VDD J TEMP_CS M VDD J0 M VDD J M VDD K POWER_HOLD M0 VDD K MUTE_A M VDD K LOAD M VDD K L K0 NTH_LOCK L0 0 K MUTE_B L L L L D R 0 XPC0DEPBGA/A R 0 SCL,, SW_VD_ SDA, R 0 MISO R 0, R 0 MOSI,, R 0 SPICLK, RF_SPI_ENA R 0 UDC_CTS PTT, CLSN P OPT_SEL, UDC_RTS ON_OFF_IND,, IRQ R 0M R K C pf Y C pf.mhz NOTE: The number from next to a node label indicates the page number of the circuit to which it connects. 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF ) Version C Board (see Section.) NOTE: Pages and are not used.

129 EB_D EB_A EB_D EB_D0 EB_A EB_D EB_D EB_D EB_A EB_A EB_D EB_D EB_A EB_D EB_D EB_D EB_D EB_A0 EB_A EB_D EB_A EB_A0 EB_D EB_D EB_A EB_A EB_A EB_A EB_D EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_D EB_A EB_D EB_D EB_D0 EB_D EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_A EB_A EB_D0 EB_D EB_D EB_D0 EB_D EB_A0 EB_A EB_D EB_D EB_A EB_A EB_D EB_A EB_D UNSW_VD_ UNSW_VD_ UNSW_VD_ SW_VD_ SW_VD_ UNSW_VD_ SW_VD_ UNSW_VD_ EB_WE0, EB_WE EB_nOE, EB_R/nW,, EB_A[:0] EB_D[0:],, nhreset,,,,,,, EB_WE0, EB_CS0 PWRGOOD EB_CS EB_CS NOT POPULATED C 0.uF U ZP OE A Y VCC U MxSRAMFBGA A0 A A A A A A B A B A C A C A D A H A H A0 H A H A G A G A F IO F IO E IO D IO C IO C IO D IO E IO F IO F IO G IO B IO C IO0 C IO F IO G IO0 B BLE A BHE B E VCC D VCC E VSS D VSS E CE B WE G OE A A F A E A D H A G CE A A H R 0K R0 0K R0 0K R 0K R 0K C 0.0uF U TCS0FU R 0K C 0.0uF R 0K U MxMxFLASHFBGA/A A0 G A F A E A C A D A F A E A C A D A C A0 E A F A D A C A E DQ J DQ H DQ J DQ K DQ G DQ K DQ K DQ G DQ K DQ G DQ H DQ J DQ0 H DQ H DQ/A J DQ0 G A E A A A F VCC J RESET D VSS K VSS K CE H WE C OE J BYTE H RY/BY C A F A G A D WP/ACC D A0 F M A A B B B L 0 L L L M M M A E C 0.0uF Buffer M x FLASH Memory M x SRAM Memory 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

130 SW_VA_0 VA_REF_ R Not Populated R 0 R 0 Vol Control D/A Converter U VOL_LVL C 00pF R 0K SW_VD_0 OUT DIN REFIN SCLK VDD CS A FS TLVI/A CS_DAC_VOL FS_DAC_VOL Bat Voltage/Vol Ctrl A/D Converter SW_VD_ U VOL_CTRL R 0K C 0.0uF VCC CH0 CH CS CLK DIN DOUT LTCLxMS CS_ADC_BATT/VOL SPICLK, MOSI,, MISO, SW_BATT R K % 0.V 0.V R 0K % R.K % R 0K % OPA0 U0.V.V Temperature D/A Converter SW_VD_ U VCC CS CLK CH0 DIN CH DOUT LTCLxMS TEMP_CS R 00K % C 0.0uF SW_VD_ SW_VD_ SW_VD_0 C 0.0uF C 0.0uF C 0.0uF TEMP 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

131 IP_B IP_B EB_D IP_B IP_B IP_B0 IP_B IP_B IP_B EB_D EB_D EB_D EB_D0 SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ BR TEA IP_B MODCK DSCK,,, IP_B IRQ, IP_B IRQ IP_B0,,, nkr/nretry UIB_IRQ, RSTCONF EB_WAIT, UPWAITB IRQ, IRQ TA BB DSP_HINT, IP_B nhreset WAIT_B FIPS_IRQ, IRQ0 EB_D[0:],, BI IP_B,,, TS IP_B DSDI,,, MODCK IP_B Not Populated Not Populated Not Populated R 0K R 0K UB LCX R 0K U SZPX R 0K R K R 0K R K R 0K UC LCX 0 R0 0K R 0K C0 0.0uF R 0K R.K R 0K R 0K R 0K R 0K UD LCX UA LCX R 0K R.K R0 K R 0K R 0K C 0.0uF R 0K R.K R 0K R K R0.K R0 0K R 0K R.K R 00K R 0K R 00K 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

132 SW_VD_ SW_VD_0 SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_0 SW_VD_ AUX_ TX_LED CHNL_0 SCL,, RX_LED TOG_0 DTMFCOL_ NAVROW_ CHNL_ NAVROW_0 DTMFCOL_0 EMER DTMFCOL_ UIB_IRQ, CHNL_ BACKLT_0 NAVCOL_ NAVROW_ DTMFROW_ BACKLT_ DTMFROW_ SDA, DTMFROW_ NAVCOL_0 AUX_ DTMFROW_0 TOG_ CHNL_ AUX_ TX_DATA RX_DATA R 0K R 0K R K C 0.uF C pf U MA/A E0 E SCL WC SDA VCC VSS C 0.uF C 0.uF Q MMBT0TT Q MMBT0TT R 0K R 0K R K R 0K Q MMBT0TT R 0K R % R R 0K CR LED_DUAL/A A C A C C nf UA XCRXL0BGA/A I/O E I/O E I/O F I/O F I/O F I/O F I/O G I/O G I/O G I/O0 H I/O B I/O B I/O B I/O A I/O A I/O C I/O A I/O E I/O D I/O0 A I/O H I/O H I/O H I/O J I/O J I/O J I/O K I/O K I/O K I/O0 L I/O E I/O D I/O A I/O C I/O B I/O A I/O A I/O B I/O D I/O0 L I/O L I/O M I/O M I/O M I/O N I/O N I/O N I/O N I/O U0 I/O0 T0 I/O W I/O U I/O T I/O W I/O U I/O T I/O V I/O U I/O P I/O0 P I/O R I/O R I/O R I/O R I/O R I/O T I/O T I/O U I/O T I/O0 W I/O T I/O R I/O W I/O U I/O V I/O T I/O V I/O W I/O B I/O0 C I/O A I/O B I/O C I/O A U MAXEAE EN C V C C C V RIN ROUT FORCEOFF TIN FORCEON TOUT VCC INVALID 0 R 0K R K R 0K C pf C 0.uF K x EEPROM Programmable Logic Device (PLD) RS Transceiver 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

133 Programmable Logic Device (PLD), OPT_SEL, OPT_SEL UDC_TXD SW_VD_ R.K R.K R.K 0 SW_VD_ TX_LED RX_LED, IRQ SRC_SEL R 0K R 0K E D B A D D E E E E F F F G D C B A C B C D0 C0 G G G H H H J J K K W0 T U T T W V U W UB I/O I/O T I/O I/O K I/O I/O L I/O I/O0 L I/O I/O M I/O0 I/O M I/O I/O M I/O I/O N I/O I/O N I/O I/O N I/O I/O V I/O I/O U I/O I/O R I/O I/O0 W I/O I/O T I/O00 I/O V I/O0 I/O U I/O0 I/O W I/O0 I/O U I/O0 I/O W I/O0 I/O P I/O0 I/O P I/O0 I/O P I/O0 I/O0 R I/O0 I/O R I/O0 I/O R I/O I/O T I/O I/O U I/O I/O V I/O I/O U I/O I/O IN0 A0 I/O IN D I/O IN C I/O IN B I/O0 I/O PORT_EN P I/O I/O TCK L I/O TDI B I/O TDO C I/O TMS L XCRXL0BGA/A FRZ, DSCK,,, DSDO,, DSDI,,, CLSN PTT, SCL,, nhreset,,,,,,, TCK, TDI TDO_TO_TDI TMS, SW_VD_ C 0.0uF C IP_B,,, IP_B0,,, nsreset,,, nhreset,,,,,,, UDC_RXD UDC_RTS UDC_CTS R0 00 C 0.uF nf C 0.uF C 0.uF C 0.uF Y OUT V DIV SET LTC C 0.uF Oscillator C0 0.uF C 0.uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF SW_VD_ C 0.0uF C 0.0uF R M SW_VD_ C 0.0uF Programmable Logic Device (PLD) SW_VD_ UC A VCC E B0 VCC E C VCC E C VCC E D VCC E0 D VCC E F VCC E J VCC E L VCC G P VCC0 0 G T VCC H U VCC H U VCC J V VCC J V VCC K V VCC K L A L A M A 0 M A N A N A R B R B R B R0 B 0 R B R B R C C P C R C R C T C T C T D 0 T D 0 U D U D U D U D V D V D V E V0 E V F 0 V F 0 V G V H V J W J W K W K W M W M W N 0 W P 0 W P XCRXL0BGA/A 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

134 SW_VA_0 R K C.uF C.uF C 0.0uF C 0.0uF TONE_SIG R 00K R K VA_REF_ R K UB OPA0 L 0.uH R 00K MUTE_B R 00K SW_VA_0 R 0 Q0 R 00K C 00pF C 0.uF R 00K C 0.0uF U VIN VO DC/SD VO BYPASS VDD HP_SENSE LMM UA OPA0 Internal Speaker Amp SW_VA_0 SW_VA_0 VA_REF_ INTSPKR_P INTSPKR_M AUDIO_OUT_M C 0.uF R 00K R 00K MMBT0TT Do not place R R R K SW_VA_0 AUDIO_OUT_P C0 0.uF R 00K VA_REF_ R 00K 00K UD OPA0 C 0.uF R 00K R 0 UC OPA0 C uf L 0.uH 0 R C 00pF C 0.uF R 0K External Speaker Amp U VIN VO DC/SD VO BYPASS VDD HP_SENSE LMM Q MMBT0TT R SW_VA_0 EXTSPKR_P EXTSPKR_M 00K R0 00K nseop VOL_LVL R 00K C 0.0uF U OPA0 SW_VA_0 0K R 0K C 00pF C0 00pF Q MMBT0TT R 0K MUTE_A 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

135 R 00K % EXT_MIC VA_REF_ R.K C 0.uF R 00K R 00K VA_REF_ C 0pF R 00K C0 0pF R 00K 0 UC OPA0 Int/Ext Mic Sel Switch NO VCC U COM CS NLAS/A SW_VA_0 C 0.0uF VA_REF_ R0 R.K R R 00K % 00K % SW_VA_0 R UA OPA0 00K % UD OPA0 AUDIO_IN_M AUDIO_IN_P.K INT_MIC MIC_ VA_REF_ R.K C C 0pF 0.uF R0 00K R 00K C 0pF R 00K C 0pF R 00K UB OPA0 SRC_SEL SW_VA_0 SW_VA_0 R0 00K R0 00K C 0.0uF Q MMBT0TT VA_REF_ C 0.0uF C 0.0uF 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE 0 OF )

136 0 SW_VD_ SW_VD_ SW_BATT SW_VD_ SW_VD_ ND G D GN SW_VD_ SW_VD_0 SW_VD_ SW_VD_ SW_VD_ KEYLOAD CHNL_ PTT, VOL_CTRL CHNL_0 KEYFILL EMER RX_DATA CHNL_ EXT_MIC 0 TOG_ TOG_0 AUX_ AUX_ TX_DATA ON_OFF_SW, AUX_ CHNL_ OPT_SEL, OPT_SEL, TP,,, TP0,, TP,,,,,,,,,, TP0 TP,,, TP,,, TP,,, EXTSPKR_P EXTSPKR_M KEYLOAD MT R0 0K MT0 C 00pF R0 0K J CLIP C 00pF R 0K CR BZXCVLT J FKZ 0 U0 OPA0 R0 0K C0 0.0uF C 0.0uF R 0K R 00K MT J CLIP C 00pF C 0.0uF CR BZXCVLT R0 0K R 0K J FKZ 0 0 R MT0.K R R 0 R 0 C 00pF J GROUND_CLIP CR BZXCVLT C 0.0uF J FKZ 0 R 0K R 0K C 00pF R 00K J0 CLIP R 0K CR BZXCVLT C 00pF R K.K R0 0 R C 00pF R0 0K C0 0.0uF R 00K MT R.K 0 R CR BZXCVLT MT U TLCID out in in in in out VCC To Acc Connector To Top Panel To Side Panel Comparator 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

137 NAVCOL_ NAVCOL_0 NAVROW_0 NAVROW_ S UP Keypad S DOWN NAVROW_ S LEFT S RIGHT R K R0 K R K R K R K S F S F R 0 R 0 R 0 R 0 R 0 R 0 SW_VD_0 DTMFCOL_ DTMFCOL_ DTMFCOL_0 Keypad DTMFROW_0 DTMFROW_ DTMFROW_ S S S R0 SW_VD_0 DTMFROW_ S0 S S 0 R 0 S S S R 0 S * S 0 S # R R K R K R K R K R K R K R0 K 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

138 C0 uf C0 uf C0 uf C0 uf C0 uf To LCD Display J,, MOSI SPICLK_L LCD_ LCD_ LCD_ SW_VD_ 0 0 FPZ R 00K SW_VD_ R 00K Q MMBT0TT SW_VD_,,,,,,, nhreset R 00K Q MMBT0TT C 0.0uF C0.uF C0.uF C0.uF C.uF 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

139 SW_VD_0 SW_VD_ SW_VD_0 SW_VD_ Reset R0 0K R 0K R0.K R.K U C 0.0uF C 0.0uF C 0.0uF VCC VCC/ VCCA LT/A COMP COMP/ COMPA RST PWRGOOD PORESET nhreset,,,,,,, nsreset,,, C.00uF C0.00uF SW_VD_ R 00K R 00K CR ON_OFF_IND,, ON_OFF_SW BAWLT Q MMBT0TT C 0.0uF 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

140 SW_VD_0 BB_D[0:] R CR 00 Q MMBT0TT R0 K BACKLT_0 EB_A[:0] TEMP, EB_WAIT AUDIO_OUT_P AUDIO_OUT_M 0 AUDIO_IN_M 0 AUDIO_IN_P SPICLK_O,, EB_R/nW, DSP_DS0, ON_OFF_SW nt/r P UDIO_MUTE SYNTH_LOCK,,,,,,, nhreset POWER_HOLD EB_A0 EB_A SW_VA_0 SW_BATT UNSW_VD_ SW_VD_0 To Logic Board J SW_VD_ BB_D0 BB_D BB_D BB_D BB_D BB_D BB_D BB_D SDA, SCL,, LOGBRD_nRST MISO, MOSI,, FIPS_CS SYNTH_EN SPI_ADDR_ SPI_ADDR_, DSP_DS, EB_CS, SPI_ADDR_ RF_SPI_ENA DSP_HINT, CON0_OE/A SW_VD_0 C.uF C.uF C.uF C.uF C.uF R R R R0 CR 000 CR0 000 CR 000 CR 000 CR 000 CR 000 CR 000 Q MMBT0TT R0 K BACKLT_ 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

141 TP TP TP TP TP TP,,, TP TP0,, TP TP,,, TP TDI TDO, TCK, TMS TRM_TXD TRM_RXD,,, DSDI,, DSDO,,, DSCK, FRZ,,,,,,, nhreset,,, nsreset,,, IP_B0,,, IP_B PPC_TMS TP TP SW_VD_ TP00 TP0 TP0 TP0 TP0 TP TP TP TP TP TP TP0,,,,,,, TP,,, TP,,, TP,,, 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF ) NOTE: Page is not used.

142 BB_D BB_D0 BB_D BB_D BB_D BB_D BB_D BB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ SW_VD_ TCK, TMS, TDO TDO_TO_TDI EB_nOE, nw,, EB_CS, EB_WE0,,, DS 0, DS, K_O K, C.0uF C.0uF R00 k U XCC C F H IO K IO H VCCIO C VCCIO H VCC G VAUX D TDI J0 TCK K0 TMS K TDO A I/O K I/OGCK K IO K I/OGCK K I/OGCK0 J I/O G I/O H I/O F I/O G I/O C I/O A I/OGSR B I/OGTS A I/OGTS A I/OGTS0 C I/OGTS D I/O E I/O E I/O F I/O C I/O A I/O C I/O C I/O A I/O A I/O A I/O A0 I/O B0 I/O C0 I/O D I/O E I/O D0 I/O K I/O H I/O K I/O H I/O H I/O K I/O H0 I/O G0 I/O F0 I/O E0 I/O A R 0 C.uF U OPA0 C.uF R0 K R.K C0.0uF Programmable Logic Device (CPLD) 000 USER INTERFACE BOARD VER C SCHEMATIC (PAGE OF )

143 000 USER INTERFACE BOARD VER C TOP VIEW Version C Board (see Section.)

144 000 USER INTERFACE BOARD VER C BOTTOM VIEW

145 J CON0_OE/A EB_D GPIO_ EB_D EB_D EB_A EB_D0 EB_A GPIO_ EB_D EB_D GPIO_ EB_CS EB_D EB_A0 GPIO_0 EB_WE0 EB_D UNSW_VD_ In SW_BATT In SW_VD_ In SW_VA_0 In EB_nOE POWER_HOLD nlock_in AUDIO_IN_P MOSI SPICLK RFSPIEN ON_OFF_SW DSP_HINT AUDIO_OUT_P nhreset ISW_IRQ AUDIO_OUT_M AUDIO_IN_M R 0K UNSW_VD_ U KAPWR A VDDSYN B RSTCONF C PORESET B IRQ N IRQ/RSV D IRQ/DP0 C IRQ/DP D IRQ/DP D IRQ/DP C IRQ N IP_B0/IWP0/VFLS0 A IP_B/IWP/VFLS C IP_B/IOIS_B/AT D IP_B/IWP/VF A IP_B/LWP0/VF0 B IP_B/LWP/VF C IP_B/DSDI/AT0 C IP_B/PTR/AT D FRZ/IRQ A0 OP/MODCK/STS D OP/MODCK/DSDO B TRST P TCK/DSCK T TMS R TDI/DSDI R WAIT_B C KR/RTY/IRQ/SPKO B UPWAITA/G PL_A/AS D E WE0/BS_AB0/IORD D WE/BS_AB/IOWR E WE/BS_AB/PCOE D WE/BS_AB/PCWE F J VDDL A VDDL G XFC B TDO/DSDO N VDDL J VDDL T VSSSYN A VSSSYN A XTAL A EXTAL A D0 M D L D J D J D L D H D F D E D M D K D0 K D K D M D M D J D J D H D K D H D G D0 G D F D H D L D F D G D E D L D F D E D0 D D E GPL_A C EXTCLK A CLKOUT D ALE_B/DSCK/AT B GPL_A/GPL_B/CS D GPL_A/GPL_B/CS C GPL_A0/GPL_B0 E TEXP D SRESET B HRESET B IRQ0 N UPWAITB/GPL_B B N N P P0 C.nF C 0uF XPC0DEPBGA/A VDD E VDD E VDD E VDD E VDD E VDD E0 VDD E VDD E VDD F VDD0 F VDD G VDD G VCC H VDD H VDD J VDD J VDD K VDD K VDD L VDD0 L VDD M F F F F F0 F G G G 0 G G0 G H H H H H0 H J 0 J J J J0 J K K K K K0 0 K L L L L L0 L VDD M VDD M VDD M VDD M VDD M0 VDD M VDD M R 0M C0 0.uF. MHz R K L.uH EB_WE0 EB_WE SW_VD_ SW_VD_ SW_VD_ SW_VD_ DSCK UIB_IRQ nsreset IRQ0 nhreset RSTCONF MODCK IP_B IP_B IP_B IP_B IP_B DSDI IRQ FRZ IRQ DSP_HINT PORESET IRQ MODCK nkr/nretry IP_B0 IRQ PPC_TMS WAIT_B IRQ DSDO IP_B UPWAITB IP_B EB_WAIT Y C pf C pf BB A BG C0 BR B RD/WR C TEA C TSIZ0/REG F TSIZ E BURST B0 BDIP/GPL_B A TS D0 TA A BI B BR EB_R/nW BI TS TA TEA A G A H A0 G A F A M A N A N A M A0 L A M A M A L A L A L A K A K A G A K A0 J A J A G A H A H A H A F A K PD N PD P PD P PD R PD R PD T PD P PD0 T PD N PD R PD P PD T PD R CS0 D CS A CS B CS A CS B CS D CS/CE_B C CS/CE_B B A C C EB_CS0 GPIO_ GPIO_ EB_CS GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ EB_CS GPIO_0 GPIO_ EB_CS GPIO_[:] R 0 R 0 R 0 R 0 R 0 TXD/PA R SMRXD/LTXDA/PA N0 RXD/PA R USBOE/PA R USBRXD/PA P LRQA/LST/PB R LST/PB N RTS/LST/PB P LST/PB R SMSYN/SDACK/PB R SMSYN/SDACK/PB T0 RXD/SMRXD/PB T TXD/SMTXD/PB N BRGO/ICSCL/PB P BRGO/ICSDA/PB T BRGO/SPIMISO/PB T RXD/SPIMOSI/PB P TXD/SPICLK/PB0 P SPISEL/PB N TIN/LTCLKA/BRGO/CLK/PA T TIN/TOUT/CLK/PA P TIN/LRCLKA/BRGO/CLK/PA T SMTXD/LRXDA/PA T CD/LRSYA/PC T CTS/SDACK/LTSYA/PC P USBTXN/PC N USBTXP/PC T TGATE/CD/PC N CTS/PC R USBRXN/TGAT E/PC0 P LST/LRQA/PC T RTS/LST/PC P LST/RTS/DREQ/PC T USBRXP/PC R0 LST/DREQ0/PC R TIN/TOUT/CLK/PA R UDC_RTS E_TCLK UDC_RXD MISO POWER_HOLD TRM_TXD OPT_SEL BB TENA TRM_RXD ON_OFF_IND E_RXD CLSN MOSI IRQ ISW_IRQ nlock_in RENA SCL UDC_TXD SDA TONE_SIG E_TXD UDC_CTS RFSPIEN L L L L L L L L L L L L0 L L L L L0 L0 L0 L0 L L0 L0 L L L0 L0 L00 L L0 L0 L L L L L L L0 L EB_D[0:] EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A0 EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A OE/GPL_A/GPL_B C EB_nOE U SZPX UC LCX 0 UD UA LCX R.K SW_VD_ SW_VD_ UB LCX EB_D EB_D EB_D EB_D EB_D0 POWER PC MICROPROCESSOR U A0 A A A A A A B A B A C A C A D A H A H A0 H A H A G A G A F IO F IO E IO D IO C IO C IO D IO E IO F IO F IO G IO B IO C IO0 C IO F IO G IO0 B BLE A BHE B E VSS D VSS E CE B WE G OE A A F A E D G H U A0 A A A A A A B A B A C A C A D A H A H A0 H A H A G A G A F IO F IO E IO D IO C IO C IO D IO E IO F IO F IO G IO B IO C IO0 C IO F IO G IO0 B BLE A BHE B E VSS D VSS E CE B WE G OE A A F A E A D G H EB_A EB_A EB_A0 EB_D0 EB_A0 EB_A EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_D EB_A EB_A EB_A EB_D EB_D EB_D EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_D EB_A EB_D EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_D EB_A EB_A EB_A EB_D EB_A EB_D0 EB_A EB_A EB_A0 EB_A EB_A EB_D0 EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_WE EB_WE EB_WE0 K x SRAM K x SRAM R 0K R 0K R 0K R 0K R K R 0K R K R 0K R R0 R.K R Not Used R 0K R 0K R 0K R Not Used R.K R0 K R 0K R 0K R 0K R.K R 0K R K R0.K R 0K R0 0K R 00K R 0K R 00K SW_VD_ BR TEA IP_B MODCK DSCK IP_B IRQ IP_B IRQ IP_B0 nkr/nretry UIB_IRQ RSTCONF EB_WAIT UPWAITB IRQ TA BB IP_B WAIT_B IRQ IRQ0 BI IP_B TS IP_B DSDI MODCK IP_B 0K C 0.uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.0uF SW_VD_ UNSW_VD_ TO LOGIC BOARD TO/FROM SHEET OF GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ SW_VD_ E_RCLK MUTE_A MUTE_B SPICLK OPT_SEL R0 R0 0K U MxMxFLASHFBGA/A A0 G A F A E A C A D A F A E A C A D A C A0 E A F A D A C A E DQ J DQ H DQ J DQ K DQ G DQ K DQ K DQ G DQ K DQ G DQ H DQ J DQ0 H DQ H DQ/A J DQ0 G A E A A A F VCC J RESET D VSS K VSS K CE H WE C OE J BYTE H RY/BY C A F A G A D WP/ACC D A0 F M A A B B B L 0 L L L M M M E EB_A EB_A0 EB_A EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_D EB_D EB_D EB_D EB_A EB_A EB_A0 EB_A EB_D EB_D0 EB_A EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_A EB_A0 EB_D0 EB_D EB_D EB_A EB_D EB_D EB_A SW_VD_ SW_VD_ 0K M x FLASH EB_CS LCX SZPX VD_ R 0K UNSW_VD._ U (Not Used) EB_R/nW EB_R/nW EB_nOE EB_nOE EB_CS EB_WE0 EB_nOE EB_CS0 0.0uF C 0.0uF C SW_VD_ R 00K R 00K R 00K nhreset Q MMBT0TT Q MMBT0TT 0 0 EB_WE0 EB_CS SW_VD_0 In GPIO_ GPIO_ EB_R/nW EB_WAIT EB_R/nW EB_nOE nhreset EB_WAIT AUDIO_OUT_M AUDIO_OUT_P AUDIO_IN_M AUDIO_IN_P SPICLK ON_OFF_SW ISW_IRQ GPIO_ Ferrite Inductors Ferrite Inductors U LT/A RST COMP VCC VCC/ COMPA VCCA COMP/ R 0K SW_VD_0 SW_VD_ SW_VD_ POREST RESET C.uF SW_VA_0 C 0.0uF SW_VD_0 C 0.0uF C 0.0uF C0 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C0 0.0uF C 0.0uF C 0.0uF C 0.uF C0 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF nlock_in VCC D VCC E CE A A H UNSW_VD_ EB_A R 0 A VCC D VCC E A H UNSW_VD_ EB_A C 0.0uF C 0.0uF.uF C C 0.0uF C 0.0uF C 0.0uF C0 0.0uF C 0.0uF 000 USER INTERFACE BOARD VER A SCHEMATIC (PAGE OF ) Version w/o encryption module Version A Board (see Section.)

146 0 R 0K R K R 0K UA XCRXL0BGA/A I/O E I/O E I/O F I/O F I/O F I/O F I/O G I/O G I/O G I/O0 H I/O B I/O B I/O B I/O A I/O A I/O C I/O A I/O E I/O D I/O0 A I/O H I/O H I/O H I/O J I/O J I/O J I/O K I/O K I/O K I/O0 L I/O E I/O D I/O A I/O C I/O B I/O A I/O A I/O B I/O D I/O0 L I/O L I/O M I/O M I/O M I/O N I/O N I/O N I/O N I/O U0 I/O0 T0 I/O W I/O U I/O T I/O W I/O U I/O T I/O V I/O U I/O P I/O0 P I/O R I/O R I/O R I/O R I/O R I/O T I/O T I/O U I/O T I/O0 W I/O T I/O R I/O W I/O U I/O V I/O T I/O V I/O W I/O B I/O0 C I/O A I/O B I/O C I/O A R 0K R 0K SW_VD_ SW_VD_ AUX_ CHNL_0 SCL TOG_0 DTMFCOL_ RX CHNL_ DTMFCOL_0 EMER DTMFCOL_ UIB_IRQ CHNL_ BACKLT_0 DTMFROW_ BACKLT_ DTMFROW_ SDA TX DTMFROW_ AUX_ DTMFROW_0 nseop CHNL_ AUX_ R % C nf U MA/A E0 E SCL WC SDA VCC VSS SW_VD_ R K SW_VD_ R 0K Q MMBT0TT K R.K R.K R 0K R 0K R.K SW_VD_ OPT_SEL SRC_SEL OPT_SEL R0 00 R M Y LTC V OUT SET DIV C nf SW_VD_ UDC_TXD CR CR CR R Q MMBT0TT 000 SW_VD_0 SCL SDA PTT S F R 0 R 0 S LEFT R 0 S DOWN R 0 R 0 S UP S F R 0 S RIGHT SW_VD_0 NAVCOL_0 NAVROW_ NAVROW_ NAVROW_0 NAVCOL_ R 0 R 0 R 0 S S 0 R 0 R 0 R 0 S0 S R 0 S S R 0 S S * DTMFROW_ DTMFROW_ DTMFCOL_0 DTMFROW_0 DTMFCOL_ DTMFROW_ DTMFCOL_ R0 K S S # R0 0 S S SW_VD_0 R 0 R 0 R 0 R R R R R R K K K K K K DTMF KEYPAD EXTSPKR_M TENA OPT_SEL EXTSPKR_P E_TCLK E_RCLK RENA RX_DATA EXT_MIC TX_DATA OPT_SEL R 0 CR R 0 CR R 0 R 0 R 0 J FKZ 0 BZXCVLT R 0 CR SW_BATT TO ACC JK FLEX FKZ CHNL_ CHNL_0 CHNL_ TOG_ TOG_0 ON_OFF_SW CHNL_ J J 0 R0 0K R0 0K R0 0K R 0K R0 0K R 0K R0 0K SW_VD_ TO TOP FLEX U0 OPA0 C 0.0uF C 00pF C0 0.0uF SW_VD_ VOL_CTRL J FKZ 0 R 0K SW_VD_ PTT AUX_ AUX_ AUX_ R 0K R 0K R 0K FPZ 0 C0.uF C 0.0uF C0.uF C0 uf C.uF C0.uF SPICLK GPIO_ MOSI C0 uf C0 uf C0 uf C0 uf TO PTT SW FLEX TO LCD Q MMBT0TT R CR A C R 00K SW_VD_0 RX_LED TX_LED Q MMBT0TT A C R 00K TX_LED RX_LED UC OPA0 0 R 00K R 00K R 00K R 00K C 0.uF C 0.uF R0 0K R K R 00K C.0uF C 0.0uF R 00K C 0.uF R 00K R K UD OPA0 UB OPA0 R K R 00K C0 0.uF R 0K VA_REF VA_REF SW_VA_0 AUDIO_OUT_P TONE_SIG VOL_LVL AUDIO_OUT_M U OPA0 SW_VA_0 R 0K U LMM VIN VDD HP_SENSE DC/SD VO VO BYPASS C 0.uF R 0K Q MMBT0TT R 00K MMBT0TT SW_VA_0 SW_VA_0 EXTSPKR_P MUTE_A EXTSPKR_M nseop Q C 0.uF Q0 MMBT0TT INTSPKR_P U LMM VIN VDD HP_SENSE DC/SD VO VO BYPASS R 00K INTSPKR_M SW_VA_0 MUTE_B R 00K C 0.0uF C 0.uF R0 00K R.K R 00K Q MMBT0TT UC OPA0 0 R 00K C 0.0uF C0 0pF R 00K UB OPA0 R 00K R0 00K C 0pF 0pF U NLAS/A COM CS NO VCC SW_VA_0 SW_VA_0 VA_REF VA_REF SRC_SEL AUDIO_IN_M AUDIO_IN_P EXT_MIC UA OPA0 R 00K R 00K R 00K C00 0.0uF R0 00K R 00K UD OPA0 R K SW_VA_0 VA_REF VA_REF CR BAWLT R 00K R0 0K R 00K R 0K C 0.0uF Q MMBT0TT SW_VD_ ON_OFF_SW R.K R 0K U0A OPA0 R 0K C 0.0uF U LTCLxMS CH0 CH VCC CLK DIN DOUT CS R 0K GPIO_ GPIO_ GPIO_ SW_VD_ SW_VD_ MISO SPICLK MOSI VOL_CTRL 0.V0.V.V.V R 0K U TLVI/A REFIN VDD DIN SCLK A CS OUT FS C 00pF SW_VD_0 VOL_LVL R 00K % R 0K SW_BATT EMER INTERNAL SPEAKER AMP EXTERNAL SPEAKER AMP AUDIO_OUT_P AUDIO_OUT_M TONE_SIG R K R0 K R K R K R K UIB_IRQ UDC_TXD AUDIO_IN_P AUDIO_IN_M GPIO_ GPIO_ PROGRAMMABLE LOGIC DEVICE (PLD) K x EEPROM BACKLIGHT TO/FROM SHEET OF MK0 R 00K C 0pF C R 00K R0 00K INT_MIC R.K MIC_ C 0.uF VA_REF VA_REF IN/EXT MIC SEL SWITCH SPx OHM SPEAKER SW_VD_ OSCILLATOR Bat Volt/Vol Ctrl A/D Converter Vol Ctrl D/A Converter ON_OFF_IND C 0.uF U MAXEAE C EN Vcc V V C Forceoff C ROut RIn TOut TN C Invalid 0 RS TRANSCEIVER Forceon SW_VD_ C 0.uF C 0.uF C 0.uF R 0K SW_VD_0 RX TX UC XCRXL0BGA/A VCC A VCC B0 VCC C VCC C VCC D VCC D VCC F VCC J VCC L VCC0 P VCC T VCC U VCC U VCC V VCC V VCC V R R R A A A A A A B B B 0 B E E E E E0 E E E G 0 G H H J J K K L L M 0 M N N R R R R0 B B C C C C C C C 0 D D D D D D D D E E 0 F F G H J J K K M M 0 N P P P R R T T T T 0 U U U U V V V V0 V V 0 V V V W W W W W W W 0 W SW_VD_ TP TP TP UB XCRXL0BGA/A I/O H I/O H I/O H I/O J I/O J I/O K I/O K I/O W0 I/O T I/O0 U I/O T I/O T I/O W I/O V I/O U I/O W I/O T I/O K I/O L I/O0 L I/O M I/O M I/O M I/O N I/O N I/O N I/O V I/O U I/O R I/O0 W I/O T I/O V I/O U I/O W I/O U I/O W I/O P I/O P I/O P I/O0 R I/O R I/O R I/O T I/O U I/O V I/O U IN0 A0 IN D IN C IN B PORT_EN P TCK L TDI B TDO C TMS L I/O E I/O D I/O B I/O A I/O D I/O0 D I/O E I/O E I/O E I/O E I/O F I/O F I/O F I/O G I/O D I/O00 C I/O0 B I/O0 A I/O0 C I/O0 B I/O0 C I/O0 D0 I/O0 C0 I/O0 G I/O0 G I/O0 G IRQ TDO CLSN TRM_TXD TCK FRZ UDC_CTS TDI nsreset nhreset DSDI DSDO UDC_RTS UDC_RXD IP_B0 PTT SCL DSCK TP TP TP TP TP TP TP TP00 TP TP TP TP TP TP TRM_RXD TMS PPC_TMS MUTE_A MUTE_B C 0pF U TLCD Out Vcc In Out In In In SW_VD_0 R.k R k R 00k C 00pF C 00pF C 00pF C 00pF CR 00 Q MMBT0TT R0 K R SW_VD_0 R0 CR0 CR R R0 R CR CR ON_OFF_SW IP_B Vol Control Buffer Microphone OPTION SELECT BUFFER R 0k SW_VD_ Battery Voltage Sense R 0 R 0 CR CR CR CR CR E_RXD E_TXD SW_VD_ DSDI DSDO DSCK nhreset nsreset IP_B0 IP_B TP0 TP0 TP0 TP0 R 00K UA OPA0 R 00K SW_VA_0 VA_REF C 0.0uF SW_VD_ R K R 00K 000 USER INTERFACE BOARD VER A SCHEMATIC (PAGE OF ) Version w/o encryption module

147 000 USER INTERFACE BOARD VER A TOP VIEW Version A Board (see Section.) Version w/o encryption module

148 000 USER INTERFACE BOARD VER A BOTTOM VIEW Version w/o encryption module

149 J CON0_OE/A EB_D GPIO_ EB_D EB_D EB_A EB_D0 EB_A GPIO_ EB_D EB_D GPIO_ EB_CS EB_D EB_A0 GPIO_0 EB_WE0 EB_D UNSW_VD_ In SW_BATT In SW_VD_ In SW_VA_0 In EB_nOE POWER_HOLD nlock_in MOSI RFSPIEN DSP_HINT nhreset R 0K UNSW_VD_ U KAPWR A VDDSYN B RSTCONF C PORESET B IRQ N IRQ/RSV D IRQ/DP0 C IRQ/DP D IRQ/DP D IRQ/DP C IRQ N IP_B0/IWP0/VFLS0 A IP_B/IWP/VFLS C IP_B/IOIS_B/AT D IP_B/IWP/VF A IP_B/LWP0/VF0 B IP_B/LWP/VF C IP_B/DSDI/AT0 C IP_B/PTR/AT D FRZ/IRQ A0 OP/MODCK/STS D OP/MODCK/DSDO B TRST P TCK/DSCK T TMS R TDI/DSDI R WAIT_B C KR/RTY/IRQ/SPKO B UPWAITA/GPL_A/AS D E WE0/BS_AB0/IORD D WE/BS_AB/IOWR E WE/BS_AB/PCOE D WE/BS_AB/PCWE F J VDDL A VDDL G XFC B TDO/DSDO N VDDL J VDDL T VSSSYN A VSSSYN A XTAL A EXTAL A D0 M D L D J D J D L D H D F D E D M D K D0 K D K D M D M D J D J D H D K D H D G D0 G D F D H D L D F D G D E D L D F D E D0 D D E GPL_A C EXTCLK A CLKOUT D ALE_B/DSCK/AT B GPL_A/GPL_B/CS D GPL_A/GPL_B/CS C GPL_A0/GPL_B0 E TEXP D SRESET B HRESET B IRQ0 N UPWAITB/GPL_B B N N P P0 C.nF C 0uF XPC0DEPBGA/A VDD E VDD E VDD E VDD E VDD E VDD E0 VDD E VDD E VDD F VDD0 F VDD G VDD G VCC H VDD H VDD J VDD J VDD K VDD K VDD L VDD0 L VDD M F F F F F0 F G G G 0 G G0 G H H H H H0 H J 0 J J J J0 J K K K K K0 0 K L L L L L0 L VDD M VDD M VDD M VDD M VDD M0 VDD M VDD M R 0M C0 0.uF. MHz R K L.uH EB_WE0 EB_WE SW_VD_ SW_VD_ SW_VD_ SW_VD_ DSCK UIB_IRQ nsreset IRQ0 nhreset RSTCONF MODCK IP_B IP_B IP_B IP_B IP_B DSDI IRQ FRZ IRQ DSP_HINT PORESET IRQ MODCK nkr/nretry IP_B0 FIPS_IRQ PPC_TMS WAIT_B IRQ DSDO IP_B UPWAITB IP_B EB_WAIT Y C pf C pf BB A BG C0 BR B RD/WR C TEA C TSIZ0/REG F TSIZ E BURST B0 BDIP/GPL_B A TS D0 TA A BI B BR EB_R/nW BI TS TA TEA A G A H A0 G A F A M A N A N A M A0 L A M A M A L A L A L A K A K A G A K A0 J A J A G A H A H A H A F A K PD N PD P PD P PD R PD R PD T PD P PD0 T PD N PD R PD P PD T PD R CS0 D CS A CS B CS A CS B CS D CS/CE_B C CS/CE_B B A C C EB_CS0 GPIO_ GPIO_ EB_CS GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ EB_CS GPIO_0 GPIO_ EB_CS GPIO_[:] R 0 R 0 R 0 R 0 R 0 TXD/PA R SMRXD/LTXDA/PA N0 RXD/PA R USBOE/PA R USBRXD/PA P LRQA/LST/PB R LST/PB N RTS/LST/PB P LST/PB R SMSYN/SDACK/PB R SMSYN/SDACK/PB T0 RXD/SMRXD/PB T TXD/SMTXD/PB N BRGO/ICSCL/PB P BRGO/ICSDA/PB T BRGO/SPIMISO/PB T RXD/SPIMOSI/PB P TXD/SPICLK/PB0 P SPISEL/PB N TIN/LTCLKA/BRGO/CLK/PA T TIN/TOUT/CLK/PA P TIN/LRCLKA/BRGO/CLK/PA T SMTXD/LRXDA/PA T CD/LRSYA/PC T CTS/SDACK/LTSYA/PC P USBTXN/PC N USBTXP/PC T TGATE/CD/PC N CTS/PC R USBRXN/TGATE/PC0 P LST/LRQA/PC T RTS/LST/PC P LST/RTS/DREQ/PC T USBRXP/PC R0 LST/DREQ0/PC R TIN/TOUT/CLK/PA R UDC_RTS E_TCLK UDC_RXD MISO POWER_HOLD TRM_TXD OPT_SEL BB TENA TRM_RXD ON_OFF_IND E_RXD CLSN MOSI IRQ ISW_IRQ nlock_in RENA SCL UDC_TXD SDA TONE_SIG E_TXD UDC_CTS RFSPIEN L L L L L L L L L L L L0 L L L L L0 L0 L0 L0 L L0 L0 L L L0 L0 L00 L L0 L0 L L L L L L L0 L EB_D[0:] EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A0 EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A OE/GPL_A/GPL_B C EB_nOE U SZPX UC LCX 0 UD UA LCX R.K SW_VD_ SW_VD_ UB LCX EB_D EB_D EB_D EB_D EB_D0 POWER PC MICROPROCESSOR U A0 A A A A A A B A B A C A C A D A H A H A0 H A H A G A G A F IO F IO E IO D IO C IO C IO D IO E IO F IO F IO G IO B IO C IO0 C IO F IO G IO0 B BLE A BHE B E VSS D VSS E CE B WE G OE A A F A E D G H U A0 A A A A A A B A B A C A C A D A H A H A0 H A H A G A G A F IO F IO E IO D IO C IO C IO D IO E IO F IO F IO G IO B IO C IO0 C IO F IO G IO0 B BLE A BHE B E VSS D VSS E CE B WE G OE A A F A E A D G H EB_A EB_A EB_A0 EB_D0 EB_A0 EB_A EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_D EB_A EB_A EB_A EB_D EB_D EB_D EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_D EB_A EB_D EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_D EB_A EB_A EB_A EB_D EB_A EB_D0 EB_A EB_A EB_A0 EB_A EB_A EB_D0 EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_WE EB_WE EB_WE0 K x SRAM K x SRAM R 0K R 0K R 0K R 0K R K R 0K R K R 0K R R0 R.K R Not Used R 0K R 0K R 0K R Not Used R.K R0 K R 0K R 0K R 0K R.K R 0K R K R0.K R 0K R0 0K R 00K R 0K R 00K SW_VD_ BR TEA IP_B MODCK DSCK IP_B IRQ IP_B IRQ IP_B0 nkr/nretry UIB_IRQ RSTCONF EB_WAIT UPWAITB IRQ TA BB IP_B WAIT_B FIPS_IRQ IRQ0 BI IP_B TS IP_B DSDI MODCK IP_B 0K C 0.uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.0uF SW_VD_ UNSW_VD_ TO LOGIC BOARD TO/FROM SHEET OF GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ SW_VD_ E_RCLK MUTE_A MUTE_B SPICLK OPT_SEL R0 R0 0K U MxMxFLASHFBGA/A A0 G A F A E A C A D A F A E A C A D A C A0 E A F A D A C A E DQ J DQ H DQ J DQ K DQ G DQ K DQ K DQ G DQ K DQ G DQ H DQ J DQ0 H DQ H DQ/A J DQ0 G A E A A A F VCC J RESET D VSS K VSS K CE H WE C OE J BYTE H RY/BY C A F A G A D WP/ACC D A0 F M A A B B B L 0 L L L M M M E EB_A EB_A0 EB_A EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_D EB_D EB_D EB_D EB_A EB_A EB_A0 EB_A EB_D EB_D0 EB_A EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_A EB_A0 EB_D0 EB_D EB_D EB_A EB_D EB_D EB_A SW_VD_ SW_VD_ 0K M x FLASH EB_CS LCX SZPX VD_ R 0K UNSW_VD._ U (Not Used) EB_R/nW EB_R/nW EB_nOE EB_nOE EB_CS EB_WE0 EB_nOE EB_CS0 0.0uF C 0.0uF C SW_VD_ R 00K R 00K R 00K nhreset Q MMBT0TT Q MMBT0TT 0 0 EB_WE0 EB_CS SW_VD_0 In GPIO_ GPIO_ EB_R/nW EB_R/nW EB_nOE nhreset EB_WAIT AUDIO_OUT_M AUDIO_OUT_P AUDIO_IN_M AUDIO_IN_P ON_OFF_SW ISW_IRQ GPIO_ Ferrite Inductors Ferrite Inductors U LT/A RST COMP VCC VCC/ COMPA VCCA COMP/ R 0K SW_VD_0 SW_VD_ SW_VD_ POREST RESET C.uF SW_VA_0 C 0.0uF SW_VD_0 C 0.0uF C 0.0uF C0 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C0 0.0uF C 0.0uF C 0.0uF C 0.uF C0 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF nlock_in VCC D VCC E CE A A H UNSW_VD_ EB_A R 0 A VCC D VCC E A H UNSW_VD_ EB_A C 0.0uF C 0.0uF.uF C C 0.0uF C 0.0uF C 0.0uF C0 0.0uF C 0.0uF FIPS_CS AUDIO_IN_P SPICLK ON_OFF_SW AUDIO_OUT_P ISW_IRQ AUDIO_OUT_M AUDIO_IN_M EB_WAIT SPICLK FIPS_CS MISO FIPS_IRQ FIPS_CS 000 USER INTERFACE BOARD VER B SCHEMATIC (PAGE OF ) Version with EFJ SEM Version B Board (see Section.)

150 R 0K R K R 0K UA XCRXL0BGA/A I/O E I/O E I/O F I/O F I/O F I/O F I/O G I/O G I/O G I/O0 H I/O B I/O B I/O B I/O A I/O A I/O C I/O A I/O E I/O D I/O0 A I/O H I/O H I/O H I/O J I/O J I/O J I/O K I/O K I/O K I/O0 L I/O E I/O D I/O A I/O C I/O B I/O A I/O A I/O B I/O D I/O0 L I/O L I/O M I/O M I/O M I/O N I/O N I/O N I/O N I/O U0 I/O0 T0 I/O W I/O U I/O T I/O W I/O U I/O T I/O V I/O U I/O P I/O0 P I/O R I/O R I/O R I/O R I/O R I/O T I/O T I/O U I/O T I/O0 W I/O T I/O R I/O W I/O U I/O V I/O T I/O V I/O W I/O B I/O0 C I/O A I/O B I/O C I/O A R 0K R 0K SW_VD_ SW_VD_ AUX_ CHNL_0 SCL TOG_0 DTMFCOL_ RX CHNL_ DTMFCOL_0 EMER DTMFCOL_ UIB_IRQ CHNL_ BACKLT_0 DTMFROW_ BACKLT_ DTMFROW_ SDA TX DTMFROW_ AUX_ DTMFROW_0 nseop CHNL_ AUX_ R % C nf U MA/A E0 E SCL WC SDA VCC VSS SW_VD_ R K SW_VD_ R 0K Q MMBT0TT K R.K R.K R 0K R 0K R.K SW_VD_ OPT_SEL SRC_SEL OPT_SEL R0 00 R M Y LTC V OUT SET DIV C nf SW_VD_ UDC_TXD CR CR CR R Q MMBT0TT 000 SW_VD_0 SCL SDA PTT S F R 0 R 0 S LEFT R 0 S DOWN R 0 R 0 S UP S F R 0 S RIGHT SW_VD_0 NAVCOL_0 NAVROW_ NAVROW_ NAVROW_0 NAVCOL_ R 0 R 0 R 0 S S 0 R 0 R 0 R 0 S0 S R 0 S S R 0 S S * DTMFROW_ DTMFROW_ DTMFCOL_0 DTMFROW_0 DTMFCOL_ DTMFROW_ DTMFCOL_ R0 K S S # R0 0 S S SW_VD_0 R 0 R 0 R 0 R R R R R R K K K K K K DTMF KEYPAD EXTSPKR_M TENA OPT_SEL EXTSPKR_P E_TCLK E_RCLK RENA RX_DATA EXT_MIC TX_DATA OPT_SEL R 0 CR R 0 CR R 0 R 0 R 0 J FKZ 0 BZXCVLT R 0 CR SW_BATT TO ACC JK FLEX FKZ CHNL_ CHNL_0 CHNL_ TOG_ TOG_0 ON_OFF_SW CHNL_ J J 0 R0 0K R0 0K R0 0K R 0K R0 0K R 0K R0 0K SW_VD_ TO TOP FLEX U0 OPA0 C 0.0uF C 00pF C0 0.0uF SW_VD_ VOL_CTRL J FKZ 0 R 0K SW_VD_ PTT AUX_ AUX_ AUX_ R 0K R 0K R 0K FPZ 0 C0.uF C 0.0uF C0.uF C0 uf C.uF C0.uF SPICLK GPIO_ MOSI C0 uf C0 uf C0 uf C0 uf TO PTT SW FLEX TO LCD Q MMBT0TT R CR A C R 00K SW_VD_0 RX_LED TX_LED Q MMBT0TT A C R 00K TX_LED RX_LED UC OPA0 0 R 00K R 00K R 00K R 00K C 0.uF R0 0K R K R 00K C.0uF C 0.0uF R 00K C 0.uF R 00K R K UD OPA0 UB OPA0 R K R 00K C0 0.uF R 0K VA_REF VA_REF SW_VA_0 AUDIO_OUT_P TONE_SIG VOL_LVL AUDIO_OUT_M U OPA0 SW_VA_0 R 0K U LMM VIN VDD HP_SENSE DC/SD VO VO BYPASS C 0.uF R 0K Q MMBT0TT R 00K MMBT0TT SW_VA_0 SW_VA_0 EXTSPKR_P MUTE_A EXTSPKR_M nseop Q C 0.uF Q0 MMBT0TT INTSPKR_P U LMM VIN VDD HP_SENSE DC/SD VO VO BYPASS R 00K INTSPKR_M SW_VA_0 MUTE_B R 00K C 0.0uF C 0.uF R0 00K R.K R 00K Q MMBT0TT UC OPA0 0 R 00K C 0.0uF C0 0pF R 00K UB OPA0 R 00K R0 00K C 0pF 0pF U NLAS/A COM CS NO VCC SW_VA_0 SW_VA_0 VA_REF VA_REF SRC_SEL AUDIO_IN_M AUDIO_IN_P EXT_MIC UA OPA0 R 00K R 00K R 00K C00 0.0uF R0 00K R 00K UD OPA0 R K SW_VA_0 VA_REF VA_REF CR BAWLT R 00K R0 0K R 00K R 0K C 0.0uF Q MMBT0TT SW_VD_ ON_OFF_SW R.K R 0K U0A OPA0 R 0K C 0.0uF U LTCLxMS CH0 CH VCC CLK DIN DOUT CS R 0K GPIO_ GPIO_ GPIO_ SW_VD_ SW_VD_ MISO SPICLK MOSI VOL_CTRL 0.V0.V.V.V R 0K U TLVI/A REFIN VDD DIN SCLK A CS OUT FS C 00pF SW_VD_0 VOL_LVL R 00K % R 0K SW_BATT EMER INTERNAL SPEAKER AMP EXTERNAL SPEAKER AMP AUDIO_OUT_P AUDIO_OUT_M TONE_SIG R K R0 K R K R K R K UIB_IRQ UDC_TXD AUDIO_IN_P AUDIO_IN_M GPIO_ GPIO_ PROGRAMMABLE LOGIC DEVICE (PLD) K x EEPROM BACKLIGHT TO/FROM SHEET OF MK0 R 00K C 0pF C R 00K R0 00K INT_MIC R.K MIC_ C 0.uF VA_REF VA_REF IN/EXT MIC SEL SWITCH SPx OHM SPEAKER SW_VD_ OSCILLATOR Bat Volt/Vol Ctrl A/D Converter Vol Ctrl D/A Converter ON_OFF_IND C 0.uF U MAXEAE C EN Vcc V V C Forceoff C ROut RIn TOut TN C Invalid 0 RS TRANSCEIVER Forceon SW_VD_ C 0.uF C 0.uF C 0.uF R 0K SW_VD_0 RX TX UC XCRXL0BGA/A VCC A VCC B0 VCC C VCC C VCC D VCC D VCC F VCC J VCC L VCC0 P VCC T VCC U VCC U VCC V VCC V VCC V R R R A A A A A A B B B 0 B E E E E E0 E E E G 0 G H H J J K K L L M 0 M N N R R R R0 B B C C C C C C C 0 D D D D D D D D E E 0 F F G H J J K K M M 0 N P P P R R T T T T 0 U U U U V V V V0 V V 0 V V V W W W W W W W 0 W SW_VD_ TP TP TP UB XCRXL0BGA/A I/O H I/O H I/O H I/O J I/O J I/O K I/O K I/O W0 I/O T I/O0 U I/O T I/O T I/O W I/O V I/O U I/O W I/O T I/O K I/O L I/O0 L I/O M I/O M I/O M I/O N I/O N I/O N I/O V I/O U I/O R I/O0 W I/O T I/O V I/O U I/O W I/O U I/O W I/O P I/O P I/O P I/O0 R I/O R I/O R I/O T I/O U I/O V I/O U IN0 A0 IN D IN C IN B PORT_EN P TCK L TDI B TDO C TMS L I/O E I/O D I/O B I/O A I/O D I/O0 D I/O E I/O E I/O E I/O E I/O F I/O F I/O F I/O G I/O D I/O00 C I/O0 B I/O0 A I/O0 C I/O0 B I/O0 C I/O0 D0 I/O0 C0 I/O0 G I/O0 G I/O0 G IRQ TDO CLSN TRM_TXD TCK FRZ UDC_CTS TDI nsreset nhreset DSDI DSDO UDC_RTS UDC_RXD IP_B0 PTT SCL DSCK TP TP TP TP TP TP TP TP00 TP TP TP TP TP TP TRM_RXD TMS PPC_TMS MUTE_A MUTE_B C 0pF U TLCD Out Vcc In Out In In In SW_VD_0 R.k R k R 00k C 00pF C 00pF C 00pF C 00pF CR 00 Q MMBT0TT R0 K R SW_VD_0 R0 CR0 CR R R0 R CR CR ON_OFF_SW IP_B Vol Control Buffer Microphone OPTION SELECT BUFFER R 0k SW_VD_ Battery Voltage Sense R 0 R 0 CR CR CR CR CR E_RXD E_TXD SW_VD_ DSDI DSDO DSCK nhreset nsreset IP_B0 IP_B TP0 TP0 TP0 TP0 R 00K UA OPA0 R 00K SW_VA_0 VA_REF C 0.0uF SW_VD_ R 00K R 00K L 0.uH L 0.uH R K 000 USER INTERFACE BOARD VER B SCHEMATIC (PAGE OF ) Version with EFJ SEM

151 000 USER INTERFACE BOARD VER B TOP VIEW Version B Board (see Section.) Version with EFJ SEM

152 000 USER INTERFACE BOARD VER B BOTTOM VIEW Version with EFJ SEM

153 J CON0_OE/A EB_D GPIO_ EB_D EB_D EB_A EB_D0 EB_A GPIO_ EB_D EB_D GPIO_ EB_CS EB_D EB_A0 GPIO_0 EB_WE0 EB_D UNSW_VD_ In SW_BATT In SW_VD_ In SW_VA_0 In EB_nOE POWER_HOLD nlock_in MOSI RFSPIEN DSP_HINT nhreset R 0K UNSW_VD_ U KAPWR A VDDSYN B RSTCONF C PORESET B IRQ N IRQ/RSV D IRQ/DP0 C IRQ/DP D IRQ/DP D IRQ/DP C IRQ N IP_B0/IWP0/VFLS0 A IP_B/IWP/VFLS C IP_B/IOIS_B/AT D IP_B/IWP/VF A IP_B/LWP0/VF0 B IP_B/LWP/VF C IP_B/DSDI/AT0 C IP_B/PTR/AT D FRZ/IRQ A0 OP/MODCK/STS D OP/MODCK/DSDO B TRST P TCK/DSCK T TMS R TDI/DSDI R WAIT_B C KR/RTY/IRQ/SPKO B UPWAITA/GPL_A/AS D E WE0/BS_AB0/IORD D WE/BS_AB/IOWR E WE/BS_AB/PCOE D WE/BS_AB/PCWE F J VDDL A VDDL G XFC B TDO/DSDO N VDDL J VDDL T VSSSYN A VSSSYN A XTAL A EXTAL A D0 M D L D J D J D L D H D F D E D M D K D0 K D K D M D M D J D J D H D K D H D G D0 G D F D H D L D F D G D E D L D F D E D0 D D E GPL_A C EXTCLK A CLKOUT D ALE_B/DSCK/AT B GPL_A/GPL_B/CS D GPL_A/GPL_B/CS C GPL_A0/GPL_B0 E TEXP D SRESET B HRESET B IRQ0 N UPWAITB/GPL_B B N N P P0 C.nF C 0uF XPC0DEPBGA/A VDD E VDD E VDD E VDD E VDD E VDD E0 VDD E VDD E VDD F VDD0 F VDD G VDD G VCC H VDD H VDD J VDD J VDD K VDD K VDD L VDD0 L VDD M F F F F F0 F G G G 0 G G0 G H H H H H0 H J 0 J J J J0 J K K K K K0 0 K L L L L L0 L VDD M VDD M VDD M VDD M VDD M0 VDD M VDD M R 0M C0 0.uF. MHz R K L.uH EB_WE0 EB_WE SW_VD_ SW_VD_ SW_VD_ W_VD_ DSCK UIB_IRQ nsreset IRQ0 nhreset RSTCONF MODCK IP_B IP_B IP_B IP_B IP_B DSDI IRQ FRZ IRQ DSP_HINT PORESET IRQ MODCK nkr/nretry IP_B0 FIPS_IRQ PPC_TMS WAIT_B IRQ DSDO IP_B UPWAITB IP_B EB_WAIT Y C pf C pf BB A BG C0 BR B RD/WR C TEA C TSIZ0/REG F TSIZ E BURST B0 BDIP/GPL_B A TS D0 TA A BI B BR EB_R/nW BI TS TA TEA A G A H A0 G A F A M A N A N A M A0 L A M A M A L A L A L A K A K A G A K A0 J A J A G A H A H A H A F A K PD N PD P PD P PD R PD R PD T PD P PD0 T PD N PD R PD P PD T PD R CS0 D CS A CS B CS A CS B CS D CS/CE_B C CS/CE_B B A C C EB_CS0 GPIO_ GPIO_ EB_CS GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ EB_CS GPIO_0 GPIO_ EB_CS GPIO_[:] R 0 R 0 R 0 R 0 R 0 TXD/PA R SMRXD/LTXDA/PA N0 RXD/PA R USBOE/PA R USBRXD/PA P LRQA/LST/PB R LST/PB N RTS/LST/PB P LST/PB R SMSYN/SDACK/PB R SMSYN/SDACK/PB T0 RXD/SMRXD/PB T TXD/SMTXD/PB N BRGO/ICSCL/PB P BRGO/ICSDA/PB T BRGO/SPIMISO/PB T RXD/SPIMOSI/PB P TXD/SPICLK/PB0 P SPISEL/PB N TIN/LTCLKA/BRGO/CLK/PA T TIN/TOUT/CLK/PA P TIN/LRCLKA/BRGO/CLK/PA T SMTXD/LRXDA/PA T CD/LRSYA/PC T CTS/SDACK/LTSYA/PC P USBTXN/PC N USBTXP/PC T TGATE/CD/PC N CTS/PC R USBRXN/TGATE/PC0 P LST/LRQA/PC T RTS/LST/PC P LST/RTS/DREQ/PC T USBRXP/PC R0 LST/DREQ0/PC R TIN/TOUT/CLK/PA R UDC_RTS E_TCLK UDC_RXD MISO POWER_HOLD TRM_TXD OPT_SEL BB TENA TRM_RXD ON_OFF_IND E_RXD CLSN MOSI IRQ ISW_IRQ nlock_in RENA SCL UDC_TXD SDA TONE_SIG E_TXD UDC_CTS RFSPIEN L L L L L L L L L L L L0 L L L L L0 L0 L0 L0 L L0 L0 L L L0 L0 L00 L L0 L0 L L L L L L L0 L EB_D[0:] EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A0 EB_A0 EB_A EB_A EB_A EB_A EB_A EB_A EB_A EB_A OE/GPL_A/GPL_B C EB_nOE U SZPX UC LCX 0 UD UA LCX R.K SW_VD_ SW_VD_ UB LCX EB_D EB_D EB_D EB_D EB_D0 POWER PC MICROPROCESSOR U A0 A A A A A A B A B A C A C A D A H A H A0 H A H A G A G A F IO F IO E IO D IO C IO C IO D IO E IO F IO F IO G IO B IO C IO0 C IO F IO G IO0 B BLE A BHE B E VSS D VSS E CE B WE G OE A A F A E D G H U A0 A A A A A A B A B A C A C A D A H A H A0 H A H A G A G A F IO F IO E IO D IO C IO C IO D IO E IO F IO F IO G IO B IO C IO0 C IO F IO G IO0 B BLE A BHE B E VSS D VSS E CE B WE G OE A A F A E A D G H EB_A EB_A EB_A0 EB_D0 EB_A0 EB_A EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_D EB_A EB_A EB_A EB_D EB_D EB_D EB_A EB_A EB_A EB_A0 EB_A EB_A EB_A EB_D EB_A EB_D EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_D EB_A EB_A EB_A EB_D EB_A EB_D0 EB_A EB_A EB_A0 EB_A EB_A EB_D0 EB_D EB_D EB_D0 EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_D EB_WE EB_WE EB_WE0 K x SRAM K x SRAM R 0K R 0K R 0K R 0K R K R 0K R K R 0K R R0 R.K R Not Used R 0K R 0K R 0K R Not Used R.K R0 K R 0K R 0K R 0K R.K R 0K R K R0.K R 0K R0 0K R 00K R 0K R 00K SW_VD_ BR TEA IP_B MODCK DSCK IP_B IRQ IP_B IRQ IP_B0 nkr/nretry UIB_IRQ RSTCONF EB_WAIT UPWAITB IRQ TA BB IP_B WAIT_B FIPS_IRQ IRQ0 BI IP_B TS IP_B DSDI MODCK IP_B 0K C 0.uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.uF C 0.uF C 0.0uF C 0.0uF C 0.0uF SW_VD_ UNSW_VD_ TO LOGIC BOARD TO/FROM SHEET OF GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ SW_VD_ E_RCLK MUTE_A MUTE_B SPICLK OPT_SEL R0 R0 0K U MxMxFLASHFBGA/A A0 G A F A E A C A D A F A E A C A D A C A0 E A F A D A C A E DQ J DQ H DQ J DQ K DQ G DQ K DQ K DQ G DQ K DQ G DQ H DQ J DQ0 H DQ H DQ/A J DQ0 G A E A A A F VCC J RESET D VSS K VSS K CE H WE C OE J BYTE H RY/BY C A F A G A D WP/ACC D A0 F M A A B B B L 0 L L L M M M E EB_A EB_A0 EB_A EB_A EB_D EB_A EB_D EB_A EB_D EB_A EB_D EB_D EB_D EB_D EB_D EB_A EB_A EB_A0 EB_A EB_D EB_D0 EB_A EB_A EB_A EB_A EB_A EB_A EB_D EB_A EB_A EB_A0 EB_D0 EB_D EB_D EB_A EB_D EB_D EB_A SW_VD_ SW_VD_ 0K M x FLASH EB_CS LCX SZPX VD_ R 0K UNSW_VD._ U (Not Used) EB_R/nW EB_R/nW EB_nOE EB_nOE EB_CS EB_WE0 EB_nOE EB_CS0 0.0uF C 0.0uF C SW_VD_ R 00K R 00K R 00K nhreset Q MMBT0TT Q MMBT0TT 0 0 EB_WE0 EB_CS SW_VD_0 In GPIO_ GPIO_ EB_R/nW EB_R/nW EB_nOE nhreset EB_WAIT AUDIO_OUT_M AUDIO_OUT_P AUDIO_IN_M AUDIO_IN_P ON_OFF_SW ISW_IRQ GPIO_ Ferrite Inductors Ferrite Inductors C.uF SW_VA_0 C 0.0uF SW_VD_0 C 0.0uF C 0.0uF C0 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C 0.0uF C0 0.0uF C 0.0uF C 0.0uF C 0.uF C0 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.0uF C 0.uF C 0.0uF C 0.uF C 0.0uF C0 0.uF C 0.0uF nlock_in VCC D VCC E CE A A H UNSW_VD_ EB_A R 0 A VCC D VCC E A H UNSW_VD_ EB_A C 0.0uF C 0.0uF.uF C C 0.0uF C 0.0uF C 0.0uF C0 0.0uF C 0.0uF FIPS_CS AUDIO_IN_P SPICLK ON_OFF_SW AUDIO_OUT_P ISW_IRQ AUDIO_OUT_M AUDIO_IN_M EB_WAIT SPICLK FIPS_CS MISO FIPS_IRQ FIPS_CS EMC_WAKEUP PORESET PORESET RENA EMC_WAKEUP 000 USER INTERFACE BOARD VER B SCHEMATIC (PAGE OF ) Version with Motorola UCM Version B Board (see Section.)

154 R 0K R K R 0K UA XCRXL0BGA/A I/O E I/O E I/O F I/O F I/O F I/O F I/O G I/O G I/O G I/O0 H I/O B I/O B I/O B I/O A I/O A I/O C I/O A I/O E I/O D I/O0 A I/O H I/O H I/O H I/O J I/O J I/O J I/O K I/O K I/O K I/O0 L I/O E I/O D I/O A I/O C I/O B I/O A I/O A I/O B I/O D I/O0 L I/O L I/O M I/O M I/O M I/O N I/O N I/O N I/O N I/O U0 I/O0 T0 I/O W I/O U I/O T I/O W I/O U I/O T I/O V I/O U I/O P I/O0 P I/O R I/O R I/O R I/O R I/O R I/O T I/O T I/O U I/O T I/O0 W I/O T I/O R I/O W I/O U I/O V I/O T I/O V I/O W I/O B I/O0 C I/O A I/O B I/O C I/O A R 0K R 0K SW_VD_ SW_VD_ AUX_ CHNL_0 SCL TOG_0 DTMFCOL_ RX CHNL_ DTMFCOL_0 EMER DTMFCOL_ UIB_IRQ CHNL_ BACKLT_0 DTMFROW_ BACKLT_ DTMFROW_ SDA TX DTMFROW_ AUX_ DTMFROW_0 nseop CHNL_ AUX_ R % C nf U MA/A E0 E SCL WC SDA VCC VSS SW_VD_ R K SW_VD_ R 0K Q MMBT0TT K R.K R.K R 0K R 0K R.K SW_VD_ OPT_SEL SRC_SEL OPT_SEL R0 00 R M Y LTC V OUT SET DIV C nf SW_VD_ UDC_TXD CR CR CR R Q MMBT0TT 000 SW_VD_0 SCL SDA PTT S F R 0 R 0 S LEFT R 0 S DOWN R 0 R 0 S UP S F R 0 S RIGHT SW_VD_0 NAVCOL_0 NAVROW_ NAVROW_ NAVROW_0 NAVCOL_ R 0 R 0 R 0 S S 0 R 0 R 0 R 0 S0 S R 0 S S R 0 S S * DTMFROW_ DTMFROW_ DTMFCOL_0 DTMFROW_0 DTMFCOL_ DTMFROW_ DTMFCOL_ R0 K S S # R0 0 S S SW_VD_0 R 0 R 0 R 0 R R R R R R K K K K K K DTMF KEYPAD EXTSPKR_M TENA OPT_SEL EXTSPKR_P E_TCLK E_RCLK RENA RX_DATA EXT_MIC TX_DATA OPT_SEL R 0 CR R 0 CR R 0 R 0 R 0 J FKZ 0 BZXCVLT R 0 CR SW_BATT TO ACC JK FLEX FKZ CHNL_ CHNL_0 CHNL_ TOG_ TOG_0 ON_OFF_SW CHNL_ J J 0 R0 0K R0 0K R0 0K R 0K R0 0K R 0K R0 0K SW_VD_ TO TOP FLEX U0 OPA0 C 0.0uF C 00pF C0 0.0uF SW_VD_ VOL_CTRL J FKZ 0 R 0K SW_VD_ PTT AUX_ AUX_ AUX_ R 0K R 0K R 0K FPZ 0 C0.uF C 0.0uF C0.uF C0 uf C.uF C0.uF SPICLK GPIO_ MOSI C0 uf C0 uf C0 uf C0 uf TO PTT SW FLEX TO LCD Q MMBT0TT R CR A C R 00K SW_VD_0 RX_LED TX_LED Q MMBT0TT A C R 00K TX_LED RX_LED UC OPA0 0 R 00K R 00K R 00K R 00K C 0.uF R0 0K R K R 00K C.0uF C 0.0uF R 00K C 0.uF R 00K R K UD OPA0 UB OPA0 R K R 00K C0 0.uF R 0K VA_REF VA_REF SW_VA_0 AUDIO_OUT_P TONE_SIG VOL_LVL AUDIO_OUT_M U OPA0 SW_VA_0 R 0K U LMM VIN VDD HP_SENSE DC/SD VO VO BYPASS C 0.uF R 0K Q MMBT0TT R 00K MMBT0TT SW_VA_0 SW_VA_0 EXTSPKR_P MUTE_A EXTSPKR_M nseop Q C 0.uF Q0 MMBT0TT INTSPKR_P U LMM VIN VDD HP_SENSE DC/SD VO VO BYPASS R 00K INTSPKR_M SW_VA_0 MUTE_B R 00K C 0.0uF C 0.uF R0 00K R.K R 00K Q MMBT0TT UC OPA0 0 R 00K C 0.0uF C0 0pF R 00K UB OPA0 R 00K R0 00K C 0pF 0pF U NLAS/A COM CS NO VCC SW_VA_0 SW_VA_0 VA_REF VA_REF SRC_SEL AUDIO_IN_M AUDIO_IN_P EXT_MIC UA OPA0 R 00K R 00K R 00K C00 0.0uF R0 00K R 00K UD OPA0 R K SW_VA_0 VA_REF VA_REF CR BAWLT R 00K R0 0K R 00K R 0K C 0.0uF Q MMBT0TT SW_VD_ ON_OFF_SW R.K R 0K U0A OPA0 R 0K C 0.0uF U LTCLxMS CH0 CH VCC CLK DIN DOUT CS R 0K GPIO_ GPIO_ GPIO_ SW_VD_ SW_VD_ MISO SPICLK MOSI VOL_CTRL 0.V0.V.V.V R 0K U TLVI/A REFIN VDD DIN SCLK A CS OUT FS C 00pF SW_VD_0 VOL_LVL R 00K % R 0K SW_BATT EMER INTERNAL SPEAKER AMP EXTERNAL SPEAKER AMP AUDIO_OUT_P AUDIO_OUT_M TONE_SIG R K R0 K R K R K R K UIB_IRQ UDC_TXD AUDIO_IN_P AUDIO_IN_M GPIO_ GPIO_ PROGRAMMABLE LOGIC DEVICE (PLD) K x EEPROM BACKLIGHT TO/FROM SHEET OF MK0 R 00K C 0pF C R 00K R0 00K INT_MIC R.K MIC_ C 0.uF VA_REF VA_REF IN/EXT MIC SEL SWITCH SPx OHM SPEAKER SW_VD_ OSCILLATOR Bat Volt/Vol Ctrl A/D Converter Vol Ctrl D/A Converter ON_OFF_IND C 0.uF U MAXEAE C EN Vcc V V C Forceoff C ROut RIn TOut TN C Invalid 0 RS TRANSCEIVER Forceon SW_VD_ C 0.uF C 0.uF C 0.uF R 0K SW_VD_0 RX TX UC XCRXL0BGA/A VCC A VCC B0 VCC C VCC C VCC D VCC D VCC F VCC J VCC L VCC0 P VCC T VCC U VCC U VCC V VCC V VCC V R R R A A A A A A B B B 0 B E E E E E0 E E E G 0 G H H J J K K L L M 0 M N N R R R R0 B B C C C C C C C 0 D D D D D D D D E E 0 F F G H J J K K M M 0 N P P P R R T T T T 0 U U U U V V V V0 V V 0 V V V W W W W W W W 0 W SW_VD_ TP TP TP UB XCRXL0BGA/A I/O H I/O H I/O H I/O J I/O J I/O K I/O K I/O W0 I/O T I/O0 U I/O T I/O T I/O W I/O V I/O U I/O W I/O T I/O K I/O L I/O0 L I/O M I/O M I/O M I/O N I/O N I/O N I/O V I/O U I/O R I/O0 W I/O T I/O V I/O U I/O W I/O U I/O W I/O P I/O P I/O P I/O0 R I/O R I/O R I/O T I/O U I/O V I/O U IN0 A0 IN D IN C IN B PORT_EN P TCK L TDI B TDO C TMS L I/O E I/O D I/O B I/O A I/O D I/O0 D I/O E I/O E I/O E I/O E I/O F I/O F I/O F I/O G I/O D I/O00 C I/O0 B I/O0 A I/O0 C I/O0 B I/O0 C I/O0 D0 I/O0 C0 I/O0 G I/O0 G I/O0 G IRQ TDO CLSN TRM_TXD TCK FRZ UDC_CTS TDI nsreset nhreset DSDI DSDO UDC_RTS UDC_RXD IP_B0 PTT SCL DSCK TP TP TP TP TP TP TP TP00 TP TP TP TP TP TP TRM_RXD TMS PPC_TMS MUTE_A MUTE_B C 0pF U TLCD Out Vcc In Out In In In SW_VD_0 R.k R k R 00k C 00pF C 00pF C 00pF C 00pF CR 00 Q MMBT0TT R0 K R SW_VD_0 R0 CR0 CR R R0 R CR CR ON_OFF_SW IP_B Vol Control Buffer Microphone OPTION SELECT BUFFER R 0k SW_VD_ Battery Voltage Sense R 0 R 0 CR CR CR CR CR E_RXD E_TXD SW_VD_ DSDI DSDO DSCK nhreset nsreset IP_B0 IP_B TP0 TP0 TP0 TP0 R 00K UA OPA0 R 00K SW_VA_0 VA_REF C 0.0uF SW_VD_ R 00K L 0.uH L 0.uH R 00K R K 000 USER INTERFACE BOARD VER B SCHEMATIC (PAGE OF ) Version with Motorola UCM

155 000 USER INTERFACE BOARD VER B TOP VIEW Version B Board (see Section.) Version with Motorola UCM

156 000 USER INTERFACE BOARD VER B BOTTOM VIEW 0 Version with Motorola UCM

157 DB To Computer Serial Port Red Orn Wht Brn Blk Tx Data/USB DP Rx Data/USB DM _EN DSR CTS PROGRAMMING CABLE SCHEMATIC Part No UDC To Transceiver Accessory Jack 00 Test Cable Part No DB F Pin Numbering DB To Computer Serial Port Red Orn Wht Tx Data Rx Data RENA Ext Spkr UDC To Transceiver Accessory Jack UDC Pin Numbering Audio Jack TEST CABLE SCHEMATIC Part No. 0000

158 SECTION OBSOLETE BOARD SCHEMATICS AND LAYOUTS J0 Antenna Jack.V Battery Pack B J RF Input/ Output J B Bat Status A RF BOARD D Out D Out* SB Reset Bat Status ODC DA CE SPI Clk SPI Data Ref Osc En Synth CE Lock Detect Mod In 0 Unsw B Sw B Unsw B 0 PC0 Flex Cir NOTE: The following schematics and board layouts are for earlier versions of the Logic and User Interface (UI) boards. Use this information if you need to service earlier versions of the 00 transceiver. The board version number is indicated by the last two digits (.xx) of the 0 PC board number on the board. A00 LOGIC BOARD J J J D Out HCNTL0 D Out* HCNTL SB Reset HBIL Bat Status HPI_D 0 0 ODC DA CE SPI Clk SPI Data Ref Osc En Synth CE Lock Detect Mod In Unsw B Sw B Unsw B SW_VA_0 HPI_D HRDY HPI_D AUDIO_OUT_P HPI_D AUDIO_OUT_M HPI_D AUDIO_IN_M HPI_D0 AUDIO_IN_P HPI_D SW_BATT UNSW_VD_ HPI_D SPICLK H_R/nW MOSI HDS nsynsel ON_OFF_SW ndacsel ISW_IRQ LOGBRD_nRST RX_AUDIO_MUTE HDS SW_VD_0 H_nCS nroscsel ADSIC_nSEL RF_nLOCK RFSPIEN nhreset HINT POWER_HOLD SW_VD_ MK0 Microphone SP0 Speaker EB_A EB_A0 EB_A EB_D SW_VA_0 EB_D EB_WAIT EB_D AUDIO_OUT_P EB_D AUDIO_OUT_M EB_D AUDIO_IN_M EB_D0 AUDIO_IN_P EB_D SW_BATT UNSW_VD_ EB_D SPICLK EB_R/nW MOSI EB_nOE GPIO_ ON_OFF_SW GPIO_ ISW_IRQ GPIO_ GPIO_ EB_WE0 SW_VD_0 A00 USER INTERFACE (UI) BOARD EB_CS GPIO_ GPIO_0 nlock_n RFSPIEN nhreset DSP_HINT POWER_HOLD SW_VD_ MIC MIC Ext Spkr Ext Spkr OPT_SEL EXTSPKR_P EXT_MIC SW_BATT OPT_SEL EXTSPKR_M RX_DATA TX_DATA CTS RTR DSR _EN EMER CHNL_ CHNL_0 CHNL_ SW_VD_ ON_OFF_SW TOG_ CHNL_ Volume Control TOG_0 PTT Aux Aux Aux GPIO_ GPIO_ GPIO_ SPICLK MOSI SW_VD_ J 0 J 0 J 0 J 0 PC0 UDC Flex Circuit PC0 Top Flex Circuit PTT Flex Circuit Volume Pot R0 Opt Sel Ext Spkr Ext Mic Sw B Opt Sel Ext Spkr Rx Data D Tx Data CTS RTR DSR En DS0 DISPLAY (LCD) OnOff Sw 0 UDC (ACCESSORY) CONNECTOR A B SW Emergency Sw S0 Rotary Channel/Toggle Sw SW PTT Sw SW Opt Sw SW Opt Sw SW Opt Sw C C C OBSOLETE VERSION INTERCONNECT SCHEMATIC (Use With Revision UI Board)