Maintenance/ Discontinued

Transcription

1 ICs for TV AN5491K Synchronous signal and deflection distortion correction processing IC supporting I 2 C bus for HD, wide television Overview The AN5491K is a deflection processor IC for synchronous signal processing and screen distortion correction. It synchronizes with the input signal of High-vision, wide television, NTSC, PAL and VGA by the external binary input signal of them so that a multimedia television can be realized easily. Features Supports the multiple-point horizontal frequency (15.7 khz to 62.7 khz) Horizontal duty is controllable by external voltage. Built-in full functions for correction (Horizontal and vertical: 16 items) Over-current detection, shut-down and hold-down Applications High-vision televisions, Wide screen televisions and Projection televisions to ± ± SDIP042-P-0600A 36.8± Unit: mm 0.5± ± ± ± ±0.25 includes following four Product lifecycle stage. 1

2 AN5491K ICs for TV Block Diagram AGC V- EHT H- EHT Trapezoid EHT-DC EHT-AC V-out DEF GND Phase out EW out Corner level VGA I 2 L GND H-GND Lock det. H-out H-duty adj. H-AFC2 FBP in H-OSC H-POS EHT correction H H Lock f EW Phase V duty out det. H switch H-WID V-POS EHT-AC input out out Parallel POL out BOW H AFC2 H VCO Upper Lower V-S V-LIN Corner correction Counter BF V-SAW correction Phase crrection Trapezoid crrection 4 Counter PG Counter decode Ramp /AGC H-parabola V-amp. 5 V/I converter Counter input Trape 6 Counter Gain-SW V-AGC timing Latch-SW V-latch pulse Data latch Sync. DEF DAC H AFC1 V OSC VP slice I 2 C decode V-BLK gen. X-ray det. Shut down det. HP slice Ramp V-OSC VS2 VP in DEF V CC SCL SDA I 2 L V CC V-SAW in V-SAW lower V-SAW upper BLK out Comparator out Comparator in Comparator ref. Shut down includes following four Product lifecycle stage. H-V CC H-pulse in H-AFC1 2

3 ICs for TV AN5491K Pin Descriptions Pin No. Description Pin No. Description 1 H-AFC1 22 V-AGC 2 H-pulse input 23 EHT-DC input 3 H-V CC (6.2 V) 24 EHT-AC input 4 Shut down SW Comparator ref. () Comparator 27 VGA 7 Comparator output 28 V-output 8 BLK output 29 DEF GND -SAW slice voltage (High) 30 Phase output 10 V-SAW slice voltage (Low) V-SAW input 32 EW output 12 I 2 L V CC (5 V) 33 Corner slice voltage 13 I 2 C SDA input 34 I 2 L GND 14 I 2 C SCL input DEF V CC () 36 H-GND 16 V-pulse input 37 Lock det. 17 V-pulse output 38 H-output 18 V-OSC 39 H-duty H-AFC2 20 V-ramp 41 FBP input 21 Trapezoid correction voltage 42 H-OSC Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage V CC V CC1 5.6 V V CC2 10 Supply current I CC I CC1 24 ma I CC2 29 I 3 14 Power dissipation *2 P D 600 mw Operating ambient temperature * 1 includes following four Product lifecycle stage. T opr 20 to +70 C Storage temperature *1 T stg 55 to +150 C Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for T a = 25 C. *2: The power dissipation shown is for the independent IC without a heat sink in free air at T a = 70 C. 3

4 AN5491K ICs for TV Recommended Operating Range Parameter Symbol Range Unit Supply voltage V CC1 4.5 to 5.0 to 5.5 V V CC2 8.1 to 9.0 to 9.9 Electrical Characteristics at T a = 25 C DC characteristics Parameter Symbol Conditions Min Typ Max Unit Circuit current I CC1 I 12 V CC1 = 5 V, V CC2 = ma Circuit current I CC2 I 15 V CC1 = 5 V, V CC2 = ma Circuit current I CC3 I 3 V CC1 = 5 V, V CC2 =, ma V CC3 = Synchronizing signal processing Horizontal free-running oscillation f HO8 Pin 2: Without input, Pin 25: High khz frequency 1 [Divide-by-8] Pins 19, 26, 31, 35: Low Horizontal free-running oscillation f HO16 Pin 2: Without input khz frequency 2 [Divide-by-16] Pins 19, 25, 26, 31, 35: Low Horizontal free-running oscillation f HO32 Pin 2: Without input khz frequency 3 [Divide-by-32] Pin 19: High Horizontal output pulse duty cycle 1 τ HO1 Pin 2: Without input, Pin 39: 2 V µs [Divide-by-32] Pin 19: High Horizontal output pulse duty cycle 2 τ HO2 Pin 2: Without input, Pin 39: 5 V µs [Divide-by-32] Pin 19: High Horizontal high-level output voltage V FHH DC voltage for pin 38 high-level V Horizontal low-level output voltage V FHL DC voltage for pin 38 low-level V Horizontal output start voltage V FHS Minimum voltage of pin 3 to bec V ome f > 10 khz when horizontal oscillation output is 1 V[p-p] or more in divide-by-32 mode. Screen center variable range 1 t DH16 Pin 25: Low, µs [Divide-by-16] Pins 19, 26, 31, 35: High Change amount of phase difference between H P and H-out of Data 08: [00] to [1F] includes following four Product lifecycle stage. Screen center variable range 2 t DH32 Pin 19: Low, µs [Divide-by-32] Change amount of phase difference between H P and H out of Data 08: [00] to [1F] Horizontal input pulse threshold voltage V T2 Slice level of pin V Over-voltage protective operation V 4 Pin 4 voltage at I 4 = 50 µa V voltage 4

5 ICs for TV AN5491K Electrical Characteristics at T a = 25 C (continued) Parameter Symbol Conditions Min Typ Max Unit Deflection correction processing V P pulse for OSD low-level V LOSD V CC1 = 5 V, V CC2 = V V P pulse for OSD high-level V HOSD V CC1 = 5 V, V CC2 = V EHT-AC input pin voltage V 24 Pin 24: Open V Vertical input signal threshold voltage V TFV Pin 16: Input V Vertical free-running oscillation f VO Pin 16: Without input Hz frequency external R = 10 kω, C = 3.3 µf Typical vertical output amplitude V V V amplitude DAC: Typ V[p-p] Typical EW output amplitude V EW EW output amplitude for typical ver V[p-p] tical output amplitude = 1.25 V[p-p] Phase out amplitude V PHASE Side pin parallel, DAC: Typ V[p-p] Ramp waveform amplitude V RAMP f V = 50 Hz to 120 Hz V[p-p] AGC input and output current I AGC ma Service SW: ON time V 28SW Vertical output DC BLK pulse high-level V HBLK V BLK pulse low-level V LBLK V Vertical output amplitude V AMPmax V amplitude ratio between % variable ratio (max.) typ. max. Vertical output amplitude V AMPmin V amplitude ratio between % variable ratio (min.) typ. max. Vertical output DC variable amount (min.) V SHIFTmin Vertical DC: Typ. min V Vertical output DC variable amount (max.) V SHIFTmax Vertical DC: Typ. max V Vertical output trapezoidal waveform V TRAPmin Trapezoidal waveform correction: V correction variable amount (min.) Typ. min. Vertical output trapezoidal waveform V TRAPmin Trapezoidal waveform correction: V correction variable amount (max.) Typ. max. External trapezoidal waveform V V center voltage Vertical output center DC level V V EW output (min.) to parabolic V EWmin Parabolic amplitude: Min V[p-p] amplitude change EW output (max.) to parabolic V EWmax Parabolic amplitude: Max V[p-p] amplitude change EW output (min.) (DC) V EWmin Horizontal amplitude: Min V to horizontal amplitude change EW output (max.) (DC) V EWmax Horizontal amplitude: Max V to horizontal amplitude change EW output (bottom voltage) 1 V EDC1 EHT-DC: 5.0 V 3.8 V V to EHT-DC change Horizontal EHT: Max. EHT-AC gain: Min. includes following four Product lifecycle stage. 5

6 AN5491K ICs for TV Electrical Characteristics at T a = 25 C (continued) Parameter Symbol Conditions Min Typ Max Unit Deflection correction processing (continued) EW output (bottom voltage) 2 V EDC2 EHT-DC: 5.0 V 6.2 V V to EHT-DC change Horizontal EHT: Max. EHT-AC gain: Min. EW output (bottom voltage) 1 V EAC1 EHT-AC: 2.35 V 1.35 V V to EHT-AC change Horizontal EHT: Max. EHT-AC gain: Max. EW output (bottom voltage) 2 V EAC2 EHT-AC: 2.35 V 3.35 V V to EHT-AC change Horizontal EHT: Max. EHT-AC gain: Max. EW output parabolic DC level V 32 Typ V Parallelogram correction fluctuation 1 V UPH1 Parallelogram correction: V (upper side) Typ. min. Parallelogram correction fluctuation 2 V UPH2 Parallelogram correction: V (upper side) Typ. max. Parallelogram correction fluctuation 3 V BPH1 Parallelogram correction: V (lower side) Typ. min. Parallelogram correction fluctuation 4 V BPH2 Parallelogram correction: V (lower side) Typ. max. Bow shape correction fluctuation 1 V USD1 Bow shape correction: V (upper side) Typ. min. Bow shape correction fluctuation 2 V USD2 Bow shape correction: V (upper side) Typ. max. Bow shape correction fluctuation 3 V BSD1 Bow shape correction: V (lower side) Typ. min. Bow shape correction fluctuation 4 V BSD2 Bow shape correction: V (lower side) Typ. max. I 2 C interface SCL, SDA input threshold voltage V TH V CC1 = 5 V db Sink capacity at ACK V ACK I = 3 ma in case of pull-up resistor 0.4 V 1.6 Ω Maximum clock frequency f SCL 100 khz includes following four Product lifecycle stage. Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit DC characteristics AGC pulse width τ AGC 95 µs Ramp discharge current I RAMP1 3.6 ma Ramp charge current 1 I RAMP2 f = 120 Hz, Pin 4: 5.7 V 138 µa Ramp charge current 2 I RAMP3 f = 30 Hz, Pin 4: 7.5 V 32.9 µa 6

7 ICs for TV AN5491K Electrical Characteristics at T a = 25 C (continued) Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit DC characteristics (continued) BLK output amplitude V BLK V Vertical output drive current I 28 2 ma Vertical output amplitude fluctuation V V Difference of V CCmax V CCmin 0.1 V with supply voltage V CC Vertical output DC fluctuation V 28 Difference of V CCmax V CCmin 1.0 V with supply voltage V CC EW output amplitude fluctuation V EW Difference of V CCmax V CCmin 0.1 V with supply voltage V CC EW output DC fluctuation V 32 Difference of V CCmax V CCmin 1.0 V with supply voltage V CC Synchronizing signal processing Horizontal free-running oscillation f HO15 Pin 2: Without input, Pin 19: Low khz frequency [Divide-by-15] Pins 25, 26, 31, 35: High Horizontal output pull-in range f HP8 Pin 2: Without input, Pin 25: High ±2 000 ±2 600 Hz [Divide-by-8] Pins 19, 26, 31, 35: Low Comparator detection operation voltage V 6 Pin 6: Minimum voltage to become high, Pin 5: 6.2 V Lock detection output voltage V 37 V 37 in horizontal AFC lock mode Lock detection charge and discharge I LOCK DC measurement in divide-by-32 ±0.8 ma current FBP (AFC2) slice level V TFBP Minimum voltage of pin 41 at V which AFC operates. Horizontal AFC µ µ DC measurement in divide-by µa/µs Horizontal VCO β β Slant of β curve near f = 15.7 khz 1.9 Hz/mV FBP allowable range 1 t FBP8 Time from H-out rise to FBP 3 9 µs [Divide-by-8] center FBP allowable range 2 t FBP16 Time from H-out rise to FBP 4 13 µs [Divide-by-16] center FBP allowable range 3 t FBP32 Time from H-out rise to FBP 6 20 µs [Divide-by-32] center AFC1 reference current 1 I AFC1 Data 0C = "11" (D1, D0) 0.82 ma AFC1 reference current 2 I AFC2 Data 0C = "01" (D1, D0) 1.1 ma AFC1 reference current 3 I AFC3 Data 0C = "10" (D1, D0) 1.5 ma AFC1 reference current 4 I AFC4 Data 0C = "00" (D1, D0) 2.0 ma Horizontal output pull-in range 1 f HP16 Pin 2: Without input ±1 000 ±1 300 Hz [Divide-by-16] Pins 19, 25, 26, 31, 35: Low Horizontal output pull-in range 2 f HP32 Pin 2: Without input ±500 ±650 Hz [Divide-by-32] Pin 19: High includes following four Product lifecycle stage. 7

8 AN5491K ICs for TV Electrical Characteristics at T a = 25 C (continued) Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit Deflection correction processing Vertical output S-shape variable V SC1 Vertical S-shape: 28 % ratio 1 Ratio of min. max. Vertical output S-shape variable V SC2 Vertical S-shape: Ratio of min. 1.5 % ratio 2 max. (Change of V-out 40% to 60% point) Vertical output (upper side) V ULIN1 Vertical linearity (upper side): +12 % linearity variable ratio 1 Typ. max. Vertical output (upper side) V ULIN2 Vertical linearity (upper side): 10 % linearity variable ratio 2 Typ. min. Vertical output (lower side) V BLIN1 Vertical linearity (lower side): +9 % linearity variable ratio 1 Typ. max. Vertical output (lower side) V BLIN2 Vertical linearity (lower side): 11 % linearity variable ratio 2 Typ. min. Vertical output V EDC1 EHT-DC = 5.0 V 3.8 V 30 % EHT-DC change 1 Vertical EHT: Max., EHT gain: Max. Vertical output V EDC2 EHT-DC = 5.0 V 6.2 V +25 % EHT-DC change 2 Vertical EHT: Max., EHT gain: Max. Vertical output V EAC1 EHT-AC = 2.35 V 1.35 V 12 % EHT-AC change 1 EHT: Max., EHT gain: Max. Vertical output V EAC2 EHT-AC = 2.35 V 3.35 V +12 % EHT-AC change 2 EHT: Max., EHT gain: Max. EW output (min.) V TRAPmin Trapezoidal SW: On, 40 % to trapezoidal waveform change Trapezoidal: Typ. min. EW output (max.) V TRAPmax Trapezoidal SW: On, +40 % to trapezoidal waveform change Trapezoidal: Typ. max. EW output (min.) to upper corner V UCmin Upper corner: Typ. min. 45 % trapezoidal waveform change Corner slice voltage: 1 V EW output (max.) to upper corner V UCmax Upper corner: Typ. max. +45 % trapezoidal waveform change Corner slice voltage: 1 V EW output (min.) to lower corner V BCmin Lower corner: Typ. min. 45 % trapezoidal waveform change Corner slice voltage: 1 V EW output (max.) to lower corner V BCmax Lower corner: Typ. max. +45 % trapezoidal waveform change Corner slice voltage: 1 V External trapezoidal waveform correction V ETR1 External trapezoidal correction: 40 % fluctuation 1 (Parabolic amplitude) 3 V 2 V External trapezoidal waveform correction V ETR2 External trapezoidal correction: +40 % fluctuation 2 (Parabolic amplitude) 3 V 4 V includes following four Product lifecycle stage. 8

9 ICs for TV AN5491K Electrical Characteristics at T a = 25 C (continued) Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. I 2 C interface Parameter Symbol Conditions Min Typ Max Unit 3, 4, 5, 6-bit DAC DNLE L1 1LSB = LSB/step {Data(max.) Data(00)}/7,15,31,63 7-bit DAC DNLE (Except for 40) L2 1LSB = {Data(max.) Data(00)}/ LSB/step 7-bit DAC DNLE (40 only) L3 1LSB = {Data(max.) Data(00)}/ LSB/step Terminal Equivalent Circuits Pin No. Equivalent circuit Description Voltage 1 AFC1: Horizontal frequency detection pin 3.15 V Pin for adjusting the frequency of horizontal input pulse and the internal refere- 4.3 V 27 kω 1 nce pulse. Connect a lag lead filter. 5.3 V DC approx. 4.3 V 2 H-pulse in: AC 3 V 100 kω Horizontal synchronizing signal input pin Polarity is as shown in the right figure (Negative). Slice level is 1.5 V. 1.5 V 2 Input polarity is one polarity only 1 kω 1.5 V (not corresponding to both polarities). H rate 3 12 V V CC : DC Horizontal system power supply () pin 330 Ω Connect an external zener 3 includes following four Product lifecycle stage. 4 Shut down: DC 28 kω 28 kω Control pin for shut-down Normal: GND Horizontal output stops (GND) if a voltage 1 V BE and over (more than approx V) 4 is applied to the pin. 9

10 AN5491K ICs for TV Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 5 Comparator ref.: DC Reference voltage input pin for comparator Attach zener diode externally (approx. 6.2 V) (Usable as reference voltage for hold-down) 5 1 kω 6 Comparator: DC Input pin for comparator detection (Usable as pin for hold-down detection) kω 1 kω 7 Comparator out: DC Comparator detection output pin Normally: 25 kω Connect pull-up resistors outside the IC. High (usable as hold-down control pin) Note) Use under 400 µa or less kω 8 BLK out: DC Blanking pulse output pin At BLK: High Normally: Low At BLK: High (5 V) kω includes following four Product lifecycle stage. 9 Upper side slice: DC Upper side slice voltage input pin for BLK pulse generation Upper side Ω 145 Ω BLK 10

11 ICs for TV AN5491K Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 10 Lower side slice: DC Lower side slice voltage input pin for BLK Pulse generation Ω 11 V-SAW in: AC V-SAW input pin for BLK pulse generation 25 µa Ω 12 V CC : DC Power supply (5 V) pin for DAC/I 2 L 5 V Connect a pass capacitor (0.01 µf) between pin 12 and GND (pin 19) V SDA: I 2 C data input pin 20 µa 5 V 13 1 kω 14 5 V SCL: I 2 C clock input pin 20 µa 14 1 kω Lower side BLK GND includes following four Product lifecycle stage. 5 V GND 15 V CC : DC Pin for deflection system power supply () Connect a pass capacitor between the pin and GND. 11

12 AN5491K ICs for TV Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 16 V-pulse in: AC 290 Ω Vertical sync. signal input pin (Pulse) 25 µa Polarity is as shown in the right figure (Negative) 1.5 V 16 Slice level is 1.5 V. 30 kω 0 V Input polarity is only one polarity V rate 1.5 V (Not correspond to both polarities) 290 Ω 17 V-pulse out: AC Vertical sync. signal output pin (Pulse) If vertical sync. signal input is present: 2.5 V 17 Outputs the pulse synchronized with input V. Not present: Outputs free-running V pulse. 55 kω (Usable for microcomputer OSD control) 0 V V rate 18 5 V V-OSC: AC 36 kω Vertical oscillation pin Connect CR. Free-running oscillation when there is no 5.8 V 18 1 kω input. 3.1 V 50 µa V rate V 32: DC Horizontal free-running oscillation frequency 150 kω control pin To be used by high/low control. 19 Input is controlled by open collector output. 30 kω 30 kω 30 kω includes following four Product lifecycle stage. 20 9V V-ramp pin: AC 1kΩ The pin for generating reference V sawtooth waveform for IC inside. Connect an 0.22 µf mylar capacitor. 2.5 V 20 V rate 0 V 2.5V 12

13 ICs for TV AN5491K Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 21 External trapezoidal waveform: DC The pin for controlling trapezoidal wavefo- 2 V to 4 V 25 µa rm compensation from outside. Used by linking to V-position shift (at AC coupling). typ V 145 Ω 22 V-AGC: DC Vertical AGC pin 500 Ω AGC pin to make a vertical output amplitude constant. 22 Connect 3.3 µf tantalum capacitor. 500 Ω 145 Ω 23 EHT-DC: DC Pin for extremely high-tension compensation (EHT) V DC-coupled to pin. Operating range: 3.8 V to 6.2 V 5.45 V 24 EHT-AC AC Pin for extremely high-tension compensation 25 µa 25 µa AC-coupled to pin V in an open mode Ω 145 Ω Operating range: 1.35 V to 3.35 V 25 8: DC Horizontal free-running oscillation frequency 150 kω control pin 25 To be used by high/low control. Input is controlled by open collector output. includes following four Product lifecycle stage. 13

14 AN5491K ICs for TV Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 26 4: DC Horizontal free-running oscillation frequency 150 kω control pin To be used by high/low control. 26 Input is controlled by open collector output. 27 V-FB: DC Forced progressive mode pin To be used by high/low control. At high: Multi-point mode kω At low: Progressive mode 28 V-out: AC 300 Ω V sawtooth waveform output pin 5 Typ V[p-p] Ω Ω 29 GND: DC GND pin for deflection-system circuit () GND 30 Phase out: AC Pin for side pin (Bow shape) correction, parallelogram correction and control pulse output. DC 290 Ω Connect to H-AFC2 pin via 1 µf (non- approx. 3.7 V 30 polarity) capacitor. includes following four Product lifecycle stage. 290 Ω 0 V Max. 300 mv[p-p] 14

15 ICs for TV AN5491K Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 31 2: DC Horizontal free-running oscillation frequency 150 kω control pin 31 To be used by high/low control. Input is controlled by open collector output. 32 EW out: AC Parabolic waveform output pin 500 Ω kω 300 Ω 10 kω 1.5 V 33 Corner slice: DC The voltage to set a slice point of upper and 50 µa 50 µa lower corner correction. The correction gain can be controlled inde- Externally set 33 pendently by I 2 C bus for upper and lower, at 0 VDC to respectively VDC 34 GND: GND pin for 5 V system (I 2 C/I 2 L) DC GND 35 1: DC 150 kω Horizontal free-running oscillation frequency control pin 35 To be used by high/low control. 10 kω 36 GND: GND pin for system DC (Horizontal system) GND 37 Lock det.: DC 200 Ω Horizontal lock detection pin Connect µf and 1 MΩ between the At lock mode: 820 µa pin and GND. 6 V µa At unlocked mode: GND includes following four Product lifecycle stage. 15

16 AN5491K ICs for TV Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 38 H-out: AC Horizontal output pin The length of high-period can be adjusted ma by a separate pin. 15 kω GND 38 H rate 40 kω 39 H-duty: DC Pin for controlling the length of high-period 1 V to 5 V 124 kω of horizontal output pulse. 39 Apply DC voltage from the outside. 10 kω 124 kω 40 AFC2: DC Horizontal phase detection pin 1.5 V to 4.5 V 1. Pin for controlling phase difference between horizontal output pulse and FBP. 40 Phase out waveform is also connected to this pin via capacitor. 3. Connect µf between this pin and GND. 41 FBP input pin: AC Slices at 1. (in the IC) and then uses 50 µa as AFC2 control pulse kω Do not input any signal under GND inside the IC. GND kω H-OSC: AC Reference oscillation pin (500 khz) 2.25 V Connect CERALOCK (CSB500F48), and 270 Ω temperature guaranteed (N750) 220 pf 270 Ω capacitor in series between this pin and 0.5 V[p-p] 42 GND. 300 Ω 200 µa 3.0 V 100 µa 10 kω includes following four Product lifecycle stage. 16

17 ICs for TV AN5491K Application Circuit Example AGC 3.3 µf Trapezoid EHT DC EHT AC V-out DEF GND Phase out EW out Corner level V VGA I 2 L GND H-GND Lock det. H-out 6.5V H-duty adj. H-AFC2 FBP in H-OSC 1 MΩ 0.22 µf Ramp V-OSC VS2 VP in DEF V CC SDA I 2 L V CC V-SAW in V-SAW lower V-SAW upper BLK out Comparator out Comparator in Comparator ref kω Shut down 1 µf 40 3 H-V CC 330 Ω 12 V 41 2 H-pulse in 220 pf *1 22 µf 620 Ω 42 1 H-AFC µf 3.3 µf 10 kω 4.7 kω 4.7 kω 5 V includes following four Product lifecycle stage. SCL µf *1: Horizontal oscillator TAFCSB500F48 [Murata Manufacturing Co. Ltd.] 17

18 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. includes following four Product lifecycle stage.