PMm 2 : R&D on triggerless acquisition for next generation neutrino experiments

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1 Journal of Instrumentation OPEN ACCESS PMm 2 : R&D on triggerless acquisition for next generation neutrino experiments To cite this article: J E Campagne et al View the article online for updates and enhancements. Related content - Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays S. Blin, S. Callier, S. Conforti Di Lorenzo et al. - Digital part of PARISROC2: a photomultiplier array readout chip F Dulucq, S Conforti Di Lorenzo, A El Berni et al. - Upgrade of the ATLAS hadronic Tile Calorimeter for the High luminosity LHC A. Solodkov This content was downloaded from IP address on 25/08/2018 at 08:39

2 PUBLISHED BY IOP PUBLISHING FOR SISSA TOPICAL WORKSHOP ON ELECTRONICS FOR PARTICLE PHYSICS 2010, SEPTEMBER 2010, AACHEN, GERMANY RECEIVED: October 30, 2010 REVISED: December 10, 2010 ACCEPTED: December 20, 2010 PUBLISHED: January 13, 2011 PMm 2 : R&D on triggerless acquisition for next generation neutrino experiments J.E. Campagne, b S. Conforti Di Lorenzo, b S. Drouet, a D. Duchesneau, c F. Dulucq, b N. Dumont-Dayot, c A. El Berni, b J. Favier, c A. Gallas, b B. Genolini, a K. Hanson, d N. Hauchecorne, a R. Hermel, c M. Imre, a B. Ky, a C. de La Taille, b J. Maltese, a A. Maroni, a G. Martin-Chassard, b T. Nguyen Trung, a J. Peyré, a J. Pouthas, a E. Rindel, a P. Rosier, a L. Séminor, a J. Tassan, c C. Théneau, a E. Wanlin a,1 and A. Zghiche c a Institut de Physique Nucléaire d Orsay, IPNO-IN2P3-CNRS, Université Paris-Sud, Orsay Cedex, France b Laboratoire de l Accélérateur Linéaire, Omega-LAL, LAL-IN2P3-CNRS, Université Paris-Sud, Orsay Cedex, France c Laboratoire d Annecy-le-Vieux de Physique des Particules, LAPP-IN2P3-CNRS, Université de Haute-Savoie, 9 chemin de Bellevue, 74941Annecy-le-Vieux Cedex, France d Université Libre de Bruxelles, Campus de la Plaine, Boulevard du Triomphe, 1050 Bruxelles, Belgique wanlin@ipno.in2p3.fr ABSTRACT: The next generation of proton decay and neutrino experiments, the post- SuperKamiokande detectors, such as those that will take place in megaton size water tanks, will require very large surfaces of photo-detection and will produce a large volume of data. Even with large hemispherical photomultiplier tubes (PMTs), the expected number of channels should reach hundreds of thousands. An ANR funded R&D program to implement a solution is presented here. The very large surface of photo-detection is segmented in macro pixels consisting of an array (2 2 m 2 ) of 16 hemispherical 12-inch PMTs connected to autonomous underwater front-end electronics working in a triggerless data acquisition mode. The array is powered by a common high voltage and only one data cable allows the connection by network to the surface controller. This 1 Corresponding author. c 2011 IOP Publishing Ltd and SISSA doi: / /6/01/c01081

3 architecture allows a considerable reduction of the cost and facilitates the industrialization. This paper presents the complete architecture of the prototype system and tests results with 16 8-inch PMTs, validating the whole electronics, the built-in gain adjustment and the calibration principle. KEYWORDS: VLSI circuits; Modular electronics; Large detector systems for particle and astroparticle physics; Front-end electronics for detector readout

4 Contents 1 Introduction 1 2 System architecture Overview Triggerless front-end 2 3 Surface controller and submarine cables 3 4 Underwater front-end electronics 4 5 Demonstrator results 6 6 Conclusion 7 1 Introduction The next generation of neutrino experiments, as MEMPHYS in Europe, HyperKamiokande in Japan or LBNE in USA, will imply hundreds of thousands of hemispherical photomultiplier tubes (PMTs) covering the sensitive volume of the tanks and a large volume of data. In this international competition, the PMm 2 project has focused its research on the development of a new generation of smart photo-detectors. PMm 2 thus proposes to segment the total detection surface in 2 2 m 2 arrays of 4 4 PMTs connected to an innovative autonomous and triggerless electronics system. The digitized data will be sent from an underwater front-end board to a surface board, connected itself to an online data acquisition PC via an Ethernet network. The design was driven by costs reduction and integrates industrial assembly procedures. A collaboration with the Photonis Company showed that important savings could be obtained by using 12-inch diameter PMTs instead of the 20-inch ones used in SuperKamiokande. However, the increase in the number of electronics channels has to be compensated by using new lower cost data acquisition architecture and front-end electronics. Progresses in micro-electronics make it possible by integrating 16 channels from pre-amplifiers to analog to digital converter in a single integrated circuit. This low cost architecture, joined with the specific constraint for the whole front-end electronics to withstand 7.5-bar pressure in 65-m high water tanks, should satisfy many upcoming projects. The PMm 2 project [1] was funded by the French National Agency for Research (ANR) under the reference ANR-06-BLAN

5 Figure 1. Principle of the PMm 2 architecture and demonstrator with 16 8-inch PMTs. 2 System architecture 2.1 Overview The experiment will use hemispherical 12-inch diameter PMTs instead of the 20-inch ones as in SuperKamiokande, because engineers of Photonis showed in a study carried out in 2005 [2] that the 12-inch PMTs have greater photo-detection efficiency (quantum efficiency of 24% vs 20%, collection efficiency of 70% vs 60%) and lower production costs (800 euros vs 2500). PMm 2 proposes to group the PMTs by 16, as shown in figure 1. This segmentation constitutes a good compromise between the number of channels to integrate in a single ASIC, the power to deliver for a single high voltage supply, and finally counting and data transfer rates to sustain for 16 channels. The 16 PMTs share a common submarine waterproof electronics and high voltage bias located close to them, in a watertight enclosure. A single cable connects the submarine embedded electronics with the surface controller and carries both data and power, as shown in figure 2. The front-end electronics consists of a 16-channel ASIC, coupled to an FPGA that manages the dialog with the surface controller through the data cable. At this scale of production, cost is highly reduced by including in the ASIC the complete analog processing of the PMTs signals up to the digitization. The ASIC has also to compensate the PMTs gain dispersion due to the common high voltage. The 16 PMTs are assembled on a frame simplifying the production, the shipment and the integration to the detector. There is only one connector between the PMTs and the front-end module and a 100 m long cable linking the front-end to the surface, leading to an additional saving, because underwater connectors are expensive. 2.2 Triggerless front-end The neutrinos, while interacting with the matter, will produce charged particles that will create on the surface of the tank a huge Cerenkov light beam much larger than a single 16-PMT segment cell. Therefore, it is impossible to build a local trigger. A triggerless mode is hence necessary and the charge and timing information of each PMT are necessary to build later a trigger. The requirement on the time resolution for the electronics is 1 ns since the expected single electron transit time spread is not better than 3 ns for the considered size of PMT. 2

6 Figure 2. Block diagram of PMm 2 architecture. 3 Surface controller and submarine cables The surface controller, as indicated on figure 2, is the interface between the surface data acquisition system and the underwater front-end module. The surface controller (See figure 3) manages the power, the distribution of the reference GPS synchronization clock, the configuration and the acquisition of the watertight front-end board. It also transmits the collected data via an Ethernet network to a DAQ PC using JAVA software. The minimum data transfer rate to sustain is 5 Mbps. The two main elements of this surface controller are the NETBURNER MOD5270 (microcontroller mezzanine card ensuring the connection towards the external network) and an Altera FPGA. This one ensures the management of the synchronization and the dialogue with the watertight front-end board. The link between this controller and the submarine board is made with two differential pairs: a pair delivering the 10 MHz GPS clock (unidirectional) and the other pair for the data (bidirectional) and the 48 V supply (used in the Power Over Ethernet + technology). A third differential pair is a spare in case we need more power. For tests easyness, two surface controller boards can be used, one as a master and the other as a slave board (submarine), in order to validate the full connection with 100 m cable. The connection between the surface and the submarine board has been chosen with particular attention as it must be able to withstand immersion for several years at 7.5bar hydrostatic pressure. We have compared different solutions in order to transport electrical power and bidirectional data over 100 m. Several submarine cables and watertight connectors (figure 4) have been tested electrically and mechanically, following the CAT5 testing standard, in order to compare the performances and the costs. Components from two companies, which are able to achieve mass production for future large experiments, have been selected. 3

7 4 Underwater front-end electronics Figure 3. Block diagram of the surface controller. Figure 4. Surface board and adopted submarine cables. The block diagram of the submarine board, as well a picture of the board in its watertight enclosure, are shown on figure 5. The board hosts two main components: the PARISROC ASIC [3, 4] and an Altera Cyclone 3 FPGA. A DC/DC converter generates a 5 V supply from the 48 V received from the surface. Additional linear voltage regulators are used to generate the other necessary power sources (3.3 V, 2.5 V and 1.2 V). A single high voltage converter produces the high voltage (up to 2 kv) to bias the 16 PMTs and is adjustable from the surface. Figure 6 shows the architecture of the PARISROC ASIC. It is able to read 16 PMTs channels and is realized in a BiCMOS SiGe 0.35 µm technology from AustriaMikroSystems. It is a triggerless chip which sustains a mean counting rate of 5 khz and works in an autonomous mode. It provides the compensation of the PMTs gain dispersion due to the common high voltage, the charge digitization with a 10-bit Wilkinson ADC, time stamping on 24 bits and fine time digitization on 10 bits also, with a measured accuracy down to 425 ps RMS [5]. The charge dynamic range is covered by using two gains before digitization that a discriminator selects automatically. In order 4

8 Figure 6. Block diagram of the PARISROC ASIC. to reduce the loss rate, the input data are hold in a Switch Capacitor Array (SCA) with a depth of two. All the output data are in Gray format and only the hit channels are read out in serial mode, at a rate of 40 MHz. We calculated the loss rate with a rate of 5 khz for each PMT: it is less than 1%. The FPGA provides the connectivity for the slow control of the ASIC to the surface controller. It performs also the data collection from the PARISROC and the transmission towards the FPGA of the surface controller, following a custom protocol with a bit-encoding performed in Manchester format. The rate of data transmission to the surface controller has been tested up to 10 Mbps. 5 Figure 5. Architecture of the submarine front-end board and watertight enclosure.

9 A temperature sensor allows monitoring the temperature of the submarine board components from the surface. A USB1 interface is included to allow the stand alone debugging of the board and the validation of the different functionalities. The ASIC is hosted on a daughter board, including its own regulators and supply filters to avoid mother board digital noise pollution. Special care was taken in the design of the Printing Circuit Board to meet rules of isolation due to the high voltage, rules of filtering, cooling and Electro Magnetic Compatibility (EMC). The board has 8 layers and conforms to class 5 specifications. The geometry of the enclosure (figure 5) of the electronics board meets all the requirements due to pressure, EMC, cooling and waterproofing constraints. The PMTs cables pass through the enclosure and are directly soldered on the submarine board. We collaborated with an industrial company to achieve this assembling and over-molding of connectors and cables in polyurethane with an industrial process which can be realized in mass production ( units). Underwater pressure tests up to 13 bars have been performed to meet the final design. 5 Demonstrator results The demonstrator consists of the complete electronics set described earlier and of 16 8-inch PMTs (Hamamatsu R5912) in a light-tight tank. A common high voltage of 1550 V is set to reach a gain of on PMTs in order to measure the single electron charge by setting the discriminator threshold to 0.3 photoelectrons. Figure 7 shows the noise spectrum we obtain on one channel, after pedestal subtraction, when operating the demonstrator. The data corresponding to the higher gain amplification before digitization are plotted in blue and the rescaled data corresponding to the lower gain before digitization plotted in green. Both histograms match well: the charge overlap due to the discrimination errors represents only 4 ADC bins. The physical events we expect (PMT noise pulses in the majority) should have a charge above the threshold we set to the discriminator. This threshold corresponds on the left figure to the sharp edge at 10 ADC bins. However, we observe events with a charge centered at 0: this is an acquisition noise. It corresponds to events that trigged the discriminator after the fast shaper, but which amplitude after the slow shaper is around zero. This can be due to electronics noise or coupling, for which the integral is null. We calculated with a simplified probabilistic model an upper limit for the additional loss rate induced by the acquisition noise: it is less than 3%. We observe on figure 7 a 4-LSB pattern on the high gain charge histogram that looks like the effect of a differential non-linearity in the digitization. The induced error is less than 5% on the histogram bin amplitude; it is much greater than the contribution of the statistics. Since the pattern of the error is symmetric (positive and negative error), we observe on figure 7 (left) a rather good agreement when fitting by a Gaussian. We used the least square method and obtained 287 for chisquare with 17 degrees of freedom. This error is induced only by the electronics: we obtained a ratio for the chi-square to the number of degrees of freedom (which was greater than 50) smaller than one with an acquisition based on a digitizing oscilloscope. We therefore used those fits to calculate the gains in order to compensate the dispersions of the 16 PMTs due to the common high voltage: the ratio of the greatest PMT gain to the smallest one is 4.0, and we reduced it to

10 Figure 7. Typical noise histogram. Left: detail on the single photoelectron peak with a fit by a Gaussian curve. Right: whole spectrum with the histograms corresponding to the two gains before the ADC. We measured the PMTs counting rates by fitting the distribution of the time difference between consecutive events, which corresponds to an exponential distribution for delays greater than 30 µs. We obtained 1 khz without water, after more than 24 h of operation. This rate corresponds to the measurements we performed previously with a CAMAC based data acquisition. After immersion under 70 cm of water and PMT stabilization, we measured rates between 4.5 and 6.7 khz, and obtained the same position for the single electron peak. 6 Conclusion We validated the ability of the PMm2 elements to operate under 65 m of water. We showed that the PMm 2 demonstrator can measure the number of impinging photoelectrons on 16 large PMTs with their arrival time, with a loss rate smaller than 4%, including the effects of the noise we measured. We were able to perform the single electron peak measurement and compensate the PMT gain dispersion due to the common high voltage. Those first results confirm that the architecture proposed by the PMm 2 R&D project satisfies many upcoming projects of megaton scale detectors for proton decay search and neutrino physics. References [1] PMm 2 program website, [2] C. Marmonier, Revisiting the optimum PMT size for water-cherenkov megaton detectors, talk given at the NNN05 conference, [3] F. Dulucq et al., Digital part of PARISROC2: a photomultiplier array readout chip, Topical Workshop on Electronics for Particle Physics (TWEPP-10), Aachen Germany, September [4] S. Conforti Di Lorenzo, Développement et characterisation d un ASIC de lecture de macro-cellule de photo détecteurs de grande dimension, thèse LAL année (2010), to be published. [5] S. Drouet et al., Subnano time to digital converter implemented in PARISROC2 for PMm 2 R&D program, Topical Workshop on Electronics for Particle Physics (TWEPP-10), Aachen Germany, September