Application Note AN4149

Transcription

1 Application Note AN449 Design Guidelines for QuasiResonant Converters Using KA5Qseries Fairchild Power Switch (FPS TM ) Abstract In general, a QuasiResonant Converter (QRC) shows lower EMI and higher power conversion efficiency compared to the conventional hard switched converter with a fixed switching frequency. Therefore, it is well suited for color TV applications that are noise sensitive. This application note presents practical design considerations of QuasiResonant Converters for color TV applications employing KA5Qseries FPS TM (Fairchild Power Switch). It includes designing the transformer, output filter and sync network, selecting the components and closing the feedback loop. The stepbystep design procedure described in this application note will help engineers design quasiresonant converter easily. D R(n) L P(n) V O(n) N S(n) C O(n) C P(n) N p AC IN KA5Qseries Drain N S D R C O L P C P V O (B) Sync PWM GND Cr D R2 L P2 V O2 (Sound) V FB C B Vcc R a D a N S2 C O2 C P2 Linear regulator MCU C a N a D SY R d Rbias R 3 R str R SY HA87A R C SY R SY2 KA43 R F C F R R 2 Q Picture ON Figure. Basic Quasi Resonant Converter Using KA5Qseries (Color TV Application). Introduction The KA5Qseries FPS TM (Fairchild Power Switch) is an integrated Pulse Width Modulation (PWM) controller and a Sense FET specifically designed for quasiresonant offline Switch Mode Power Supplies (SMPS) with imal external components. Compared with a discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight while simultaneously increasing efficiency, system reliability and productivity. Figure shows the basic schematic of a quasiresonant converter using KA5Qseries for the color TV application, which also serves as the reference circuit for the design process described in this paper. V o is the output voltage that powers horizontal deflection circuit while V o2 is the output voltage that supplies power to the Micro Controller Unit (MCU) through a linear regulator. Rev..0.0

2 AN Stepbystep Design Procedure. Define the system specifications (V line, V line max, f L, P o, E ff ) 2. Detere DC link capacitor (C DC ) and DC link voltage range 3. Detere the reflected output voltage ( ) 4. Detere the transformer primary side inductance (L m ) 5. Choose proper FPS considering input power and I ds peak 6. Detere the proper core and the imum primary turns (N p ) 7. Detere the number of turns for each output 8. Detere the startup resistor In this section, a design procedure is presented using the schematic of Figure as a reference. Figure 2 illustrates the design flow chart. The detailed design procedures are as follows: [STEP] Define the system specifications Line voltage range (V line and V max line ). Line frequency (f L ). Maximum output power (P o ). Estimated efficiency (E ff ) : The power conversion efficiency must be estimated to calculate the maximum input power. If no reference data is available, set E ff = 0.7~0.75 for low voltage output applications and E ff = 0.8~0.85 for high voltage output applications. In the case of Color TV applications, the typical efficiency is 80~83%. With the estimated efficiency, the maximum input power is given by P in P o E ff = () For multiple output SMPS, the load occupying factor for each output is defined as 9. Detere the wire diameter for each winding Is the winding window area (Aw) enough? N Y P K on ( ) Ln ( ) P o = (2) where P o(n) is the maximum output power for the nth output. For single output SMPS, K L() =. It is assumed that V o is the reference output that is regulated by the feedback control in normal operation. Y Is it possible to change the core? N 0. Choose the secondary side rectifier diodes. Detere the output capacitors [STEP2] Detere DC link capacitor (C DC ) and the DC link voltage range. It is typical to select the DC link capacitor as 23uF per watt of input power for universal input range (85265Vrms) and uf per watt of input power for European input range (95V 265Vrms). With the DC link capacitor chosen, the imum DC link voltage is obtained as 2. Design the synchronization network 2 P in ( D ch ) = 2 ( V line ) (3) C DC f L 3. Design the voltage drop circuit for burst operation 4. Design the feedback control circuit Design finished Figure 2. Flow Chart of Design Procedure where C DC is the DC link capacitor and D ch is the duty cycle ratio for C DC to be charged as defined in Figure 3, which is typically about 0.2. P in, V line and f L are specified in STEP. The maximum DC link voltage is given as max where V line max is specified in STEP. max = 2V line (4) 2

3 DC link voltage D ch = T / T 2 = 0.2 T T2 Minimum DC link voltage Figure 3. DC Link Voltage Waveform [STEP3] Detere the reflected output voltage ( ) Figure 4 shows the typical waveforms of the drain voltage of quasiresonant flyback converter. When the MOSFET is turned off, the DC link voltage ( ) together with the output voltage reflected to the primary ( ) are imposed on the MOSFET. The maximum noal voltage across the MOSFET (V ds nom ) is AN449 [STEP4] Detere the transformer primary side inductance (L m ) Figure 5 shows the typical waveforms of MOSFET drain current, secondary diode current and the MOSFET drain voltage of a Quasi Resonant Converter. During T OFF, the current flows through the secondary side rectifier diode and the MOSFET drain voltage is clamped at ( ). When the secondary side current reduces to zero, the drain voltage begins to drop by the resonance between the effective output capacitor of the MOSFET and the primary side inductance (L m ). In order to imize the switching loss, the KA5Qseries is designed to turn on the MOSFET when the drain voltage reaches its imum voltage ( ). I ds I D V ds nom max = (5) where max is as specified in equation (4). By increasing, the capacitive switching loss and conduction loss of the MOSFET are reduced. However, this increases the voltage stress on the MOSFET as shown in Figure 4. Therefore, detere by a tradeoff between the voltage margin of the MOSFET and the efficiency. Typically, is set as 20~80V so that V ds norm is 490~5 (75~85% of MOSFET rated voltage). V ds T ON T OFF T F FPS L m V O TS Figure 5. Typical Waveforms of QuasiResonant Converter V ds nom 0 V max Figure 4. The Typical Waveform of MOSFET Drain Voltage for Quasi Resonant Converter Drain GND C r V ds V ds nom To detere the primary side inductance (L m ), the following variables should be detered beforehand : The imum switching frequency (f s ) : The imum switching frequency occurs at the imum input voltage and full load condition and should be higher than the imum switching frequency of FPS (20kHz). By increasing f s, the transformer size can be reduced. However, this results in increased switching losses. Therefore, detere f s by a tradeoff between switching losses and transformer size. It is typical to set f s to be around 25kHz. The falling time of the MOSFET drain voltage (T F ) : As shown in Figure 5, the MOSFET drain voltage fall time is half of the resonant period of the MOSFET s effective output capacitance and primary side inductance. By increasing T F, EMI can be reduced. However, this forces an increase of the resonant capacitor (Cr) resulting in increased switching losses. The typical value for T F is 22.5us. 3

4 AN449 After detering f s and T F, the maximum duty cycle is calculated as D max where V DC is specified in equation (3) and is detered in STEP3. Then, the primary side inductance is obtained as ( V L DC Dmax ) 2 m = (7) 2 f s Pin where P in, and D max are specified in equations (), (3), and (6), respectively and f s is the imum switching frequency. Once L m is detered, the maximum peak current and RMS current of the MOSFET in normal operation are obtained as where, D max and L m are specified in equations (3), (6) and (7), respectively and f s is the imum switching frequency. [STEP5] Choose the proper FPS considering input power and peak drain current. With the resulting maximum peak drain current of the MOSFET (I ds peak ) from equation (8), choose the proper FPS whose pulsebypulse current limit level (I LIM ) is higher than I ds peak. Since FPS has ± 2% tolerance of I LIM, there should be some margin for I LIM when choosing the proper FPS device. Table shows the lineups of KA5Qseries with rated output power and pulsebypulse current limit. PRODUCT = ( f s T F ) (6) I ds peak I ds rms Maximum Output Power 230Vac ±5% Dmax = (8) L m f s D max peak = I 3 ds ( 9) 85~ 265Vac I LIM Min Typ Max KA5Q0740RT 90 W (85~70Vac) 4.4A 5A 5.6A KA5Q0565RT 75 W 60 W 3.08A 3.5A 3.92A KA5Q0765RT 00 W 85 W 4.4A 5A 5.6A KA5Q265RT 50 W 20 W 5.28A 6A 6.72A KA5Q265RF 20 W 70 W 7.04A 8A 8.96A KA5Q565RF 250 W 20 W 0.2A.5A 2.88A [STEP6] Detere the proper core and the imum primary turns. Table 2 shows the commonly used cores for CTV application for different output powers. When designing the transformer, consider the maximum flux density swing in normal operation ( B) as well as the maximum flux density in transient (B max ). The the maximum flux density swing in normal operation is related to the hysteresis loss in the core while the maximum flux density in transient is related to the core saturation. With the chosen core, the imum number of turns for the transformer primary side to avoid the over temperature in the core is given by N P peak L m I ds = 0 6 (0) BA e where L m is specified in equation (7), I peak ds is the peak drain current specified in equation (8), A e is the crosssectional area of the transformer core in mm 2 as shown in Figure 6 and B is the maximum flux density swing in tesla. If there is no reference data, use B =0.25~0.30 T. Since the MOSFET drain current exceeds I peak ds and reaches I LIM in a transient or fault condition, the transformer should be designed not to be saturated when the MOSFET drain current reaches I LIM. Therefore, the maximum flux density (B max ) when drain current reaches I LIM should be also considered as N P L m I LIM = 0 6 () B max A e where L m is specified in equation (7), I LM is the pulsebypulse current limit, A e is the crosssectional area of the core in mm 2 as shown in Figure 6 and B max is the maximum flux density in tesla. Figure 7 shows the typical characteristics of ferrite core from TDK (PC40). Since the core is saturated at low flux density as the temperature goes high, consider the high temperature characteristics. If there is no reference data, use B max =0.35~0.4 T. The primary turns should be detered as less than N p values obtained from equation (0) and (). Aw (mm 2 ) Table. FPS Lineups with Rated Output Power Ae (mm 2 ) Figure 6. Window Area and Cross Sectional Area 4

5 Magnetization Curves (typical) Material :PC40 AN449 where n is obtained in equation (2) and N p and N s are the number of turns for the primary side and the reference output, respectively The number of turns for the other output (nth output) is detered as = N s ( 4) V N on ( ) V Fn ( ) sn ( ) V o V F Flux density B (mt) where V o(n) is the output voltage and V F(n) is the diode (D R(n) ) forward voltage drop of the nth output. N S(n) V F(n) D R(n) V O(n) Magnetic field H (A/m) Figure 7. Typical BH Characteristics of Ferrite Core (TDK/PC40) Np V N F2 S2 DR2 VO2 Linear Regulator Output Power Core 7000W EER35 V cc R a V Fa D a N a N S V F D R 0050W EER40 EER W EER49 V O Table 2. Commonly Used Cores for CTV Applications Figure 8. Simplified Diagram of the Transformer [STEP7] Detere the number of turns for each output Figure 8 shows the simplified diagram of the transformer. It is assumed that V o is the reference output which is regulated by the feedback control in normal operation. It is also assumed that the linear regulator is connected to V o2 to supply a stable voltage for MCU. First, calculate the turns ratio (n) between the primary winding and reference output (V o ) winding as a reference V R0 V o V F n = (2) where is detered in STEP3 and V o is the reference output voltage and V F is the forward voltage drop of diode (D R ). Then, detere the proper integer for N s so that the resulting N p is larger than N p as Vcc winding design : KA5Qseries drops all the outputs including the Vcc voltage in standby mode in order to imize the power consumption. Once KA5Qseries enters into standby mode, Vcc voltage is hysteresis controlled between V and 2V as shown in Figure 9. The sync threshold voltage is also reduced from 2.6V to.3v in burst mode. Therefore, design the Vcc voltage to be around 24V in normal operation for proper quasiresonant switching in standby mode as can be observed by ( 2) 2.3 (5) N p = n N s > N p (3) 5

6 AN449 V cc C DC 2V V Normal mode Standby mode V sync AC line I sup R str Vcc R a D a KA5Qseries 4.6V 2.6V 3.6V.3V C a Figure 9. Burst operation in standby mode Figure. 0 Startup Resistor and Vcc Auxiliary Circuit In general, switched mode power supply employs an error amplifier and an optocoupler to regulate the output voltage. However, Primary Side Regulation (PSR) can be used for a low cost design if output regulation requirements are not very tight. PSR scheme regulates the output voltage indirectly by controlling the Vcc voltage without an optocoupler. KA5Qseries has an internal error amplifier with a fixed reference voltage of 32.5V for PSR applications. If PSR is used, set Vcc to 32.5V. After detering V cc voltage in normal operation, the number of turns for the Vcc auxiliary winding (N a ) is obtained as V N cc V Fa a = N s V o V F where V Fa is the forward voltage drop of D a as defined in Figure 8. [STEP8] Detere the startup resistor ( turns) ( 6) Figure 0 shows the typical startup circuit for KA5Qseries. Because some protections are implemented as latch mode, AC startup is typically used to provide a fast reset. Initially, FPS consumes only startup current (max 200uA) before it begins switching. Therefore, the current supplied through the startup resistor (R str ) can charge the capacitors C a and C a2 while supplying startup current to FPS. When Vcc reaches a start voltage of 5V (V START ), FPS begins switching, and the current consumed by FPS increases. Then, the current required by FPS is supplied from the transformer s auxiliary winding. Startup resistor (R str ) : The average of the imum current supplied through the startup resistor is given by avg 2 V V line I start sup = ( 7) π 2 R str where V line is the imum input voltage, V start is the start voltage (5V) of FPS and R str is the startup resistor. The startup resistor should be chosen so that I avg sup is larger than the maximum startup current (200uA). If not, Vcc can not be charged up to the start voltage and FPS will fail to start up. The maximum startup time is detered as T str max V start = C a ( 8) avg max ( I sup I start ) Where C a is the Vcc capacitor and I start max is the maximum startup current (200uA) of FPS. Once the startup resistor (R str ) is detered, the maximum approximate power dissipation in R str is obtained as max V 2 2 V max line start 2 2 V V start line P = str R 2 π ( 9) str where V line max is the maximum input voltage, which is specified in STEP. The startup resistor should have a proper dissipation rating based on the value of P str. 6

7 AN449 [STEP9] Detere the wire diameter for each winding based on the RMS current of each output. The RMS current of the nth secondary winding is obtained as I rms sec( n) rms D I max K Ln ( ) = ds ( 20) ( ) D max V on ( ) V Fn ( ) where D max and I rms ds are specified in equations (6) and (9), V o(n) is the output voltage of the nth output, V F(n) is the diode (D R(n) ) forward voltage drop, is specified in STEP3 and K L(n) is the load occupying factor for nth output defined in equation (2). The current density is typically 5A/mm 2 when the wire is long (>m). When the wire is short with a small number of turns, a current density of 60 A/mm 2 is also acceptable. Do not use wire with a diameter larger than mm to avoid severe eddy current losses as well as to make winding easier. For high current output, it is recommended using parallel windings with multiple strands of thinner wire to imize skin effect. Check if the winding window area of the core, A w (refer to Figure 6) is enough to accommodate the wires. The required winding window area (A wr ) is given by A wr = A c K F (2) where A c is the actual conductor area and K F is the fill factor. Typically the fill factor is 0.2~0.25 for single output applications and 0.5~0.2 for multiple output applications. If the required window (A wr ) is larger than the actual window area (A w ), go back to the STEP6 and change the core to a bigger one. Sometimes it is impossible to change the core due to cost or size constraints. In that case, reduce in STEP3 or increase f s, which reduces the primary side inductance (L m ) and the imum number of turns for the primary (N p ) as can be seen in equation (7) and (0). [STEP0] Choose the proper rectifier diodes in the secondary side based on the voltage and current ratings. The maximum reverse voltage and the rms current of the rectifier diode (D R(n) ) of the nth output are obtained as max V V Dn ( ) on ( ) rms I Dn ( ) ( ) = ( 22) V on ( ) V Fn ( ) rms D I max K Ln ( ) = ds ( 23) ( ) D max V on ( ) V Fn ( ) where K L(n), max, D max and I ds rms are specified in equations (2), (4), (6) and (9), respectively, is specified in STEP3, V o(n) is the output voltage of the nth output and V F(n) is the diode (D R(n) ) forward voltage drop. The typical voltage and current margins for the rectifier diode are as follows V RRM >.3 V Dn ( ) (24) rms I F >.5 I Dn ( ) (25) where V RRM is the maximum reverse voltage and I F is the average forward current of the diode. A quick selection guide for the Fairchild Semiconductor rectifier diodes is given in Table 3. In this table, t rr is the maximum reverse recovery time. Ultra Fast Recovery Diode Products V RRM I F t rr Package EGP0B 00 V A 50 ns DO4 UF V A 50 ns DO4 EGP20B 00 V 2 A 50 ns DO5 EGP30B 00 V 3 A 50 ns DO20AD FES6BT 00 V 6 A 35 ns TO220AC EGP0C 50 V A 50 ns DO4 EGP20C 50 V 2 A 50 ns DO5 EGP30C 50 V 3 A 50 ns DO20AD FES6CT 50 V 6 A 35 ns TO220AC EGP0D 200 V A 50 ns DO4 UF V A 50 ns DO4 EGP20D 200 V 2 A 50 ns DO5 EGP30D 200 V 3 A 50 ns DO20AD FES6DT 200 V 6 A 35 ns TO220AC EGP0F 300 V A 50 ns DO4 EGP20F 300 V 2 A 50 ns DO5 EGP30F 300 V 3 A 50 ns DO20AD EGP0G 400 V A 50 ns DO4 UF V A 50 ns DO4 EGP20G 400 V 2 A 50 ns DO5 EGP30G 400 V 3 A 50 ns DO20AD UF V A 75 ns DO4 EGP0J 600 V A 75 ns DO4 EGP20J 600 V 2 A 75 ns DO5 EGP30J 600 V 3 A 75 ns DO20AD UF V A 75 ns TO4 UF V A 75 ns TO4 Table 3. Fairchild Diode Quick Selection Table 7

8 AN449 [STEP] Detere the output capacitors considering the voltage and current ripple. The ripple current of the nth output capacitor (C o(n) ) is obtained as KA5Qseries N p N s rms I cap( n) = ( ) 2 I on (26) rms I Dn ( ) ( ) 2 where I o(n) is the load current of the nth output and I D(n) rms is specified in equation (23). The ripple current should be smaller than the maximum ripple current specification of the capacitor. The voltage ripple on the nth output is given by Sync comparator CO 4.6.6V Sync Vcc Drain C r I ds GND L m V ds N a V o R cc D a I V D on ( ) max on ( ) = C on ( ) f s peak I ds VRO R Cn ( ) K Ln ( ) ( ) (27) V on ( ) V Fn ( ) C a D SY where C o(n) is the capacitance, R c(n) is the effective series resistance (ESR) of the nth output capacitor, K L(n), D max and I peak ds are specified in equations (2), (6) and (8) respectively, is specified in STEP3, I o(n) and V o(n) are the load current and output voltage of the nth output, respectively and V F(n) is the diode (D R(n) ) forward voltage drop. Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. In those cases, additional LC filter stages (post filter) can be used to reduce the ripple on the output. V sync C SY R SY R SY2 Figure. Synchronization Circuit The peak value of the sync signal is detered by the voltage divider network R SY and R SY2 as V sync pk R SY2 R SY R SY2 = V cc ( 28) [STEP2] Design the synchronization network. KA5Qseries employs a quasi resonant switching technique to imize the switching noise as well as switching loss. In this technique, a capacitor (C r ) is added between the MOSFET drain and source as shown in Figure. The basic waveforms of a quasiresonant converter are shown in Figure 2. The external capacitor lowers the rising slope of drain voltage, which reduces the EMI caused by the MOSFET turnoff. To imize the MOSFET switching loss, the MOSFET should be turned on when the drain voltage reaches its imum value as shown in Figure 2. The optimum MOSFET turnon time is indirectly detected by monitoring the Vcc winding voltage as shown in Figure and 2. The output of the sync detect comparator (CO) becomes high when the sync voltage (V sync ) exceeds 4.6V and low when the V sync reduces below 2.6V. The MOSFET is turned on at the falling edge of the sync detect comparator output (CO). Choose the voltage divider R SY and R SY2 so that the peak value of sync voltage (V sync pk ) is lower than the OVP threshold voltage (2V) in order to avoid triggering OVP in normal operation. Typically, V sync pk is set to 8~0V. To synchronize the V sync with the MOSFET drain voltage, choose the sync capacitor (C SY ) so that T F is same as T Q as shown in Figure 2. T F and T Q are given, respectively, as T F = π L m C eo (29) R SY2 R SY R SY2 V cc T Q = R SY2 C SY ln 2.6 (30) where L m is the primary side inductance of the transformer, N s and N a are the number of turns for the output winding and Vcc winding, respectively and C eo is the effective MOSFET output capacitance (C oss C r ) Fairchild Semiconductor Corporation

9 AN449 V ds Assug that both V o and V o2 drop to half of their normal values, the maximum value of R 3 for proper burst operation is given by ( V ) R R 2 R 3 = (32) 2.5 ( R R 2 ) ( R 2 V 0 2) V sync T F V ovp (2V) V sync pk V FB V 4.6V 2.6V I ds I bpk CO T Q V cc MOSFET Gate ON ON 2V V Figure. 2 Synchronization Waveforms Normal Mode Standby Mode [STEP3] Design voltage drop circuit for the burst operation. To imize the power consumption in the standby mode, KA5Qseries employs burst operation. Once FPS enters into burst mode, all the output voltages as well as effective switching frequencies are reduced as shown in Figure 3. Figure 4 shows the typical output voltage drop circuit for CTV applications. Under normal operation, the picture on signal is applied and the transistor Q is turned on, which decouples R 3 and D from the feedback network. Therefore, only V o is regulated by the feedback circuit in normal operation and is detered as R R 2 V o = 2.5 (3) In standby mode, the picture on signal is disabled and the transistor Q is turned off, which couples R 3 and D to the reference pin of KA43. If R 3 is small enough to make the reference pin voltage of KA43 higher than 2.5V, the current through the opto LED pulls down the feedback voltage (V FB ) of FPS and forces FPS to stop switching. Once FPS stops switching, V cc decreases, and when V cc reaches V, it resumes switching with a predetered peak drain current until Vcc reaches 2V. When Vcc reaches 2V, the switching operation is terated again until Vcc reduces to V. In this way, Vcc is hysteresis controlled between V and 2V in the burst mode operation. R 2 R bias KA43 Figure 3. Burst Operation Waveforms V O2 C A R D V O (B) R R 3 C F R F D Q R R 2 Linear Regulator Micom Picture ON Figure 4. Typical Feedback Circuit to Drop Output Voltage in Standby Mode [STEP4] Design the feedback control circuit. Since the KA5Qseries employs current mode control as shown in Figure 5, the feedback loop can be easily implemented with a onepole and onezero compensation circuit. The current control factor of FPS, K is defined as 9

10 AN449 I pk K = = (33) V FB I LIM V FBsat where I pk is the peak drain current and V FB is the feedback voltage for a given operating condition, I LIM is the current limit of the FPS and V FBsat is the internal feedback saturation voltage, which is typically 2.5V. In order to express the small signal AC transfer functions, the small signal variations of feedback voltage (v FB ) and controlled output voltage (v vˆ FB and vˆ o ) are introduced as o. FPS R B C B v FB i D R D CTR : v bias KA43 i bias R bias C F R F v o R When the converter has more than one output, the low frequency controltooutput transfer function is proportional to the parallel combination of all load resistance, adjusted by the square of the turns ratio. Therefore, the effective load resistance is used in equation (34) instead of the actual load resistance of V o. Notice that there is a right half plane (RHP) zero (w rz ) in the controltooutput transfer function of equation (34). Because the RHP zero reduces the phase by 90 degrees, the crossover frequency should be placed below the RHP zero. The Figure 6 shows the variation of a quasiresonant flyback converter s controltooutput transfer function for different input voltages. This figure shows the system poles and zeros together with the DC gain change for different input voltages. The gain is highest at the high input voltage condition and the RHP zero is lowest at the low input voltage condition. Figure 7 shows the variation of a quasiresonant flyback converter s controltooutput transfer function for different loads. This figure shows that the gain between f p and f z does not change for different loads and the RHP zero is lowest at the full load condition. The feedback compensation network transfer function of Figure 5 is obtained as I pk MOSFET current R 2 ˆ v FB ˆ w i s w zc = ( 35) s s w pc v o R where w B CTR i =, w R R D C zc =, w F R F C pc = F R B C B Figure 5. Control Block Diagram For quasiresonant flyback converters, the controltooutput transfer function using current mode control is given by and R B is the internal feedback bias resistor of FPS, which is typically 2.8kΩ, CTR is the current transfer ratio of opto coupler and R, R D, R F, C F and C B are shown in Figure 5. G vc = vˆ o vˆ FB K R L ( N p N s ) ( s w z )( s w rz ) = ( 34) 22V ( RO v DC ) s w p 40 db 20 db f p where is the DC input voltage, R L is the effective total load resistance of the controlled output, which is defined as V o 2 /P o. Additionally, N p and N s are specified in STEP7, is specified in STEP3, V o is the reference output voltage, P o is specified in STEP and K is specified in equation (33). The pole and zeros of equation (34) are defined as R w z, w L ( D) 2 ( D) = R c C rz = o DL m ( N s N p ) 2 and w p = R L C o 0 db 20 db 40 db Hz f p Low input voltage High input voltage 0Hz 00Hz khz 0kHz 00kHz Figure 6. QR Flyback Converter Controlto Output Transfer Function Variation for Different Input Voltages f z f z f rz f rz where L m is specified in equation (7), D is the duty cycle of the FPS, C o is the output capacitor of V o and R C is the ESR of C o. 0

11 AN449 When detering the feedback circuit component, there are some restrictions as described below: 40 db 20 db f p Light load (a) Design the voltage divider network of R and R 2 to provide 2.5V to the reference pin of the KA43. The relationship between R and R 2 is given as 0 db f p Heavy load 2.5 R R 2 = (36) V o db 40 db Hz f z f rz f rz 0Hz 00Hz khz 0kHz Figure 7. QR Flyback Converter Controlto Output Transfer Function Variation for Different Loads 00kHz When the input voltage and the load current vary over a wide range, detering the worst case for the feedback loop design is difficult. The gain together with zeros and poles varies according to the operating conditions. One simple and practical solution to this problem is designing the feedback loop for low input voltage and full load condition with enough phase and gain margin. The RHP zero is lowest at low input voltage and full load condition. The gain increases only about 6dB as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. The procedure to design the feedback loop is as follows (a) Set the crossover frequency (f c ) below /3 of RHP zero to imize the effect of the RHP zero. Set the crossover frequency below half of the imum switching frequency (f s ). (b) Detere the DC gain of the compensator (w i /w zc ) to cancel the controltooutput gain at f c. (c) Place a compensator zero (f zc ) around f c /3. (d) Place a compensator pole (f pc ) around 3f c. where V o is the reference output voltage. (b) The capacitor connected to feedback pin (C B ) is related to the shutdown delay time in an overload condition by T delay = ( V SD 2.5) C B I delay (37) where V SD is the shutdown feedback voltage and I delay is the shutdown delay current. Typical values for V SD and I delay are 7.5V and 5uA, respectively. In general, a delay of 20 ~ 50 ms is typical for most applications. Because C B also deteres the high frequency pole (w pc ) of the compensator transfer function as shown in equation (35), too large a C B can limit the control bandwidth by placing w pc at too low a frequency. Typical value for C B is 050nF. Application circuit to extend the shutdown time without limiting the control bandwidth is shown in Figure 9. By setting the zener breakdown voltage (Vz) slightly higher than 2.7V, the additional delay capacitor (Cz) is decoupled from the feedback circuit in normal operation. When the feedback voltage exceeds the zener breakdown voltage (Vz), Cz and C B detere the shutdown time. I FB I delay FPS v FB 40 db Loop gain T C B C z V z 20 db f p f zc f pc Compensator 0 db Control to output f c V SD 20 db f rz V Z 2.7V 40 db f z Hz 0Hz 00Hz khz 0kHz 00kHz Figure 8. Compensator Design T delay Figure 9. Delayed Shutdown

12 AN449 (c) The resistors R bias and R D used together with the optocoupler HA87A and the shunt regulator KA43 should be designed to provide proper operating current for the KA43 and to guarantee the full swing of the feedback voltage for the FPS device chosen. In general, the imum values of cathode voltage and current for the KA43 are 2.5V and ma, respectively. Therefore, R bias and R D should be designed to satisfy the following conditions: V bias 2.5 > I FB ( 38) V OP R bias V OP R D > ma (39) where V bias is the KA43 bias voltage as shown in Figure 6 and V OP is optodiode forward voltage drop, which is typically V. I FB is the feedback current of FPS, which is typically ma. 2

13 AN449 Design Example I (KA5Q0765RT) Application Device Input Voltage Output Power Output Voltage (Rated Current) Color TV KA5Q0765RT 85265Vac (60Hz) 82W 25V (0.4A) 20V (0.5A) 6V (.0A) 2V (0.5A) Schematic BD0 LF0 RT0 5D9 C02 220uF 400V R03 68kΩ 0.5W R04 68kΩ 0.5W 3 Vcc Drain IC0 SYNC 5 KA5Q0765RT GND FB 2 4 C04 47uF C09 47nF ZD0 4.7V 0.5W C03 00nF L0 BEAD D05 N4937 D06 N448 R05 470Ω R06 D03 680Ω N4937 C05 3.9nF 3 4 C07 nf R Ω 7 T EER D20 EGP20D C22 D205 EGP20D C207 D203 EGP20J C206 D202 EGP20D C205 L204 C20 BEAD 000uF 35V L203 C208 BEAD 000uF 35V C24 00uF 60V L202 BEAD L20 C202 BEAD 000uF 35V C25 47uF 60V 20V, 0.5A 2V, 0.5A 25V, 0.4A 6V, A C0 330nF 275VAC F0 FUSE 2 3.0A PC30 87A C08 2.2nF Q20 KA43 R20 kω R203 kω R204 39kΩ C203 22nF VR20 30kΩ R kΩ R kΩ VR202 30kΩ D20 Q202 KSC945 SW 20 R207 5.kΩ R208 5.kΩ 3

14 AN449 Transformer Specifications N p EER N 6V N a N p2 3 6 N 20V N 25V 4 5 N 25V N p2 5 4 N 25V N 2V 6 3 N 2 V N 6V N a 7 2 N 25V 8 N p 9 0 N 20 V Transformer Schematic Diagram Winding Specifications No Pin (s f) Wire Turns Winding Method N p φ 35 Center Winding N 25V φ 28 Center Winding N 6V φ 2 8 Center Winding N 2V φ 6 Center Winding N p φ 35 Center Winding N 25V φ 28 Center Winding N 20V φ 0 Center Winding N a φ Center Winding Electrical Characteristics Pin Specification Remarks Inductance 4 565uH ± 5% khz, V Leakage Inductance 4 0uH Max 2 nd all short Core & Bobbin Core : EER 3540 Bobbin : EER3540 Ae : 09 mm 2 4

15 AN449 Design Example II (KA5Q265RF) Application Device Input Voltage Output Power Output Voltage (Rated Current) Color TV KA5Q265RF 85265Vac (60Hz) 54W 25V (0.8A) 20V (0.5A) 6V (2.0A) 2V (.0A) Schematic BD0 LF0 RT0 0D9 C02 470uF 400V R03 68kΩ 0.5W R04 68kΩ 0.5W 3 Vcc Drain IC0 SYNC 5 KA5Q265RF GND FB 2 4 C04 47uF C09 47nF ZD0 4.7V 0.5W C03 00nF L0 BEAD D05 N4937 D06 N448 R05 470Ω R06 D03 680Ω N4937 C05 2.7nF 3 4 C07.5nF R Ω 7 T EER D20 EGP20D C22 D205 EGP20D C207 D203 EGP30J C206 D202 EGP30D C205 L204 C20 BEAD 000uF 35V L203 C208 BEAD 2200uF 35V C24 220uF 200V L202 BEAD L20 C202 BEAD 2200uF 35V C25 00uF 200V 20V, 0.5A 2V, A 25V, 0.8A 6V, 2A C0 330nF 275VAC F0 FUSE 2 5.0A PC30 87A C08 2.2nF Q20 KA43 R20 kω R203 kω R204 39kΩ C203 22nF VR20 30kΩ R kΩ R kΩ VR202 30kΩ D20 Q202 KSC945 SW 20 R207 5.kΩ R208 5.kΩ 5

16 AN449 Transformer Specifications N p EER N a 2 7 N 6V N 20V N p2 3 6 N 25V 4 5 N 25V N p2 5 4 N 25V N 2V 6 N a N 2 V N 6V N 25V N p 9 0 N 20 V Transformer Schematic Diagram Winding Specifications No Pin (s f) Wire Turns Winding Method N p φ 2 22 Center Winding N 25V φ 2 8 Center Winding N 6V φ 2 5 Center Winding N 2V φ 2 4 Center Winding N p φ 2 22 Center Winding N 25V φ 2 8 Center Winding N 20V φ 6 Center Winding N a φ 7 Center Winding Electrical Characteristics Pin Specification Remarks Inductance 4 385uH ± 5% khz, V Leakage Inductance 4 0uH Max 2 nd all short Core & Bobbin Core : EER 4242 Bobbin : EER4242 Ae : 234 mm 2 6

17 AN449 Design Example III (KA5Q565RF) Application Device Input Voltage Output Power Output Voltage (Rated Current) Color TV KA5Q565RF 85265Vac (60Hz) 27W 25V (.0A) 20V (.0A) 6V (3.0A) 2V (2.0A) Schematic BD0 LF0 RT0 0D9 C02 470uF 400V R03 68kΩ 0.5W R04 68kΩ 0.5W 3 Vcc Drain IC0 SYNC 5 KA5Q565RF GND FB 2 4 C04 47uF C09 47nF ZD0 4.7V 0.5W C03 00nF L0 BEAD D05 N4937 D06 N448 R05 470Ω R06 D03 680Ω N4937 C05 2.7nF 3 4 C07 2nF R Ω 7 T EER D20 EGP20D C22 D205 EGP30D C207 D203 FFPF05U60S C206 D202 FFPF05U20S C205 L204 C20 BEAD 000uF 35V L203 C208 BEAD 2200uF 35V C24 330uF 200V L202 BEAD L20 C202 BEAD 2200uF 35V C25 220uF 200V 20V, A 2V, 2A 25V, A 6V, 3A C0 330nF 275VAC F0 FUSE 2 5.0A PC30 87A C08 2.2nF Q20 KA43 R20 kω R203 kω R204 39kΩ C203 22nF VR20 30kΩ R kΩ R kΩ VR202 30kΩ D20 Q202 KSC945 SW 20 R207 5.kΩ R208 5.kΩ 7

18 AN449 Transformer Specifications N p EER N a 2 7 N 6V N 20V N p2 3 6 N 25V N a 8 5 N 25V 4 N 25V 3 2 N 2 V N p2 N 2V N 6V N 25V N p 9 0 N 20 V Transformer Schematic Diagram Winding Specifications No Pin (s f) Wire Turns Winding Method N p φ 2 2 Center Winding N 25V φ 2 7 Center Winding N 6V φ 3 5 Center Winding N 2V φ 2 4 Center Winding N p φ 2 2 Center Winding N 25V φ 2 7 Center Winding N 20V φ 6 Center Winding N a φ 7 Center Winding Electrical Characteristics Pin Specification Remarks Inductance 4 325uH ± 5% khz, V Leakage Inductance 4 0uH Max 2 nd all short Core & Bobbin Core : EER 5345 Bobbin : EER5345 Ae : 38 mm 2 8

19 AN449 Hangseok Choi, Ph.D Power Conversion Team / Fairchild Semiconductor Phone : Facsimile : hangseok.choi@fairchildsemi.com DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPROATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 90/05 0.0m Fairchild Semiconductor Corporation