Document prepared by Magneti Marelli - HU core team

Transcription

1 BMW Entry Nav Head Unit EN2 Filename: technical_specifications Date of issue: Friday, 22rd May 2015 Revision level: 6.00 Number of pages: 145 Document prepared by Magneti Marelli - HU core team 1/145

2 REVISION HISTORY Date Author(s) Version Description/comment 19/06/09 HU Core Team Ref. chap First issue: Preliminary documentation 30/10/09 HU Core Team Ref. chap Second issue: Document modified 14/01/10 HU Core Team Ref. chap Third issue: Document modified 01/02/10 HU Core Team Ref. chap Fourth issue: Document modified 03/02/10 HU Core Team Ref. chap Fifth issue: Document modified 22/05/2015 Wi-Fi deleted 6.00 Sixth issue: Wi-Fi deleted 2/145

3 TABLE OF CONTENTS BMW ENTRY NAV RFQ INTRODUCTION DOCUMENT OVERVIEW APPLICABLE DOCUMENTS (RECEIVED FROM BMW) GLOBAL PRESENTATION BMW ENTRY NAV RFQ HEAD UNIT ARCHITECTURE SYSTEM SYNOPTIC Option/Variant table BMW ENTRY NAV RFQ MECHANICAL DESCRIPTION HU PERSPECTIVE VIEWS EXPLODED VIEW SUBASSEMBLY GROUPS VIEWS BMW ENTRY RFQ HARDWARE ARCHITECTURE EXTERNAL CONNECTORS Fakra Radio Connector FOT Connector AM/FM Connector (AM/FM1) AM/FM Connector (AM/FM2) GPS Antenna Connector OPTION: DAB (DMB) Antenna Connectors (L-Band and Band III) OPTION: SDARS Antenna Connector LVDS Connector (CID) USB1 HSD Connector (USB 2.0) OPTION: USB2 HSD Connector (USB 2.0) OPTION: USB3 HSD Connector (USB 2.0) Short circuit protections HARDWARE SYSTEM ARCHITECTURE BLOCK DIAGRAM /145

4 4.3 POWER SUPPLIES Power Supply Operating Range Temperature Range Mode of Operation vs Power Supply Power supply Reverse battery protection RAD_ON Current Consumption Sleep current consumption Thermal Management FAN MODULE AND TEMPERATURE SENSOR MSA Support DAUGHTER BOARD CPU nvidia ESoC System Memories Power supply & reset Thermal management Start-Up strategy DB to MB connector MAIN BOARD MICROCONTROLLER Reset Strategy Power Management Thermal management OPTION: UART MANAGED NAND FLASH CAN HIGH SPEED INTERFACE OPTION: MOST INIC ROM OPTION: MOST INIC FLASH OPTION: FOT (OPTICAL LINK TRANSCEIVER FOR MOST) OPTION: GYROSCOPE & ACCELEROMETER INTERFACE Accelerometer and Gyroscope Introduction OPTION: Accelerometer OPTION: Gyroscope OPTION: SD CARD HOLDER LAN FILTER USB 2.0 INTERFACES CVBS - INPUT ARCHITECTURE Video Input Decoder Annex: Example of CVBS PAL signal LVDS OUTPUTS ARCHITECTURE LVDS INOVA APIX2 Transmitters /145

5 Pixel Channel Interface Downstream and upstream control data to CID via SPI Power supply for display AUDIO INPUT INTERFACE Microphones Auxiliary Audio stereo Input Aux_IN and mono input Tel_IN Tel Mute RADIO & DSP Introduction Radio function overview Tuner owerview DSP Radio Processing Audio Processing Software Features Audio Functions Analog Audio outputs Power supply for Radio section Antenna interface for Phantom power supply Auxiliary1 audio input FM Receivers electrical characteriztion AM Receivers electrical characteriztion RDS Test Annex1 Radio Test Description AUDIO AMPLIFIER CD-ROM DRIVE CDM-M10 drive CDM-M10 Power Supply Voltage CDM-M10 Operating Temperature CDM-M10 Vibration BLUETOOTH GPS Block Diagram Architecture AXIS ACCELEROMETER OPTION: DUAL DAB OPTION: HD RADIO OPTION: VICS OPTION: SDARS SDARS Module Type Approval FPGA Configuration OPTION: ASD PCB /145

6 Main Board PCB Power Board PCB EMC CONCEPTS /145

7 1 BMW Entry Nav RFQ INTRODUCTION 7/145

8 1 INTRODUCTION This document constitutes the Magneti Marelli Electronic Systems proposal to develop and industrialize the BMW Entry Nav Infotainment Head Unit. This document is intended to be considered as preliminary issue; contents and solutions need to be checked and/or discussed with the BMW technical team. 1.1 Document overview After a brief introduction in chapter-1, the Head Unit architecture is presented and described in chapter-2. This followed, in chapter-3, by the mechanical description of the design concept. Chapter-4 is describing the Hardware technical solution offered. Note: some documents (i.e. components datasheets, etc..) referenced in this one are strictly confidential and have been released to Magneti Marelli under NDA, therefore they are not included in the documentation CD. 8/145

9 1.2 Applicable documents (received from BMW) The applicable documents used for this answer to RFQ are the following: Optionen_ALH_ xls DOORS specification package Figure 1. Doors specifications index 9/145

10 1.3 Global presentation The BMW Entry Nav Head Unit (also referred in the document as HU) is a highly integrated hardware platform with a well defined features set, in 1-DIN format with remote display. Miscellaneous entertainment functions, like analogue and digital tuners, CD Audio Disks, MP3/MP4/DiVx from USB, will be combined with a multimodal MMI (voice recognition or haptic controller based) for vehicle settings, climate, entertainment, etc. Extensive navigation functions, including 3D Map as well as communication aspects (phone, telematics, browser,...) are included. Interconnection with the Car Network is provided with CAN (high speed) and MOST (25 Mbit/s); additionally an Ethernet link is present for housekeeping aspects. A standard MOST/CAN Gateway (UGW) and the complete MOST master functionality are included. The HU will be build on the Standard BMW Autosar Core 2.1. Figure 2. HU global view 10/145

11 2 BMW Entry Nav RFQ HEAD UNIT ARCHITECTURE 11/145

12 2 HEAD UNIT ARCHITECTURE The MM proposal is based on an evolution of the Viking Platform composed by a 1 DIN box, without front panel, that include a CD mechanism and the electronic PCB boards. The HW architecture will be modified in order to host BMW specific contents like BTwi to take advantage of technology evolution like the DDRII support. The electronics of HU is based on 4 boards - Logic Core Board (DB) - Main Board (MB) - Multimedia Board (MMB) [as an option] - Power Board (PB) The Logic Core Board includes the main CPU and Memories, while the Main Board includes most of the interfaces toward car s system. The Power Board implements the Audio Power Section, some specific interfaces and part of the power supply block, while the multimedia functions, depending on destination markets, are implemented in the Multimedia Board. The concept is to have four different boards conceived with an optimized functional partitioning that allow the flexibility to cover variants and evolution of the platform at a reasonable cost. In this way it will be possible for instance to upgrade the logic core according to the market performance requirements in a given timeframe, by means of a replacement of the logic core board and without affecting motherboard, resulting in benefits in terms of development cost and validation. The cost is optimized too by building a large and rather simple PCB (MainBoard) and packing the high integrated component on a smaller and more complicated one (Logic Core Board or Daughter board) Variants and optional functions are implemented in the Main Board and Multimedia Board by means of depopulation and/or specific layout, while Logic Core and Power Board are stable in the various configurations with the exception of the memories size. 12/145

13 The different configurations are covered by the following partitioning: Main Board (Mother Board) One single PCB with several variants (BOM characterizations only and population/depopulation of component) according to variants/options required. Logic Core Board (Daughter Board) One single PCB with few variants (BOM characterizations only and population/depopulation of component) according to variant/options required. Power Board One single PCB integrating the audio power amplifier, the heat-sink, power supplies for external displays and connectors variants. Multimedia Board One single PCB with three variants: Double Tuner DAB (plus IBOC if required); US market (SDARS and IBOC); Japanese market (VICS). Figure 3. Modularity examples In figure above is shown an example of upgrade of the system by means of the addition or substitution of boards. 13/145

14 2.1 System synoptic The conceptual system overview of the MM proposal for the Head Unit is shown in the following figure: Figure 4. Head Unit System overview The gray boxes are optional and are NOT present on the basis product offered. The boxes with blue texts are designed and produced by HBAS 14/145

15 2.1.1 Option/Variant table In the following table is summarized the partitioning of the main functional blocks versus the content of the printed circuit boards. Table 5. HU Functional blocks partitioning Type Functional Block HU DB MB MMB PB Comment Core CPU x x ESOC3 or Tunnel Creek + ConneXt Core DDRII SDRAM Memory x x Total of 1 GB Core NAND FLASH x x Fast Boot, 512 MB CD CDM M10 (slim) x/v HU_HWNOCD: CD Module System Microcontroller x x MPC5668 Thermal FAN Module x x Thermal Thermal sensor x x Thermal Heat Sink x x Prot Reverse Battery protection x x PSU RAD_ON x x Multifunction (signal/power) output interface 15/145

16 Functional Type HU DB MB MMB PB Comment Block BT Bluetooth 2.1 EDR x x HBAS module NAV GPS receiver x x NAV Managed NAND x x 16 GB of managed NAND FLASH NAV 3 axys accelerometer o o Japanese market only NAV Gyroscope o o NAV SD card holder o o USB 3x USB 2.0 Controller (Host) x x USB USB1 2.0 Port 5V/750mA, over-current protection; x x (customer) short-circuit protection USB USB2 2.0 Port HU_HW2USB: 5V/750mA, over-current o o (customer) protection; short-circuit protection HU_HW3USB: (Combox-green) USB3 2.0 for NAD communication; 5V/750mA, USB (Combox-green) o o over-current protection; short-circuit protection 100 MBit Fast Ethernet. ETH Ethernet x x The compliance with the IEEE 802.3u standard should not be affected UART UART interface o o UART for Log & Trace ipod DRM Chip x x HU_HWAPPLEAUTH: Apple Authentication-Chip CAN CAN HS x x MOST MOST Controller o/v o/v HU_HWNOFOT MOST FOT Transceiver o/v o/v HU_HWNOFOT VIP VIP Processor HU_HWFBAS o/v o/v (SAF7115) CVBS_IN 2x CVBS Video IN o/v o/v o/v HU_HWFBAS 16/145

17 Type Functional Block HU DB MB MMB PB Comment Power supply for main CID PSU_CID PSU CID x x (KL31, 8V) LVDS LVDS_Out CID x x Tel_Mute Tel_IN Audio Mute (Tel_Mute) Mono LF Input (Tel_IN) MIC_IN Microphone input x x x x x x LVDS connection to Central Display CID (with single SPI on LVDS Sideband). Re-configurable control input for external navigation or special vehicle support Mono LF input for external navigation device Speech recognition and telephone functions MIC2_IN Microphone input o o Telephone functions AUX_IN Auxiliary input x x x Stereo Input Audio_OUT Audio Power Amplifier x x This output will be used for Stereo and HiFi. Not for Top HiFi (audio output via MOST) Radio/Audio Radio DSP x x NXP SAF7741HV (Dirana II) ASD Microcontroller o o MPC DAC RSE 2x audio stereo out o o Only with MOST AM/FM FM1/AM1 Phase Tuner Diversity Tuner x x AM/FM PD FM2/AM2 Phase Tuner Diversity Tuner x x TMC Tuner TMC (RDS) Tuner x x 2DAB Dual Tuner DAB module module o/a o/a HU_HW2DAB or HU_IBOC SDARS SDARS Double Tuner module 4.5 o/a o/a HU_HWSDARS VICS VICS Tuner o o For Japanese market only MSA MSA cranking profile x x HU_HWMSA Legend: x = Base; o = Option; v = Variant; a = Alternative; HU = Head Unit; DB = Daughter board; MB = Main board / Mother board; MMB = Multimedia board; PB = Power board. 17/145

18 3 BMW Entry Nav RFQ MECHANICAL DESCRIPTION 18/145

19 3 MECHANICAL DESCRIPTION 3.1 HU Perspective views Figure 6. - perspective front view Figure 7. - perspective rear view 19/145

20 3.2 Exploded view Figure 8. - HU exploded view 20/145

21 Table 9. - HU PRO mechanical partlist Designation Material nr Note Silver Box DX52D + Z100 MB (ENI10130) 1 Power Board + Heat sink 1 Fan 1 Mother Board PCB FR4 1 Daughter Board PCB FR4 1 Central Part PC + ABS 1 Multimedia Board PCB FR4 1 CD Reader 1 Top Cover DX52D + Z100 MB (ENI10130) 1 Finishing Part: Sputtering or pulverized vacuum deposition Overall dimensions: volume) Weight: outer dimensions like BMW CAD-model PF17705 (rear connectors are out of about 1.5 kg Figure Silver Box 21/145

22 Figure 11. Power Board + Heatsink Figure 12. Mother Board & Daughter Board 22/145

23 Figure 13. Central part + Fan Figure 14. Multimedia Board MMB 23/145

24 Figure 15. CD Reader Figure Top Cover 24/145

25 3.3 Subassembly Groups views Figure Group A: Silver Box + Mother Board & Daughter Board 25/145

26 Figure Group B : Central Part + Fan + Multimedia Board + Power Board Figure Group C: Group A + Group B 26/145

27 4 BMW ENTRY RFQ HARDWARE ARCHITECTURE 27/145

28 4 HARDWARE ARCHITECTURE 4.1 External Connectors The HU is connected to external devices in the car by the following connectors: 1x 2+40 FAKRA Radio Connector (P1) it includes: a MiniFuse to protect the system against overcurrent; a FOT Connector for Optical link over MOST. 1x LVDS Connector 2x AM/FM Connectors (used even for IBOC as an option) 1x GPS Connector 3x USB Connectors (2x as an option) 1x BT Connector The Modular design allowes to include the following optional connectors, to cover the different variants of the system: OPTION SDARS: 1x RF Connector for SDARS Antenna Connector OPTION Dual DAB: 2x RF Connectors for Dual DAB The display power supply will be delivered using the LVDS connector exploiting the differential nature of the LVDS and decoupling technique, in order to save pins and use only one radio connector. No Front Bezel nor Front Bezel Connector are implemented in this proposal. The following picture describes the rear panel of the HU, showing the position of the connectors. Figure 20. External Connectors Overview 28/145

29 4.1.1 Fakra Radio Connector The 40 vias Radio Connector is Fakra type by Molex and it is proposed with the following pinout: Note: the pinning of the following table is just a list of the pins signals and their relative positioning in the connector side; the final pin assignment will be fixed upon agreement with customer. Table 21. Proposal Pinning of Fakra Radio Connector (40 vias) - Coding Side A B Pin # Name Direction Interface Type Comment 1 LF Right Rear+ Output Audio Power Speaker 2 LF Right Front+ Output Audio Power Speaker 3 LF Left Front+ Output Audio Power Speaker 4 LF Left Rear+ Output Audio Power Speaker 5 LF Right Rear- Output Audio Power Speaker 6 LF Right Front- Output Audio Power Speaker 7 LF Left Front- Output Audio Power Speaker 8 LF Left Rear- Output Audio Power Speaker High Side Switch 9 RAD_ON Output and shut down. Output with overcurrent/overvoltage protected Power controlled by uc and timers for start-up 10 HS CAN+ I/O Data CAN Interface High speed CAN, dual wire differential + 11 UART_RX Input UART interface Debug UART interface RX 12V battery switched power supply; it 12 KL30B Input (I) Power_battery switches off 1 to 30 minutes after engine is off. 13 HS CAN- I/O Data CAN Interface High speed CAN, dual wire differential - 14 UART_TX Output UART interface Debug UART interface TX 15 Not Used - - Spare pin 16 KL31 Ground Output (I) Power_gnd Main ground power. 1 CVBS1_IN + Input Video input CVBS differential + 2 MIC1_Shield Input shield Shielding Mic1 3 MIC1+ Input Analog Microphone input 4 Tel LF + Input LF Input Tel IN mono differential LF input + 5 Tel Mute Input On-Off 6 CVBS2_IN + Input Video input CVBS differential + 7 CVBS1_IN_GND Input gnd Analog ground CVBS ground Video input 8 CVBS1_IN_Shield Input_shield (shield) CVBS shield 9 MIC1- Input gnd Analog ground Mic1 10 Tel LF - input Analog Tel IN mono, differential LF input - Video input 11 CVBS2_IN_Shield Input_shield (shield) CVBS shield 29/145

30 Side Pin # Name Direction Interface Type Comment 12 CVBS2_IN_GND Input gnd Analog ground CVBS ground C 1 100bASEt_TX+ Out - Data HS data Ethernet differential TX bASEt_RX+ In - Data HS data Ethernet differential RX+ 3 MIC2_Shield Input shield shielding 2 nd Microphone shielding 4 MIC2+ Input Analog 2 nd Microphone positive input 5 AUX_IN_R Input AUX-IN (stereo) AUX-IN Right 6 AUX_IN_Shield Input AUX-IN (stereo) AUX-IN Shield 7 100bASEt_TX- Out - Data HS data Ethernet differential TX bASEt_RX- In - Data HS data Ethernet differential RX bASEt_OnOff Input On-Off Ethernet On-Off switch signal 10 MIC2- Input gnd Analog ground 2 nd Microphone ground 11 AUX_IN_L Input AUX-IN (stereo) AUX-IN Left 12 AUX_IN_GND Input AUX-IN (stereo) AUX-GND Figure 22. Fakra 2-40 pin (cfr DOC404_967) 30/145

31 4.1.2 FOT Connector The FOT Connector in inserted in the 40 vias Fakra Connector. A Pigtail connects the FOT connector to the Main Board, where is located the Optical Transceiver. The FOT Connector pinout is the following: Table Pinning of FOT Connector Pin Interface Name Direction No. Type 1 FOT_TX Output Optical signal 2 FOT_RX Input Optical signal Comment 31/145

32 4.1.3 AM/FM Connector (AM/FM1) The connector for the AM/FM band is a FAKRA type connector as per BMW requirement. MM proposal is to use a HS Fakra type connector. Table 24.- Pinning of AM/FM antenna connector (BMW Drawing No , coding A, color Black - ( ref. DOC404) MM proposal: HS, coding A, color Black Pin No. 1 Name AM/FM Signal 2 Housing Gnd 3 Housing Gnd 4 Housing Gnd 5 Housing Gnd Direction Input Interface Type AM/FM RF signal Type Comment AM/FM Connector (AM/FM2) A Fakra type connector for the use of a Phase Diversity antenna is offered. The Huber+Suner Fakra type connector (or equivalent) will fulfill the BMW requirements. Table Pinning of AM/FM Phase Diversity antenna connector (ref. DOC404_70) (coding B, color white RAL 9001, according to BMW Drawing No ). MM proposal: Huber+Suner Fakra connector, ARC type, Coding B, color white Pin Interface Name Direction No. Type 1 AM/FM signal Input RF 2 Housing GND Input grounding 3 Housing GND Input grounding 4 Housing GND input grounding 5 Housing GND input grounding Type Comment 32/145

33 4.1.5 GPS Antenna Connector A Fakra type connector for the use of a GPS external antenna will be added for the optional GPS functions. The corresponding interface inside the Main Board will be added by population of the assembled board. Table Pinning of GPS antenna connector (ref. DOC404) (coding C, color Blue RAL 5005, according to BMW Drawing No ) MM proposal: Huber+Suner Fakra connector, color Blue, coding C Pin Interface Name Direction No. Type 1 GPS signal Input RF 2 Housing GND Input grounding 3 Housing GND Input grounding 4 Housing GND input grounding 5 Housing GND input grounding Type Comment 33/145

34 4.1.6 OPTION: DAB (DMB) Antenna Connectors (L-Band and Band III) Two extra Fakra connectors as per BMW requirement will be added on the rear panel for both the external DAB L-Band Antenna and DAB Band III antenna. The interface for the dual DAB antennas will made available on the Multimedia Board which is plugged on the Main Board. Table 27.- Pinning of DAB L-Band antenna connector (ref. DOC404) (BMW Drawing No , coding E, color green RAL 6002.) MM proposal: Huber+Suner Fakra connector, color green, coding E Pin Interface Name Direction No. Type 1 DAB signal Input RF 2 Housing GND Input grounding 3 Housing GND Input grounding 4 Housing GND input grounding 5 Housing GND input grounding Type Comment Table 28.- Pinning of DAB Band III antenna connector (ref. DOC404) (BMW Drawing No , coding K, color curry yellow RAL 1027.) MMProposal: Huber+Suner Fakra connector, coding K, color yellow Pin No. Name Direction Interface Type 1 DAB signal Input RF 2 Housing GND Input grounding 3 Housing GND Input grounding 4 Housing GND input grounding 5 Housing GND input grounding Type Comment 34/145

35 4.1.7 OPTION: SDARS Antenna Connector A Fakra type connector for the use of a SDARS external antenna will be made available for the optional SDARS variant functions. Because SDARS variant and DAB variant are mutually exclusive, no extra space is required for the SDARS Antenna, therefore the SDARS antenna will replace the DAB Band-III antenna position. The corresponding interface for SDARS is implemented in the Multimedia Board SDARS variant which is plugged on the Main Board. Table 29.- Pinning of SDARS antenna connector (ref. DOC404) (BMW Drawing No , coding H, color violet RAL MMProposal: Huber+Suner Fakra connector, coding H, color violet Pin No. 1 Name Direction SDARS signal Input RF Interface Type 2 Housing GND Input grounding 3 Housing GND Input grounding 4 Housing GND input grounding 5 Housing GND input grounding Type Comment SDARS connector replaces the DAB III connector for SDARS variant. 35/145

36 4.1.8 LVDS Connector (CID) The LVDS Connector is the interface between the HU and CID display. MM Proposal is to use Rosenberger HSD type connector for the LVDS output signals, according to BMW requirement. Table Pinning of P3 LVDS Connector (6 vias)- (ref. DOC404) (BMW drawing No coding "D", color bordeauxviolet). MM Proposal: Rosenberger HSD type, coding D, color bordeaux violet Pin Interface Name Direction No. Type 1 High Speed SDOUT+ output Data 2 SDIN- input Grounding 3 High Speed SDOUT + output Data 4 SDIN- input Grounding Housing GND input shielding 5 Pwr CID+ output Power 6 Pwr CID- output Power Type Comment Figure 31. Rosenberger HSD 99S20D-40MA5-Y 36/145

37 4.1.9 USB1 HSD Connector (USB 2.0) The USB1, USB2, USB3 interface connectors will use an High Speed Data connector, according to BMW requirements. The connector will be provided on the main board. The interface is backward compatible with USB 1.1 and USB 1.0 standards. Table 32.- Pinning of USB1 external connector (BMW drawing No coding "B", color white.) MM Proposal: Rosenberger HSD type (EMI shielded version), coding B, color White (to be agreed with BMW) Pin Interface Type Name Direction Comment No. Type 1 GND Ground Ground connection 2 High High Speed data differential Data - I/O Data Speed negative data 3 Power Vcc Output Power Supply +5V, 700 ma Supply 4 High Data High Speed data differential I/O Data Speed + positive data Housing GND Housing Housing is connected to ground OPTION: USB2 HSD Connector (USB 2.0) A second USB 2.0 connector is provided. The High Speed interface for this second USB is provided in the Main board. The interface of this USB is backward compatible with USB 1.1 and USB 1.0 standards. Table 33.- Pinning of USB2 external connector (ref. DOC404_1441) (BMW drawing No coding "C", color blue.) MM Proposal: Rosenberger HSD type (EMI shielded version), coding C, color Blue (to be agreed with BMW) Pin Interface Name Direction No. Type Type Comment 1 GND Ground Ground connection 2 Data - I/O Data High Speed data High Speed data differential negative 3 Vcc Output Power Supply Power Supply +5V, 700 ma 4 Data + I/O Data High Speed data High Speed data differential positive 37/145

38 Housing GND Housing Housing is connected to ground OPTION: USB3 HSD Connector (USB 2.0) A third USB 2.0 connector is provided for NAD operation. The High Speed interface for this third USB is provided in the Main board. The interface of this USB is backward compatible with USB 1.1 and USB 1.0 standards. Table 34.- Pinning of USB3 external connector (ref. DOC404) (BMW drawing No coding "E", color green) MM Proposal: Rosenberger HSD type (EMI shielded version), coding E and color Green Pin Interface Name Direction No. Type Coding Comment 1 GND Ground Ground connection 2 Data - I/O Data High Speed data High Speed data differential negative 3 Vcc Output Power Supply Power Supply +5V, 700 ma 4 Data + I/O Data High Speed data High Speed data differential positive Housing GND Housing Housing is connected to ground Short circuit protections Protection of output pins against short circuit to ground and to battery will be provided, according to the internal rules of Magneti Marelli and to customer requests. Reference: [1] BMW DOC 404, sec [2] Rosenberger HSD, High Speed Data Connector, catalog /145

39 4.2 Hardware System Architecture Block Diagram The Block Diagram of the hardware architecture for the HU is shown in the following pictures. Figure 35. HU Block Diagram The gray boxes are optional and are NOT present on the basis product offered. The boxes with blue texts are designed and produced by HBAS In the next sections the main blocks will be described. 39/145

40 4.3 Power Supplies Power Supply Operating Range The system is over-current protected with a Minifuse integrated in the Main Connector. The Minifuse limits the current from KL30B at a typical value of 15A (to be confirmed for the B Sample). The HU is powered by the KL30B supply line that is switched OFF some minutes after that engine is off. A KL30B voltage sensor using standard design technique will be implemented in the HU in order to measure the level of the battery voltage and to implement the required strategy of over/under voltage. The following table summarizes the proposal for the main threshold of the power supply range. Table 36. Proposal of Power Supply Range (KL30B) (Ambient temperature) Pin Power Supply Range Min Typ Max Comment No. KL30B Operating Voltage Range 6.5V 16V Full Operation Short Over-OverVoltage KL30B 6.5V 18V No Damage Range KL30B KL30B KL30B KL30B Overvoltage Recognition Threshold Recovery from Max Overvoltage Threshold Under Voltage Recognition Threshold Recovery from Under Voltage Threshold 16V Audio Mute, RAD_ON Off 15.5V Audio Demute, RAD_ON On 9V 9.5V KL30B Low Voltage Release OFF 6.5V KL30B Recovery Voltage from Release OFF Audio Mute, RAD_ON On, MOST error storing start. Audio De-mute, RAD_ON Off, MOST error storing stop. MOST and FOT OFF are allowed; target is to have this limit as low as possible. Able to be waked up via MOST and forward signals Depending on the final implementation and design, suitable thresholds will be fixed in order to overcome the ±150 mv tolerance required, whilst maintaining the overall requirement about Over/Under Voltage recognition threshold and operating range. For example, assuming a threshold of 17V for the short OverVoltage (18V max), the tolerance can be relaxed without reducing the operative range. Reference [1] BMW DOC404 7V 40/145

41 4.3.2 Temperature Range MM proposal for the Operating Temperature Range is based on the maximum internal air temperature admissible inside the box of the HU. The proposed operating temperature range is summarized in the following table. Table 37. Proposal for Internal Air Temperature - Operating Range PCB Board Main Board MMB DAB / SDARS Logic Core Board Power Board Temperature Range Min Typ Max Unit Operating Ambient Temperature range Operating Ambient Temperature range Operating Ambient Temperature range Operating Ambient Temperature range C Full Operation* C Full Operation* C Full Operation* C Full Operation * Comment * Thermal Management based on hardware and software strategy will be provided in order to maintain the internal temperature inside the HU box according to the operating temperature range of the product. Then some countermeasures could be applied to keep under control the internal temperature (i.e. fan speed variations, volume limitations, turn-off of not used functional blocks, etc) Mode of Operation vs Power Supply The HU will operate in 11 modes of operation (status of the system). These modes of operation have impact on the power supply management for both the hardware and software issues, and will be taken into account for the design of the system power supply. Of course, the most important modes of operation for electronic design, are the Mode 0, Mode 1 and Mode 2: sleep current minimizing on Mode 0, transition from the sleep and the wake-up events on Mode1 and the power dissipation on Mode2. The table below summarizes the modes of operation taking into account the wake-up events and power supply of the function involved. Table HU Mode of Operation - (ref. DOC404_31) Mode Entering Active Function - Comment Mode 0 Sleep No CAN bus activity or No Optical MOST bus activity; Clamp 30B (KL30B) is active and will be active for at least 1 Supply of CAN and Optical Receiver (FOT) + necessary wake-up events (CD media insertion) Sleep current > 100uA is Necessary to maintain in sleep mode the wake-up blocks (see dedicated section about Sleep Current Consumption). 41/145

42 Mode Entering Active Function - Comment Mode 1 Wakeup Mode 2 Master Mode 22 Shutdown Mode 3 Application Mode 4 Clamp 30 Entert. Mode 5 Delay Mode minute. Sleep Mode and WakeUp via Eject key, ETB (Entertainment button), insert CD, FSTP, CAN Wakeup, MOST Wakeup. KL30 B turned ON. The wakeup conditions in Mode 1 was CAN or MOST. (No buttons) The timer 2 ends in mode 2 Terminal R or Terminal 15 = active (KL15); KL30B, active turned- ON Clamp 30B (KL30B) is active When a phone call is active there is a clamp change from Clamp R or 15 to Clamp 30. Information on R and 15 terminal come from network CAN or MOST. Mode 0 and supply of all necessary applications (CD must be supplied in order to sense commands). Mode 0 + Communications, Full power master, Wakeup Otpical Link, GW MOST/CAN, The same of Mode 2 Full functionality (CAN, MOST, NAV, GPS, BT, etc) Wake up coming from CAN or MOST. HU is fully supplied and application interface are supplied if necessary. (Handsfree audio function, Telephone MMI depending on MMI spec, interaction with the system must be possible) At next start-up the drive recognizes a No CD or new CD inserted condition. No wakeup from Buttons is provided. No wake-up via eject button is provided, because no buttons are managed by HU proposal, 2 independent timers are necessary, Timer1 (20sec default) for wakeup and Timer 2 (15s default) for the go-on sleep. No Terminal R nor Terminal 15 (KL15) are monitored by HU; these signal are supposed to come from CAN messages. MM Assumption is that all the wakeup signals not directly wired on the HU (e.g. buttons) are coming from CAN or MOST. Assumption: when engine is off, the HU activities (eg. telephone call) will last for a time duration depending of the Clamp 30B elapsed time. Therefore the telephone call shall have a maximum duration taking into account the maximum time of system shut-down. When a phone call is active there should be a change from Clamp 30B to Clamp 30. But HU cannot manage this change. Mode 6 FeTraWe Mode 7 PowerDown tbd tbd tbd Power Down command is expected to come from CAN/MOST messages. This is a diagnosis mode where the headunit has to be in mode 0 within 5 seconds Normal startup from Mode 7 can be achieved only when Clamp 30B is active, and status of terminal 15 or terminal R come via CAN / MOST messages. Electrical shut-down, with proper sequence for power supply turn- 42/145

43 Mode Entering Active Function - Comment Mode 8 Flash Mode off will be implemented by HW/SW functions. tbd tbd tbd Mode 9 Sleep-Delay HU is in State 2/22 CAN and MOST status from active to inactive Clamp 30B timer is >xx minutes All the active functions in the previous Mode Power supply The main concepts of the HU power supply proposed architecture are the following: Power Board - High current path and interface to the main supply rail are concentrated on the Power Board (PB) that includes also the audio power amplifier. The power board feeds the main board with a protected battery voltage power rail. This solution allows to control and dissipates the power thanks to the heatsink which is directly in contact with the Power Board PCB in the rear of the box. - A Minifuse, the reverse battery protection, the over-voltage protection and the total current limitation will also be implemented in the power board. - The overall current flow of the HU is guaranteed by the Power Board that is also responsible for the correct power supply protection and filtering. The current sink from the Power Board flows into a unique supply rail and after a reverse battery protection switch (SW1) and an overvoltage switch (SW2) goes to the two main loads: the audio power amplifier in the Power Board and the remaining loads of the systems (MB, DB, MMB). Filtering - Separated filtering are used on the power rails for audio power and system boards in order to ensure proper decoupling, improve the overall electromagnetic immunity and emission and to avoid interference and crosstalk The audio amplifier power supply will use locally filtering in order to reduce noise on the audio signals connected to the loudspeakers. Some components needs to receive the power supply directly from the Vbat signal, this is the case of the phantom antenna power supply signals and the battery voltage level measurement and monitoring; for this a dedicated supply rail, reverse battery protected, is delivered from the PB to MB. Main Board - On the Main Board (MB) will be implemented the power supply regulators to serve as central supply for the on board peripherals; the main board delivers the supply rails at 5V (5.2A max), 3V3 (3.5A) and battery voltage as derivation at low current from the power board. Dedicated step-up-down dc/dc 43/145

44 converter will be used to generate the 8 volt for the CID and for the CD drive (3.3A) and in order to supply low voltage logic chip, 2V5 (0.2), 1V2 (0.2) and 1V8 (1.2A) rails are generated from 3V3. A smart power High side switch will be used to for the multifunction output signal RAD_ON. The high current DC/DC regulators present on the MB are all synchronous in order to improve the efficiency of power supply architecture. In particular the controller Maxim MAX15026, used to provide 8V, 5V and 3.3V rails, has external N-MOSFET transistor and Texas Instrument TPS54218, used to provide 1.8V voltage, is synchronous and monolithic (both high side and low side transistors are integrated). In the follow block diagram is shown the power supply architecture for the Main Board: DC/DC (1) Step up/down Enable CD-ROM M8, Display V: 8 V Imax: 3.3A DC/DC (2) Step down Enable Imax: 5.2 A Logic Core, USB, CAN, SDARS V: 5V Imax: 5.2 A BATTERY Vin: 6.5V-18V (operating) DC/DC (3) Step down Enable Imax: 3.5 A Logic Chip Supplier V: 3.3V Imax: 2.8 A Fq.Sw.: > 1.7 MHz MAX quiescent current: 400 ua T: -40 /+85 DC/DC (4) Step down LDO (1) LDO (2) Logic Chip Supplier V: 1.8V Imax: 1.2 A Logic Chip Supplier V: 2.5V Imax: 0.2 A Logic Chip Supplier V: 1.2V Imax: 0.2 A DC/DC (5) Step down uc, CAN PHY, MOST PHY V: 3.3V_SB Imax: 420 ma - DC/DC (1) (2) (3) Maxim MAX DC/DC (4) Texas Instrument TPS DC/DC (5) National Semiconductor MAX LDO (1) (2) Texas Instrument TPS73201 Logic Core 44/145

45 - Logic Core Board (DB) receives 5V power supply rail and produces locally the power supplies blocks needed to feed the high speed, high frequency logic circuitry and devices (CPU and Memories); moreover, the concept of a de-location topology allows a quicker response to a rapid current consumption decreasing the inductive value of power path and improving ground noise. Medium current (>150mA) low voltages supply will be derived from 5V power rail using high frequency switched dc/dc converter in buck configuration (Step Down configuration). The local supply concept together with the High Frequency switched mode (>1.7MHz) of buck regulators allows to reduce ground noise that can impact on the radio receivers, as well as to reduce crosstalk, interference, emissions and immunity aspects. A tradeoff will be evaluated and fixed in order to reach the optimal compromise among switching for dc/dc converters, standby current, emission and cost. Multimedia Board - Multimedia Board (MMB) receives battery voltage, 5V and 3V3 power rails from the Main Board; the low current battery power rail will be used to feed the antennas interfaces while the 5V and 3V3 to feed directly or via decoupled local regulators the medium currents loads (DAB and SDARS module). Locally decoupling - Both LDOs and Step Down regulators will have on the input and output pins several decoupling capacitors at different values that provide local filtering in a wide frequency bandwidth. Further, appropriate values of capacitance near to high switching device will be used in order to make the response to an instantaneous consumption more reactive. Quiescent currents - MM proposal is based on using devices with shut-down and quiescent currents as low as possible to reduce the sleep current consumption at a minimum value. Moreover, mixed HW-SW strategy aimed to further decrease the sleep current will be analyzed carefully as well Reverse battery protection The reverse battery protection will be designed using a back to back configuration of very low on resistance and high current power MOSFETs. This proposal will reduce drop voltage and power dissipation respect to other traditional solutions using direct forward schottky diodes. The actual implementation will be done with two Power N-Channel MOSFETs. The application circuit, used and tested in similar application is shown in the following figure and is built around two FDD8870, Q1 and Q2, featuring a maximum Rdson of 60mΩ at VSG of 10V and 175 C of Tj. The power devices FDD8870, or similar equivalent device, will have a DPACK(TO252) package capable to handle more than 30A. The both the MOS are always ON during normal condition while will be automatically turned OFF on reverse battery condition, allowing to block any reverse current thanks to the reverse biased internal diode. Both the NMOS will be turned OFF in over-voltage condition in order to disconnect all loads. The controlled signal will be derived directly from standard discrete circuitry that monitor the battery status, or as alternative, will derived from a mixed hardware/software solution involving the controller of the Main board. 45/145

46 Figure 39. Reverse Battery and Over-voltage application circuit RAD_ON MM HW proposal is to implement this function with an High Side switch connected to the power supply rail with a Rdson that fulfill the request (1V drop at 500mA); the switch is controlled by the microcontroller. Short circuit to ground protection will be provided. The RAD_ON switches will be built around an High Side, smart power switch device like the BSP452 by Infineon. A shottky diode (1A, 40V reverse) will be provided in series connections to avoid spurious recirculation currents flowing from external load and injected inside the HU. Table Specification for the Head Unit as RAD_ON Source [DOC404_267]: 46/145

47 Content symbol conditions min max Operating voltage for RAD_ON UB? UBmin [1] and CAN activity Current to drive the sink IL 500mA Capacitive load CL 500µF Voltage loss Kl.30-RAD_ON IL=Imax 1 V Rise time RAD_ON IL=Imax, CL=10nF Fall Time RAD_ON RL=10kOhm, CL=10nF 1 ms Automatic Overload protection available The RAD_ON signals will be used for (ref. DOC404): - The analogue mute / de-mute control for the HiFi Amplifier is done by the RAD_ON signal will be used - The RAD_ON signal is also used as the pwer supply for the external Antenna Amplifier. Table Specification for the sum of all sinks on RAD_ON: Content conditions min max Current of all sinks V 500mA Total Capacitance of all switch-on 500µF Total Capacitance of all switch-off 10nF Impedance of on sink V <10kOhm Inductive switch-off Recovery diode needed Current Consumption A first estimation of the total current consumption for the loads present on the Power Board, on Main Board, on the Logic Core Board and on the Multimedia is described in the following table: Table 42. Max Average Current Consumption of MBoard, MMBoard, Daughter Board Max Battery Voltage [V] Max Current [A] (MB, MMB, DB) Current of Power Amplifier in PBoard [A] The data of the above table have been estimated by averaging typical and maximum current consumption of main devices, taking into account an efficiency of 90% for dc/dc and 99% for linear regulator. Then the results have been compared with actual data of similar product. A first estimation for the absolute maximum current gives a value of 12.5 A. The maximum current is reached at a battery voltage of 12V. 47/145

48 Therefore, a Minifuse of 15 A is the starting value for strong current limitation. The final type and rated current will be fixed on B sample design. Temperature sensors will be implemented in order to measure the ambient temperature around the most critical chips and activates software thermal management strategy in order to keep the air temperature inside the HU box under the maximum allowable by the electronics devices Sleep current consumption The low current consumption in sleep mode has several impact and depend on the system requirements listed below: CAN Wake Up (sensing of the CAN Bus activities must be supplied) Optical MOST Wake Up (sensing of the Optical Transceiver must be supplied) CD insert monitoring (sensing of the CD insert switch must be supplied) Stand-by current of GPS section (clocks). Sleep Current must be achieved within 45 seconds, after the shut-down of the HU. In our proposal, the transition from the stand-by state to the operative state can be forced by three different waking events, after KL30B is turned On: CAN signal MOST activity Insertion of a CD media on the CD drive All these events are managed by the microcontroller (uc) device present on the Mother Board. The same uc wakes the overall system enabling the not-standby power supply regulator in according to the appropriate power-on timings of the components in the HU. This procedure requires that the u-controller stay in a low power consumption state, called sleep mode, when the HU is turned off. In sleep mode condition the uc works at lower frequency than the operative frequency and only the wait circuits are supplied in order to allow a very low current consumption. In the following table is showed the current consumption of devices supplied in stand-by mode. The current consumption is considered at a battery voltage value of 12 V : Table 43. Typical Sleep current 25 C Device enabled in Standby Working voltage Current 25 C GPS 3.3 V 25 ua FOT MOST 3.3 V 20 ua CAN Vbat 30 ua ucontroller 3.3 V 160 ua 48/145

49 Device enabled in Standby Working voltage Current 25 C Reset circuitry 3.3 V 20 ua Battery voltage comparators Vbat 260 ua Total Sleep Current at 25 C, 12V 400 ua The Sleep Current will be less than 400 ua in the above mentioned condition. However, design effort will be done in order to use components and circuit that will reduce this value. Note: the previous value of 400 ua already include the loss of the stand-by regulator at 3.3 V Thermal Management In the previous section, the maximum peak current has been estimated in order to fix a target for the design of power supply blocks and define a limit for the absolute maximum input current of the HU. From that data a maximum peak input power can be estimated in about 150W considering a maximum peak input power of the Audio amplifier of 96W. Data coming from experimental results and for analogy with similar telematics product in production since many years, show that the maximum average power dissipation range between 20% and 40% of the total peak power, considering realistic operational power consuming activities of a complex telematic box of 1DIN. Hence, the resulting realistic power dissipation for the HU can be estimated around 25W plus the power dissipation required by the audio amplifier. Realistic max power dissipation for the Audio power is around 25W, considering an output power of 2W per channel. For comparison, the following pictures show the results of Flowterm simulations of a telematic box in the following condition: Dissipation power: 34 W (including 14 W due to Audio Power Amplifier) Ambient temperature (external temperature around the Box): 25 C Air Flow: 1.9 l/s Max Temperature inside the Box (Bottom of DB PCB): 45 C (delta temperature = 20 C) Max temperature of heat sink: 63 C (delta temperature = 38 C) The equivalent thermal resistance from the bottom of Daughter board PCB and the external ambient temperature, at power of 6 W is 20 C / 6 W= 3.3 C/W. The equivalent thermal resistance from top heat sink and the ambient temperature, at power of 14 W (Audio Power) is 38 C / 14 W= 2.7 C/W; for analogy, the target for the HU have to be less than 1.9 C/W to sustain a max power dissipation of 20 W inside the Power Board PCB; to reach this target the heat sink will be cooled down by the fan air flow. The major critical issues to take under control during development will be the following: The max temperature on external part of the HU Box (heat sink metallic parts of rear cover) cannot exceed the maximum temperature allowable of 100 C. Logic Core Board (DDRII SDRAM, CPU case temperature) 49/145

50 Maximum external temperature around tuner modules and IC devices. The major issues to address and take into account for thermal management will be: Size and weight of the HU Box Efficiency of fan air flow Multilayer PCB with extensively usage of thermal vias Selection of IC package with the lowest thermal resistance and maximum operating junction temperature (>120 C). HW/SW power management aimed to turn-off or configure in low power mode the functions or application software non active HW/SW configuration of audio power in High efficiency mode (switched class B mode) whenever possible according to the volume set and environment condition Thermal simulations and experimental measurements to check the implementation and increase confidence of the thermal simulation models used Thermal management based on control of fan air flow, aimed to maintain internal temperature inside the box under a reasonable limit, not exceeding the allowable operating ambient temperature of critical device (<85 C) up to 65 C of ambient temperature external to the HU box; it will take into account the following inputs: o HW/SW function activities o thermal sensor inside the box o thermal sensors inside critical devices (audio power, CPU, CD, tuners) 50/145

51 Figure 44. Thermal simulation example of telematic - at 25 C medium power (34W) Fan 1,9 l/s; deltat max = 40 C (heat sink); delta T max =25 C Bottom Logic PCB. 4.4 Fan module and temperature sensor A MM standard circuit solution made of discrete components will be used to drive the fan motor; the circuits allow maximum flexibility and low cost the fan will be supplied by a protected battery voltage. The drive circuit will be controlled with I/O port by the secondary microcontroller of the Main board. The electrical schematic, reported in the figure below, is a MM standard solution for this kind of application, suitable for a FAN with the following target characteristics (see mechanical section for more details): Rated Supply Voltage: 12V typical Operating Supply Voltage: 7 to 13.8V Minimum Starting Voltage : 4.5V at -30 C ; 7V at -40 C Input Power : 1.8W (max 2.4W) 51/145

52 Speed Max Air Flux 8000 RPM Operating Temperature: -40 to 85 C Pinning : Size: m 3 /min (268/60 dm 3 /s =4.47 lt/s) Positive+ (Red); Negative (Black); Speed (Blue) 40mm x 40mm x 10mm Detailed characteristics are reported on the following table and in the reference data-sheet. A SW thermal management, working in combination with information coming from hardware circuit and thermal sensor located in specific part of the electronics board, will be implemented in order to keep the ambient temperature inside the box at a safe temperature, not exceeding the rated ambient temperature allowable for each devices or module. The target is to control the fan in order to never exceed an internal ambient temperature greater than 85 C by exploiting the air flow capability of the fan that can deliver up to 4.47 liters per second. Extensive thermal simulation and tests will be executed in order to fix the design for the B Sample phase. Figure 45. FAN driver circuit example 52/145

53 4.4.1 MSA Support MSA support requires an extended operating voltage supply range from 8V up to 14.V according to GS general requirement (dynamic I), instead of the nominal operating voltage 9V Vbat 16V. The HU parts that have major impact on MSA support are the CD-ROM drive, the Power amplifier, the display and microphone interfaces. All these blocks require a supply voltage of 8V, but the Power Amplifier that at 9V of battery voltage is in un-mute state. These operating voltage ranges are not suitable for the operating voltage range required by the MSA, hence an extra performance is required to the HU to support the automatic start. The MM proposal is to design an HU able to be fully functional from 6.5 V up to 18 V. To obtain this goal in the Main Board is present a DC/DC converter step up/down for the critical voltage of 8V. The other loads are at maximum voltage supply value of 5V that can be reached with a minimum battery voltage of 6.5V. According to BMW requirements the Audio Amplifier could be set in un-mute state at a voltage lower than 9V, so it s not necessary to boost the battery voltage to supply it. 53/145

54 4.5 Daughter Board The Daughter Board (DB) is the central processing unit of the HU. It is based on the main CPU, the system FLASH and SDRAM memories; the DB include local power supply blocks derived from 5V power supply rail provided by the Main Board (MB). The DB is connected to the MB via a board-toboard, high frequency, connector (MXM pins). The Main Features of the Logic Core are: CPU: nvidia ESOC3 RAM: 1 GB DDRII SDRAM FLASH: 512 MB SLC RAW NAND FLASH At the DB-MB connector, independently of the CPU final choice, will be available the following interfaces: 1 Video In (ITU656) 1 Video Out drgb 24 bit 3 I2S/I2S TDM 3 SPI 3 USB* 2 I2C 3 UART 1 JTAG 2 SDIO (SD-MMC 4/8 bits) 7 IRQ 9 GPIO 1 Ethernet* Table DB - MB connector signals *Note: when the Ethernet interface is used the USB2 interface is not available CPU nvidia ESoC3 Following two images with the nvidia ESoC3 block diagram and main features. 54/145

55 Figure 47. nvidia ESoC block diagram Figure 48. nvidia ESoC3 main features 55/145

56 4.5.2 System Memories The System Memory will use 1 GByte of DDRII type SDRAM with a bus width of 16 bit, so eight chips will be required each of size 64 Mb x16 (128 MB). A Micron SDRAM DDRII like the MT47H64M16, in a FBGA84 package will be used A dedicated NAND high speed FLASH will be used in order to support a fast start up time. The system will be equipped with a minimum size of 512 MByte to store the main important application software that must be ready as soon as possible after the power on Power supply & reset The Logic Core Board will be supplied by 5V power supply coming from the Main Board. The local supply voltages will be derived from the 5V rail by step-down dc-dc converter and LDO regulators. The reason to use delocalized power supply concept is to maintain under control noise, power dissipation, as well as EMC immunity and emissions. The power supply blocks do have enabled signal controlled by the Main board s microcontroller. A Smart Reset with supplies voltage monitoring will be used for the Hardware reset of the logic devices; however, all the reset signal are OR wired with the control signal of the microcontroller of the main board Thermal management The target at maximum current will allow to avoid starvation of current during peak of activities for all the high speed devices (CPU, DDRII SDRAM memory). However, maximum average power output power lies in the 40% 60% range of the maximum output power. Localized power supplies dc-dc converters and LDO regulators will be used inside the Logic Core Board, in order to spread as much as possible the power dissipation through the allowable size of the PCB and avoid hot spot areas; moreover, using several power supply stages with moderate output power (less than 4W) will allow better flexibility for the layout design of PCB, and cost optimization. Thermal simulation will be carried out in order to manage the required power dissipation taking into account thermal resistance data, PCB layers and FAN air cooling. A big attention will be paid in order to exploit maximum efficiency of the thermal resistance of PCB (with extensively use of thermal vias) and device packages, as well as efficiency of the air flux of the internal fan Start-Up strategy The start-up procedure is initialized by the microontroller in the main board. The main concept of the start-up procedure after power on is the following: 1. Step1: uc in the main board is woken-up from sleep mode or turned-on from KL30B power on; after reset time, the ucontroller manage the following tasks: a. Enables power supply of the Logic Core Board to allow BIOS execution via SPI. b. Enable and configure MOST and CAN functions. c. Manage early communication for Gateway MOST/CAN. 56/145

57 2. Step2: Main CPU is booting from FLASH (BIOS NOR or DB NAND) 3. Step3: the system is awake, hence the full OS and the application SW can be downloaded run time form DB NAND FLASH and/or MB MMC NAND. Reference From BMW DOC404: Rear View camera picture shall be visible within 1s after system activation. Audio output of Parking Functions (PDC beeps) shall be available after 2s after system activation. Entertainment audio shall be available after 5s after system activation. MMI functions shall be available and usable after 8s after system activation. Navigation shall be available after 10s after system activation. Telephone, Online and ispeech shall be available after 15s after system activation DB to MB connector The board-to-board connection between the Main Board and the Logic Core Board will be performed with MXM 2.0 connector. The first assumption is to use a 230 pins connector that includes extra spare pins for VDD and ground. In the following picture is shown the version at 230 pins. Figure pins MXM 2.0 connector for MB-to-DB 57/145

58 4.6 Main Board Microcontroller The selected secondary microcontroller is the Freescale MPC5668G with the e200z0 and e200z650 cores. In the following figure is shown a top-level block dagram of the MPC5668G device. Figure 50. MPC5668G Block Diagram Main features of the Logic core: 32-bit CPU core complex (e200z MHz) 32-bit I/O processor (e200z0 58 MHz) 2 MB on-chip FLASH 58/145

59 512 kb + 80 kb (592 kb) on-chip ECC SRAM 16-channel Direct Memory Access controller Interrupt controller (INTC) supports 316 external interrupt vectors (22 are reserved) System clocks o Frequency-modulated phase-locked loop (FMPLL) o 4 40 MHz crystal oscillator (XTAL) o 32 khz crystal oscillator (XTAL) o Dedicated 16 MHz and 128 khz internal RC oscillators Internal voltage regulator allows operation from single 3.3 V or 5 V supply Package Parameters: Package type is 17 mm x 17 mm, 208 MAPBGA, Pitch 1.00 mm Module height (max) 2.00 mm Power Supply: 1.2V (Core); 3.3V (I/O) Peripherals: Media Local Bus (MLB) interface o Supports 16 logical channels, max speed 1024 Fs Deserial Serial Peripheral Interface (DSPI) o Four individual DSPI modules o Full duplex, synchronous transfers o Master or slave operation Inter-IC communication (I2C) interface o Four individual I2C modules o Multi-master operation Fast ethernet controller o Supports 10-Mbps and 100-Mbps IEEE MII, 10-Mbps 7-wire interface o IEEE MAC (compliant with IEEE edition) Controller Area Network (FlexCAN) module o Compliant with CAN protocol specification, Version 2.0B active o 64 mailboxes, each configurable as transmit or receive Analog to Digital Converter (ADC) 10 bits module 59/145

60 4.6.1 Reset Strategy The figure below shows the reset concept from the secondary microcontroller point of view. The microcontroller watches the Logic Core Board and the Peripherals. A SW reset management will be implemented in order to enable the power supply of the peripherals. Power Supply DB 3V3 SPI (w/ watchdog) Reset/ Enables Smart Reset HW_Reset ucontroller Enable_PS Reset Peripherals WatchDog Enable_PS Figure 51. Reset conceptual strategy MM proposal is to use a dedicated Smart Reset like the Maxim MAX809 or similar used to monitor the power supplies in the microcontroller. This circuit perform a single function: it asserts a reset signal whenever the VCC supply voltage declines below a preset threshold, keeping it asserted for at specific time delay (eg. 140ms for MAX809), after VCC has risen above the reset threshold. However, these kind of devices area is available in different versions (eg. Threshold, timing, reset output active Low/High, etc), so there is flexibility to choose the right version for the proper implementation of HU. The figure below shows a possible hardware design used to reset the microcontroller. 60/145

61 Figure 52. Hardware design for the reset of the uc Therefore the MPC5668G has integrated a hardware watchdog timer, useful to monitor the program executions and detects automatically defective programs Power Management The goal is to control the status of the battery in order to manage the system power management. Specific hardware circuits are used to know, for example, if the voltage of the battery is in a correct range of values or if it is under a specific threshold. A SW power management, working in combination with information coming from the hardware circuit will be implemented. The MPC5668G has the capability to reduce the power consumption. Infact, a power control is integrated inside the microcontroller. It can works in the following modes: sleep mode normal operating mode. MM proposal is to configure the secondary microcontroller in sleep mode because is the most powersaving. due to all oscillators and resonators are stopped. That is, the CPU and peripheral functions, perated by the CPU clock and peripheral clock, also stop. Even in this case the secondary microcontroller is able to handle the wake up for CAN via dedicated wake-up interrupt and from MOST via external interrupt pin. The figure below lists the current consumption in differents measurement conditions Thermal management MM proposal is to implememt a fan module together with a thermal sensor located in a specific part of electronics board in order to keep the ambient temperature inside the box at a safe temperature. The 61/145

62 goal is to control the FAN in order to never exceed an internal ambient temperature greater then 85 C. A SW thermal management, working in combination with information coming from hardware circuit will be implemented. In order to read the temperature from the thermal sensor, MM proposal is to use the A/D converter built inside the uc. The A/D converter consists of one 10-bit successive approximation A/D converter with a capacitive coupling amplifier. The result of an A/D conversion is stored into the A/D registers corresponding to selected pins. The fan speed is controlled with a PWM signal using an output compare of the microcontroller and measuring the fan speed through an input capture OPTION: UART MM proposal for log & trace purposes is tu use a standard UART interface directly connected to the secondary microcontroller (MPC5668) through an RS232 transceiver (the Maxim MAX3221E). In the following figure is shown the typical operating circuits: Main features of the MAX3221E: EIA/TIA-232 compliant Shutdown/wakeup features RS-232 transceiver Figure 53. MAX3221E - typical operating circuits 62/145

63 Package Parameters: 16 TSSOP Power Supply: 3V3-powered The MAX3221E is 3V3-powered and is connected to secondary microcontroller MPC5668. The MAX3221E contains just one driver and one receiver, making it the smallest single-supply RS-232 transceiver. The MAX3221E achieve a 1µA supply current with Maxim s revolutionary AutoShutdown feature. They save power without changes to the existing BIOS or operating system by entering low-power shutdown mode when the RS-232 cable is disconnected, or when the transmitters of the connected peripherals are off. 4.7 Managed NAND FLASH The selected 16 GBytes managed NAND is the Micron MTFC16GEK, available in the extended operating temperature range version (-40 C to +85 C). In the following figure is shown the functional block diagram of the managed NAND. 63/145

64 Main features of the selected managed NAND: Isolated MMC interface MMC controller and NAND Flash System voltage o VCC: V o VCCQ: V or V Power dissipation (These values are sampled and are not 100 percent tested) o Standby current (TYP): 90 ua o Active current (TYP): 90 ma Password protection Permanent and temporary write protect 52 MHz clock speed (MAX) 416 Mb/s data rate (MAX) Fully backward compatible with previous MMC modes Package 169-ball FPGA 12mm x 18mm x 1.4mm 64/145

65 4.8 CAN High Speed interface The CAN bus performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1 MBit/s. For the connection to the physical layer, high speed transceiver hardware is required: TJA1041 High speed transceiver NXP TJA1041 features are: Fully compatible with the ISO standard Communication speed up to 1 Mbit/s Very low Electromagnetic Emission (EME) Differential receiver with wide common-mode range, offering high Electromagnetic Immunity (EMI) Passive behaviour when supply voltage is off Automatic I/O-level adaptation to the host controller supply voltage Recessive bus DC voltage stabilization for further improvement of EME behaviour Listen-only mode for node diagnosis and failure containment Very low-current in standby and sleep mode, with local and remote wake-up Capability to power down the entire node, still allowing local and remote wake-up Wake-up source recognition Figure 54. CAN High Speed Mode of operation 65/145

66 Figure 55. CAN High Speed Electrical application Note: chokes shall only be fitted following approval from the appropriate authority (P/N TDK ACT45B P-TL001) The TJA1041 can operate in different modes, each with specific features. Control pins STB and EN select the operating mode. Normal operating mode is the mode for normal bi-directional CAN communication. The receiver will convert analog data on the bus signal (pins CANH and CANL) into digital data, available for output to pin RXD. The transmitter will convert digital data on pin TXD into a differential analog signal, available for output to the bus pins. Bus pins are biased at 2.5 Volt. The sleep mode is entered via the undervoltage detection time on either VCC or VI/O elapses before that voltage level has recovered or via C-CAN2_STB and C-CAN2_EN signals. In sleep mode pin INH is set floating. This pin is used to wake-up the system when CAN activity is detected on the bus. Termination resistor (R342 and R343) are provided for terminating/no terminating node implementation. The default value of Resistor termination is 120 Ω. The final value, to implement on B Samples, must be agreed with the customer. ESD protection is obtained placing close to bus connector pins (C_CAN_HS_L and C_CAN_HS_H) MMBZ27VALT1: ESD rating of class N (exceeding 16 kv) per the human body model Basic PCB design rules: 66/145

67 the module has a ground plane under the CAN transceiver on the component layer of the PCB no IC's between the CAN transceiver and PCB edge connector transceiver is placed as close as possible to the PCB edge connector CAN_H/CAN_L are routed together and the pair protected by guard tracks on the same PCB layer 4.9 OPTION: MOST INIC ROM The selected MOST network interface controller is the single chip OS81060, belonging to the SMSC Intelligent Network Interface Controller (INIC) family. Main features of the OS81060: Complete MOST Network Interface on a single chip Embedded MOST Network management o Network protection mode o Hardware and application watchdog timer o Intelligent muting Media Local Bus Port o Support all MOST data types o Eases inter-chip communication and streaming o MediaLB 3-pin interface at speeds up to 1024 x Fs o Legacy MediaLB 5-pin interface at speeds up to 512 x Fs Control Port support I2C format for control messages and asynchronous packets Streaming Port supports up to four serial interfaces for synchronous data Dedicated application reset output External switching power supply synchronazation output Persistent memory for storing internal INIC values during low power operation (MOST Sleep Mode) One-Time Programmable (OTP) memory for initial configuration settings (INIC Configuration String) Package Parameters: Package type is 6.00 x 6.00 mm, 40 QFN, Pitch 0.5 mm Module height (max) 0.90 mm Power Supply: Core (1,8 V); Peripheral (3,3 V) Figure below illustrates the OS81060, with the matching protocol stack implementation. 67/145

68 Figure 56. OS81060 Protocol stack The OS81060 is connected to the secondary microcontroller MPC5668G via the Media Local Bus (MediaLB) serial port. The MPC5668G control the INIC either via MLB or via I2C serial port. The Network port TX/RX connects the OS81060 to the Optical Tranceiver. Moreover, the streaming port is used to transmit a multiplexed digital signal, an I2S/TDM at 8 stereo channels, to the MOST Network. The bi-directional I2S/TDM channel connects the synchronous channel of Logic core with the external device connected to the MOST Network. The device is powered by a 3V3 and 1V8 supply voltages; a command for the Reset is managed. The Network Port can be configured as a network timing-master or timing-slave. As a timing-slave, the OS81060 internal timing is clocked from the recovered network clock. As a timing-master, the OS81060 internal timing and the network clock are determined by an external crystal. An internal PLL in the Clock Manager multiplies the external timing source for the generation of internal clocks. The receiver input pin (RX) is over-sampled by a high-frequency clock and data is recovered by a digital state machine. The MediaLB Port is the primary interface between the EHC and the OS81060, and supports all types of data transport methods supported by the network. The Control Port is the second interface between 68/145

69 the EHC and the OS81060, and supports message-based packet and control data. The Control Port also allows the EHC to enable and configure the MediaLB Port. The Streaming Port provides a gateway for high-speed streaming data between the OS81060 and external legacy devices such as ADCs, DACs, or co-processors. Some Streaming Port and MediaLB Port modes are mutually exclusive. After reset, the OS81060 automatically interacts with the network, performing all necessary low-level network management functions. This enables the EHC to configure its interface to the OS81060 when the application is ready OPTION: MOST INIC FLASH The selected MOST network interface controller is the single chip OS81050, belonging to the SMSC Intelligent Network Interface Controller (INIC) family. The OS81050 INIC is capable of more than 24 Mbit/s data throughput when interfacing to a MOST (Media Oriented Systems Transport) Network. All relevant network management functions are handled on-chip, providing a complete system interface to the physical-layer components. It is connected to the secondary microcontroller MPC5668G via the Media Local Bus (MediaLB) serial port. The MPC5668G control the INIC via I2C serial port. The Network port TX/RX connects the OS81050 to the Optical Tranceiver. Moreover, the streaming port is used to transmit a multiplexed digital signal, an I2S/TDM at 8 stereo channels, to the MOST Network. The bi-directional I2S/TDM channel connects the synchronous channel of Logic core with the external device connected to the MOST Network. The 44 pin package OS81050 device is available in the standard temperature range of -40 C to 85 C as well as in the extended temperature range of -40 C to 105 C, so there is enough flexibility to select the right version depending on the final requirement for the operating temperature range, measured inside the HU Box. The device is powered by a single 3V3 supply voltage; a command for the Reset is managed. A typical MOST Network node would consist of the physical-layer devices connected to the MOST Network, the OS81050 to handle the low-level protocols, and an External Host Controller (EHC) for the mid- to high-level functions. This configuration eliminates the need for the user to implement the lower levels of the MOST Specification protocol, thereby drastically shrinking development time. Network management functions are off-loaded from the programmer, allowing full concentration on the application being developed. Figure below illustrates the OS81050, with the matching protocol stack implementation. 69/145

70 Figure 57. OS81050 Protocol stack Package Parameters: Package type is (max) x mm, 44 ETQFP, Pitch (typ) 0.80 mm Module height (max) 1.20 mm Power Supply: Core (2.5 V); Peripheral (3.3 V) The Network Port can be configured as a network timing-master or timing-slave. As a timing-slave, the OS81050 internal timing is clocked from the recovered network clock. As a timing-master, the OS81050 internal timing and the network clock are determined by an external crystal. An internal PLL in the Clock Manager multiplies the external timing source for the generation of internal clocks. The receiver input pin (RX) is over-sampled by a high-frequency clock and data is recovered by a digital state machine. 70/145

71 The MediaLB Port is the primary interface between the EHC and the OS81050, and supports all types of data transport methods supported by the network. The Control Port is the second interface between the EHC and the OS81050, and supports message-based packet and control data. The Control Port also allows the EHC to enable and configure the MediaLB Port. The Streaming Port provides a gateway for high-speed streaming data between the OS81050 and external legacy devices such as ADCs, DACs, or co-processors. Some Streaming Port and MediaLB Port modes are mutually exclusive. After reset, the OS81050 automatically interacts with the network, performing all necessary low-level network management functions. This enables the EHC to configure its interface to the OS81050 when the application is ready OPTION: FOT (Optical Link Transceiver for MOST) The Optical link selected is the Tyco pigtail for MOST. It is composed by: The Fiber Optic Transmitter (FOX) together with the Fiber Optic Receiver (FOR); The Plastical Optical Fiber (POF); The pinheader. MM proposal is to use the Avago ODIN_MOT4_02 device as FOX device and Avago ODIN_MOR4_02 as FOR device. Both the devices are available in the extended temperature range of -40 C to 95 C. The figure below shows the Tyco pigtail for MOST. 71/145

72 Figure 58. FOT drawing The INIC Processor manages the transfer of data to and from the network. The Network Port connects the INICS Processor to the network using the TX and RX pins to transmit and receive network data to and from the FOX and FOR. Working in conjunction with the Clock Manager, the Network Port recovers the network clock, decodes received data, passes data to the INIC Processor, and encodes data for network. MM proposal is to connect the FOT to the MOST device as showed below. 72/145

73 DB FOT ENABLE FOT SPI I2STDM GND 3,3V stby AND uc MLB MOST OR FOX (Tx) POF MPC5668G 3 OS81060 (option OS81050) TX_DATA RX_DATA 3,3V stby FOR (Rx) POF GND FOT Status Figure 59. Most interface - Block Diagram In order to save power during the stand-by mode, MM proposal is to power-down the FOX device when there is not activity on the MOST network. To bring the FOX device back we have to monitor the FOT status signal on FOR device that is always power up. When there is some activity on the 73/145

74 POF RX side, the secondary microcontroller receives an interrupt and wakes up the FOX device through the FOT ENABLE signal. The OS81050 INIC provides the ability to attenuate network optical power, by controlling the optical power output of the FOX with FOT INIC PWR. The current consumption depends on the settings of Rext. The nominal value for Rext is 15 kω. With Rext = 30 kω the optical output power is about -3 db of the nominal value. Table FOX consumption Parameter Condition Max Unit Supply Current Rext = 15 kω, ON state, 35 ma biphase coded data Supply Current Rext = 15 kω, OFF state 20 ua The figure below shows the typical dependency of average optical output power (Popt) and Supply Current versus External Resistor. Figure 61. Average Optical Output Power versus External Resistor The maximum current consumption for the FOR device is 28.5 ma. When the FOR doesn t receive data from the POF (dark condition) the maximum current consumption is only 15 ua in sleeping condition mode. For more details, see also the table below: 74/145

75 Table FOR consumption Parameter Condition Max Unit Supply Current Full Power Mode 15 ma Supply Current Low Power Mode 10 ua In order to achieve a low current consumption there is a control system inside the FOR device that disable the transistors of the output stage when the optical receiver doesn t receive data from the POF. 75/145

76 4.12 OPTION: Gyroscope & accelerometer interface Most of the current MM navigation systems are not requiring any gyroscope for navigation; the information needed for the Dead Reckoning algorithm are achieved by gathering and processing the differential odometers messages received through the CAN network. This results in cost saving opportunity. So, on the Entry Nav offer, MM will insert, just as an option, the possibility to mount a gyroscope as a backup solution, in case of the Dead Reckoning algorithm won t work correctly Accelerometer and Gyroscope Introduction Gyroscopes measure the angular velocity of the system in the inertial reference frame. By using the original orientation of the system in the inertial reference frame as the initial condition and integrating the angular velocity, the system's current orientation is known at all times. Accelerometers measure the linear acceleration of the system in the inertial reference frame, but in directions that can only be measured relative to the moving system (since the accelerometers are fixed to the system and rotate with the system) OPTION: Accelerometer The LIS3LV02DQ is a three axes digital output linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an I2C serial interface. Figure 63. Accelerometer Block Diagram 76/145

77 Accelerometer is connected to host microprocessor via I2C: Figure 64. Accelerometer application circuit OPTION: Gyroscope Murata gyroscope MEV50A is used to provide angular rotation of the vehicle. The correlation between angular velocity and output analog voltage, is depicted in the graph below. Figure 65. Gyro characteristic 77/145

78 Figure 66. Gyro application circuit Analog output need A/D conversion in order to feed host controller: the connection is via SPI. To provide an appropriate accuracy, 12 bit A/D is adopted: TLV2544 The block diagram of the A/D 12bit TLV2544 is shown in the following picture: Figure 67. Gyro Block Diagram 4.13 OPTION: SD Card Holder The selected SD Card Holder is the Molex An hardware protection will limits the current in case of overload or short circuit: the threshold is 500mA. The selected automotive SD card interface protector is the Maxim ATO /145

79 Figure 68. CAD model of the SD Card Holder Main features of the ATO314: Current limited/protected Power FET 500mA 5V or 3.3V operation for SDCARD Power Integrated 3.3V / 1.8V SDIO switchable LDO Integrated Diagnostic with Fault Output 8 5ohm Line Protection FETs 8 Channel +-15kV ESD (Air)(8kV Contact ESD Array The Block diagram in the next figure gives an overview of the ATO314 Module. 79/145

80 Figure 69. SD Card Protector ATO314 Functional Block Diagram 80/145

81 4.14 LAN Filter In order to connect the PHY-Ethernet to the Fakra Radio Connector, we use one LAN filter. MM proposal is to use the LFE8505T manufactured by Delta. The figure below shows the LFE8505T circuit. Figure 70. LAN Filter device schematics. The 16 pin package LFE8505T device, compliant with IEEE802.3 standard, is available in the automotive temperature range -40 C +85 C. The figure below shows the mechanical dimension: 81/145

82 Figure 71. LAN Filter physical drawings MM proposal for the hardware design is showed below: Figure 72. LAN Filter electrical schematics. 82/145

83 4.15 USB 2.0 interfaces The Logic Core Board can provide up to 3 USB 2.0 port including the physical layer integrated. The two USB ports will be routed on the external connector using two dedicated USB transceiver MAX16943, or equivalent. The USB3 port shall only be able to assure USB communication with NAD module. The figure below provides an overview of the USB communication. MB NAD MAX16943E USB3 USB1 MAX16943E USB2 MAX16943E Figure 73. USB interfaces - Block Diagram The MAX16943E provides high ESD and short circuit protections for the low voltage internal USB data and USB power line. The MAX16943E supports both USB High Speed (480Mbit) and USB Full Speed (12Mbit) operation. The short circuit protection features include short to battery on the protected HVBUS, HVD+, and HVD- outputs as well as short to HVBUS on the protected HVD+ and HVD- outputs. The MAX16943E is capable of short to battery condition of up to +18V. Short to GND protection and Over Current protection are also provided on the protected HVBUS output to protect the internal BUS power rail from over current faults. The MAX16943E features High ESD protection to ±15kV Air Gap and ±8kV Contact on all protected HVBUS, HVD+, and HVD-. 83/145

84 Figure 74. Conceptual application of MAX16943 Protection circuit provide low Ron(0.14 Ohm) and up to 1.2A of max current. The USB protector is able to drive at least 800 ma. Fault signal is also provided to host in case of: - short-circuit - power fails - power supply overcurrent The pinout on USB connector will be compliant to following BMW specification (refer to section external connector). 84/145

85 4.16 CVBS - Input Architecture The concept of the proposed solution for the CVBS video signals interface is depicted in the following figure. 2x CVBS Differentail to single ended circutry VIDEO IN (SAF7115) CCIR 656 I2C LOGIC CORE Figure 75. CVBS Input Interface Architecture and conceptual data flow The basis version of the CVBS-Input Architecture will use one SAF7115 video input decoder that are able to manage up to 6 different single ended CVBS input signals with future variant to cover up to 6 video input signals or 3 S-Video input signals. In the actual proposal, the SAF7115 Video Input Decoder, handles 2 single ended video signals. In order to deal with an input channel that can be single-ended or differential, a standard single-ended to differential conversion will be implemented; this is based on NJM25005 IC OpAmp, specifically designed for video bandwidth; the input interface is represented in the next figure. Vin+ R1 C1 NJM2505F Vout Vin- Rd R1 C1 + - Co GND Figure 76. CVBS differential Input Interface conceptual schematic 85/145

86 Video Input Decoder The NXP SAF7115 is a video decoder capture device suitable for in-car entertainment. This decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU-601 compatible color component values. The SAF7115 accepts CVBS from TV or VCR sources as analog inputs, including weak and distorted signals. Automatic detection of (50/60 Hz) of the input source: PAL N/M NTSC M NTSC-Japan NTSC 4.43 SECAM SAF7115 perform horizontal and vertical down-scaling and up-scaling with 6-bit anti-aliasing filter to randomly sized windows and zoom function. It can accept up to six CVBS input signals or in alternative 2 CVBS differential input signals. The device will powered with the 3,3V rail, requiring a current of 190mA (max); it is available in the HTQFP100 ( HW version, Rj-a=35 C/W ) or TFBGA160 (ET version, Rj-a =23 C/W ); the max power dissipation is 900mW and the operating ambient temperature is from -40 to +85 C. The block diagram is shown below: BUFFER AND SCALER Figure 77. Video Input Decoder SAF7115 Functional Block Diagram 86/145

87 Figure 78. Video Processor schematics example Annex: Example of CVBS PAL signal The SAF7115 device can accept CVBS input video signal PAL/NTCS/SECAM. The following example describes how will be treated CVBS PAL signal in order to be displayed, assuming the requirements listed in the following table: Table CVBS PAL Specifications PAL Lines for one frame 625 Active line for each semi-frame (288) Vertical synchronism Horizontal synchronism 50 Hz 15625±0.0001% Hz Line period 64 µs Blanking interval 12±0.3 µs 87/145

88 Every picture (frame) of the PAL consists of two semi-square (semi-frame), which is made up of lines. Only 288 lines are active, which contain data to be displayed. The rest consists of blanking lines. Each frame consists of 576 active lines. In the semi-frame odd active lines ranging from 23 to 310, while in the semi-frame, active lines ranging from 336 to 623. Moreover in standard video PAL, only the second half of the first line of frame (line 23) is active and only the first half of the last line of active frame (line 623) is active. Consequently, the lines really active in a frame are 575. A diagram of the frame PAL, is depicted here: FRAME 625 linee 288 linee 288 linee odd semi-frame even semi-frame Figure 80. PAL frame - Diagram The displays adopted will require a scaling in order to fit CVBS signal. First of all is necessary to digitalize analog video signal. This task is in charge to a video decoder. PAL signal will be digitalized in this way: Table Digital PAL Specifications PAL Samples for each line 720 Frame lines 625 Active line for each semi-frame (288) Vertical frequency Horizontal frequency Pixel clock 50 Hz Hz 13.5 MHz As can be seen from the table, there are differences in terms of pixels per line and number of total lines: 88/145

89 Table Digital PAL vs CID Specifications Digital PAL Display pixel Samples per line / /560 less Active lines/frame linee more So, the signal must be scaled in order to fit into the display size. PAL 48 lines WVGA 40 pixels 40 pixels Figure 83. PAL vs WVGA - Comparison Reference [1] BMW DOC 404 [2] SAF7115 Multi-standard video decoder with super-adaptive comb filter, scaler and VBI data readback via I2C-bus, Product Specification, Rev October [3] NJM2505A, SINGLE ISOLATION AMPLIFIER, JRC data sheet, ver.4 89/145

90 4.17 LVDS outputs Architecture The proposed HU LVDS architecture, shown in the following figure, allows the HU to drive popular automotive displays with video resolutions up to 1600x600 pixels, 24 bit colour depth and refresh rates of up to 100Hz. Logic core RGB (24 bit) SPI APIX2 1 pair 1 pair C O N N E C T O R Figure 84. LVDS Display Outputs Interface The parallel RGB bus is serialized by a INOVA APIX2 INAP375T device and transmitted to the CID display. APIX2 transmitter include one SPI serial line to send and receive information data to and from the external display. The next section reports on the operation of INAP375T LVDS Transmitter LVDS INOVA APIX2 Transmitters The HU-CID LVDS interface will be provided by the INOVA APIX2 INAP375 device. The INOVA APIX2 INAP375 component converts the parallel video data format into an high speed serial data video stream transmitted across one differential signal pair. The Control Data of the CID are transmitted across the two differential signal pairs present on the 4 wires connector. The connector used is described on the connector chapter and agreed with BMW. 24 bits of color depth: Bandwidth: Downstream Sampling Frequency: Up to 3 Gbps 30 MHz 90/145

91 Figure 85. LVDS Conceptual Block Diagram Together with the LVDS transmission, the APIX2 device is able to perform a bi-directional control data transmission. The downstream control data to CID is merged together the video download stream on the first differential pair, meanwhile the upstream control data is transmitted on a different differential pair. The use of a separated and dedicated channel for the upstream control data from CID agrees with recommendation of Inova in order to reduce EMI effect in automotive solution Pixel Channel Interface Up to 24 bit of parallel pixel data representing the pixel RGB values is received via the pixel interface. The parallel pixel interface supports pixel formats of 10, 12, 18 and 24 bit + 3 control signals. Pixel data and control signals are combined with the pixel interface clock Downstream and upstream control data to CID via SPI The Downstream Channel of control data is merged into the downstream Pixel Channel and contains the data sampled asynchronously on the SBDOWN_DATA pin at the internally generated sampling frequency. The sampling frequency at the considered bandwidth (3 Gbps) takes value 30 MHz. The maximum data rate settable on the upstream interface is 9 Mbit/sec. The downstream control data and related clock are decoded from the data downstream by the APIX2 receiver device on the receiver display (CID). Control data transmission to the display and vice versa is allowed by an SPI connection between the secondary uprocessor and the APIX2 transmitter (cfr. DOC404). 91/145

92 HEAD UNIT DOWNLOAD LINK CID uprocessor SPI Master INAP375T AShell UPLOAD LINK INAP375R Ashell SPI Slave Figure 86. LVDS Download data to CID Power supply for display The power supply for the CID will be provided using the power pins 5 (+8V) and 6 (GND) present on the Rosenberger HSD Hybrid connector 99S20D-40MA5-Y. 92/145

93 4.18 Audio Input interface Microphones For reference, the following table summarize the main BMW specification for the microphone. Ref. Ref : [DOC404_185] Input current: 5.5mA +/- 1mA Sensitivity: E/1000 Hz: 75mV +/-3dB / 74 db E/ 300 Hz: -8.5dB to -2.0dB based on 1000Hz E/3000 Hz: -1.2dB to +6.6dB based on 1000Hz Additionally each physical microphone input that the Head Unit provides must conform to the following specification (new type of microphones): Note: Magneti Marelli will provide a microphones power supply at 8V as agreed with BMW Following a figure on the microphones input interface that will be provided. 93/145

94 51Ω 8V 180Ω 180Ω 51Ω 100µF Mic in N Mic in P Parrot module Figure 87. Microphones input conceptual schematics Auxiliary Audio stereo Input Aux_IN and mono input Tel_IN The HU will equipped with one auxiliary analog interfaces, AUX_IN for stereo inputs, and one mono input signal for telephone audio input, Tel_IN. Standard interface, fully protected against short circuit to ground and battery voltage will be provided. Auxiliary stereo input signals and telephone audio signal will be connected to and processed by the NXP Radio Processor device SAF7741 (for further details about audio approach, please refer to the dedicated section Radio DSP) Tel Mute A standard interface circuit will be used for the interface of the on-off switching signal Tel_Mute. The signal will be connected and managed by the uc of the Main Board Radio & DSP 94/145

95 Introduction This section contains technical specification and operating information for the integrated radio block, developed for new MM telematic generation. Radio block is a basic modular function with one or two embedded AM/FM tuners (depending on options), one RDS data tuner for TMC functionalities, audio processing capability and interfaces with a digital SDARS and DAB radios Radio function overview The basic radio function mainly consists of: Audio-Radio digital signal processor based on NXP SAF7741; Double AM/FM tuners with phase diversity based on IF sampling concept; RDS tuner module for continuous RDS data acquisition and TMC management; One or two Fakra antenna connectors and RF front-end; Antennas phantom power with protections and diagnosis; Interfaces with a digital radio board. The radio block is a slave peripheral and is controlled on I2C bus by the main CPU hosted in the Logic Core board. The Radio SW is running on the Main CPU that has in charge the following main features: Power supply management, audio mute/de-mute and volume regulation Manual tuning Automatic tuning (seek) Complete RDS management: TMC and PTY, PI, PS name, Alternative Frequency, TA, TP, EON. PI Seek FM and AM band management Autostore Station list Basic Audio features like balance, bass, treble, loudness and fader Equalizer, source mixing, source switching and AVC Audio setting 95/145

96 Base RADIO MODULE Double World Wide AM FM Tuner Phase diversity IF Sampling Radio DSP - RDS Tuner Audio DSP Phantom_Power With I2C Diagnosis AM2 FM2 SUB ANTENNA INPUT AM1 FM1 MAIN ANTENNA INPUT Phantom_Power With I2C Diagnosis SUB_TUNER AM2 FM2 RDS2 MAIN_TUNER AM1 FM1 RDS1 I2C Reset RDS DATA TUNER DRM_I-Q HD_I-Q I2C 4 x I2S_in IF_input2 IF_input1 ADC1 ADC2 Audio Radio DSP ADC3 ADC4 Audio Mux Analog_in1 Analog_in2 Analog_in3 Analog_in4 4 x I2S_out DAC_OUT Six Channels Analog_Audio_out to power module July. 16th, 2008 rev. 1.0 Figure Base radio function schematic diagram Tuner owerview The radio function may be provided with three tuners named: Main_Tuner, Sub_Tuner and RDS_Data_Tuner. Main_Tuner and Sub_Tuner are based on two NXP SAF7700 tuner ICs plus one SAF7741 DSP, designed to implement a double tuner based on the IF sampling concept to manage AM, FM and RDS. Each tuner is suitable for analog Frequency-Modulated/Amplitude-Modulated and Weatherband (FM/AM/WX) radio reception as well as reception of encoded digital signals such as HD Radio. HD Radio signals are fed on a dedicated I-Q digital bus to be decoded inside the digital radio module (optional). The third tuner is based on the Si4762 Silicon Labs chip (base offer) that s designed for RDS data decoding and for quality analysis on FM signal level. Optionally will be replaced by: 1. the Si4761 chip, if HD Radio decoder is present; 2. the Si4760 chip, if the VICS decoder is present. The radio module is provided with two antenna Fakra connectors: the Main_Tuner is connected on an A type Fakra connector, the Sub_Tuner is connected on a B type Fakra connector. The RDS data tuner is connected on the A type Fakra connector, through the Main_Tuner. The RF front end is compatible with 50 ohm active antennas and is able to deliver an independent switched phantom power supply to both antennas. Activation or deactivation of each phantom power supply is managed by up. Phantom powers are short circuit protected and are under diagnosis (short circuit, normal load and open circuit). The thresholds can be set by software. 96/145

97 Antenna connectors Radio module is provided with following connectors: Name Type Description AM1 FM1 FAKRA Code A male connector Connection to the antenna AM/FM1 AM2 - FM2 FAKRA Code B male connector Connection to the antenna AM2/FM2 97/145

98 The following bands are available on both Main_Tuner and Sub_Tuner: Frequency Band Country Frequency Range Min Max Unit FM Europe MHz AM LW Europe KHz AM MW Europe KHz AM SW Europe KHz FM USA MHz AM USA KHz FM Japan MHz AM Japan KHz WX USA MHz 98/145

99 Main_Tuner and Sub_Tuner can be configured according to the following radio modes: Mode name Main tuner Sub tuner Application remark AM AM - Single antenna FM FM - Single antenna WX WX - Single antenna FM SAD FM SAD Double antenna FM PhaseDiversity FM PhaseDiversity FM PhaseDiversity Double antenna AM / RBS AM RBS Single antenna FM / RBS FM RBS Single antenna FM SAD / RBS FM SAD RBS Double antenna FM / AM FM AM Same as Radio mode FM, but with the following extra processing: Sub path AM level detector, Sub path AM offset detector, Sub path AM Adjacent detector, Sub path AM mono audio demodulation, Audio correlator off. AM / AM AM AM Same as Radio mode AM, but with the following extra processing: Sub path AM level detector, Sub path AM offset detector, Sub path AM Adjacent detector, Sub path AM mono audio demodulation, Audio correlator off. AM / AM DTAC AM AM Same as Radio mode AM, but with the following extra processing: Sub path AM level detector, Sub path AM offset detector, Sub path AM Adjacent detector, Sub path AM mono audio demodulation, Audio correlator on. WX / AM WX AM Same as Radio mode WX, but with the following extra processing: Sub path AM level detector, Sub path AM offset detector, Sub path AM Adjacent detector, Sub path AM mono audio demodulation, Audio correlator off. FM / RBS+ FM RBS+ [1] Same as Radio mode FM/RBS, but with the following extra processing: Sub path FM mono audio demodulation, Audio correlator off. AM / RBS+ AM RBS+ [1] Same as Radio mode AM/RBS, but with the following extra processing: Sub path FM mono audio demodulation, Audio correlator off. FM / RBS+ DTAC FM RBS+ [1] Same as Radio mode FM/RBS, but with the following extra processing: Sub path FM mono audio demodulation, Audio correlator on. [1] With RBS+ the normal RDS system is meant plus mono audio generation. 99/145

100 DSP The DSP SAF7741HV is a combined Intermediate-Frequency (IF) car radio and audio Digital Signal Processor with several powerful cores integrated onto a single device. It combines analog IF input, digital radio and audio processing, sample-rate converters and digital and analog audio outputs to enhance listening clarity and noise suppression while reducing multipath channel effect. It is equipped to work with the TEF7000 integrated tuners for analog and digital AM/FM decoding and sound processing. The SAF7741HV consists of two main processing blocks; one for radio and the other for audio. These blocks demodulate the low-if tuner output, delivering digital audio to internal Digital-to-Analog Converters (DACs). In addition to the main blocks there are a number of interfaces and dedicated subcircuits Radio Processing The IF radio block interfaces to the front-end tuner chips and supports either a so-called low-if frequency (of 60 khz or 300 khz). Two tuner interfaces are supported, each of which is suitable for analog Frequency-Modulated/Amplitude-Modulated and Weatherband (FM/AM/WX) radio reception as well as reception of encoded digital signals such as HD Radio. Signals received from the tuner front-end chips are digitized with integrated Intermediate-Frequency Analog-to-Digital Converters. The resulting digital signals are then down-sampled, error corrected and filtered in the digital domain to be suitable for further radio and audio processing by the DSPs. The SAF7741HV radio section incorporates the following features: Two IFADCs to digitize the incoming analog IF signals from the tuner(s) Two Primary Decimation Chains (PDCs) for analog and digital radio reception, including digital mixing to Zero IF (ZIF) Software-based radio functionality running on one or more DSPs depending on the features set and dual or single tuner usage The IFADC digitizes the incoming Near-Zero Intermediate Frequency (NZIF) signals. The IFADC is a baseband Σ ADC. The software radio consists of three Tuner DSPs: TDSP1, TDSP2 and TDSP1E. All three TDSPs have a basically identical structure, but TDSP1 and TDSP2 are extended with: A Finite Impulse Response (FIR) filter CORDIC (COordinate Rotation DIgital Calculation) Rotate and De-rotate (CRD) TDSP1E is extended with a CRD only. Each FIR (controlled by the TDSP) is used for variable bandwidth control and for the Polar-to-Rectangular (P->R), Rectangular-to-Polar (R->P) and DIV conversions that will be used for demodulation. Added to this block is a 2LOG(LD(x)) function. In addition, a RDS decoder is included for each tuner channel Audio Processing The audio processing block receives either external digital signals, or analog signals which are then digitized by the integrated ADCs. Together with the internal radio audio signals these inputs are available for further audio processing such as equalization, tone control and volume control. The output signals of the audio processing block are provided in digital format on the Host IIS outputs and in analog format on the DAC outputs. 100/145

101 Software Features The following software features are available for the SAF7741HV: Improved FM weak-signal processing Integrated 19 khz Multiplexed (MPX) filter and de-emphasis Electronic adjustment of FM/AM level and FM channel separation Variable IF bandwidth. Selective IF bandwidth for wideband FM, FM Weatherband and AM Variable IF bandwidth on FM, dependent on the adjacent channel interference Digital stereo decoder for FM and AM Advanced digital Interference Absorption Circuit (IAC) for FM and AM Digital Automatic Frequency Control (AFC) RDS demodulation Pause detection for RDS updates with audio mute during RDS updates Baseband audio processing (treble, bass, balance, fader and volume) Maximum of five audio SRCs Dynamic loudness or bass boost Audio level meter Compact Disc (CD) dynamics compressor/expander Improved AM processing with soft mute, high cut control Soft audio mute Extended chime functions Signal level, noise and multi-path detection for AM/FM signal quality information AM audio AGC AGC click suppression in AM mode 101/145

102 Audio Functions Three audio channels are managed in parallel : 1. Main channel with output on the main loudspeakers (stereo on front and rear) and on I2S for echo cancelation (stereo of front or rear). The inputs are : Tuner, Blackfin with DAB or FM synchronized, CD, Auxiliary1, Auxiliary2, Bluetooth, TTS, Beep generator. 2. Microphone in channel On or Off, gain control, filter. 3. Microphone out channel on or off, gain control. The audio outputs are : Front and Rear analog stereo, I2S for echo cancellation, I2S FM for Blackfin, I2S Rear seat microphone in, The audio features of each channel are : 1. Main channel : volume, mute, bass/treble, fader/balance, loudness, preset equalizer, auto volume control, TTS mixing, beep generator (single beep & cyclic beep), hifi modes. 2. Microphone in channel : On or Off, Gain control, Filter. 3. Microphone out channel : 102/145

103 On or Off, Gain control The main channel can be connected to the following audio entries : Tuner, Blackfin CD/MP3/Mic out Auxiliary1 Mic in Auxiliary2 Analog inputs (Aux1, Aux2, Mic in) can not be played at the same time. Here is summarized the general audio architecture: Figure 1 Audio architecture 103/145

104 TTS (dig) 1/4 Volume DAB/FM sync. (dig) BT_in (dig) 6 5 4/2 I2S_EC (dig) Tuner CD/MP3 (dig) CDC (ana) sw1 Volume Loudness Equalizer Mute Balance 2/4 Fader Bass Treble AVC Quad DAC Main channel Two stereo outputs (ana) Auxiliary (ana) 4 Beeps 1/4 Volume FM signal (dig) Micro_in (ana) ADC Gain Pass-band filter Micro_in (dig) Figure 2 General Audio architecture Analog Audio outputs Radio Processor can have six or four differential outputs. Audio outputs are connected to the audio power amplifier block Power supply for Radio section The Main power supply delivers 5.0V and 3.3V supply voltage; a locally supply of 1,8V, close to DSP and Radio part, will be implemented. The switched supply voltage 3V3 will turn OFF during standby, in order to reduce overall consumption in low power mode. Item Parameter Min. Typ. Max. Unit Conditions P5V0 Tuner operating supply voltage P5V0 analog/digital V Iccp5v0 Supply current P5V0 tbd 110 tbd ma FM mode, single tuner configuration Iccp5v0 Supply current P5V0 tbd 220 tbd ma AM mode, single tuner configuration P3V3 DSP operating supply V voltage 3V3 for analog/digital Iccp3v3 Supply current P3V3 tbd 370 tbd ma P1V8 DSP digital core operating supply voltage 1V V As P1V8 is generated from P3V3, Iccp1v8 current value is already computed in Iccp3v3 current value Antenna interface for Phantom power supply Antenna input («AM1 + FM1» & «AM2 + FM2» ) delivers phantom power supply according following limits : Items Limits Min. Typ. Max. Test conditions 104/145

105 Phantom Power supply (V) tbd tbd tbd Consumption (ma) tbd tbd An hardware protection will limits the current in case of overload or short circuit: the threshold is normally 140mA, different value could be implemented on request. A circuit for a SW diagnosis that detect overload and short circuit will be implemented. In case of short circuit, maximum delivered current by Radio circuits is limited during few second, after phantom power is switched OFF. 105/145

106 Auxiliary1 audio input It is an analogue differential or half-differential input Signal Flow Type Description AUX1_R Input right Analogue - Differential or Half-differential AUX1_L Input left - Max input : tbd AUX1_REF Input reference - Input impedance > 10KΩ - THD+N < -76dB - Capability with a DC voltage of 16V +/-10% - Frequency response 20Hz 20KHz (roll off at -3dB, fs=44.1khz) - S/N > 85dBA - Channel separation > 65dB at 1KHz, 0.5 Vrms, input ac grounded Note that the Radio DSP can provide a second auxiliary input channel (AUX2), with the same characteristic as AUX1_IN. This second input it is not used for the Entry HU, and will not be interfaced FM Receivers electrical characteriztion FM radio reception criteria In order to make a parallel with real-life situations, a distinction is made between three main criteria for characterisation of the radio receiver: receiver behaviour in weak field receiver behaviour in strong field behaviour in disturbed environment Receiver behaviour in weak field Sensitivity limited by the noise This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Tested frequencies are 89MHz, 98MHz and 107MHz. Parameter Test Conditions Min Typ Max Unit Sensitivity RF level for S/N=26dB 0-4 dbµv Signal to noise ratio This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Tested frequencies are 89MHz, 98MHz and 107MHz. Parameter Test Conditions Min Typ Max Unit S/N, Stereo RF input level = 0 dbµv RF input level = 5 dbµv RF input level = 15 dbµv RF input level = 40 dbµv db db db db 106/145

107 Sensitivity to frequency deviation This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Parameter Test Conditions Min Typ Max Unit Deviation audio output level of 3dBV 6 KHz Level of limitation at -3 db This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Parameter Test Conditions Min Typ Max Unit RF level Er audio output level of 3dBV 34 dbµv Total harmonic distortion as a function of the input level This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Measurement is made in stereo with left = right. Parameter Test Conditions Min Typ Max Unit THD 12dBµV< Er <60dBµV % Selectivity and rejection of the adjacent channel This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 2. Image frequency rejection 107/145

108 This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Test is performed at 89MHz. Measurement is made in stereo with left = right. Parameter Test Conditions Min Typ Max Unit Rejection 60 db 108/145

109 Rejection of RF intermodulation products This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 3. Measurement is made in stereo with left = right. Parameter Test Conditions Min Typ Max Unit Rejection Generator 1: Frequency = 98MHz Generator 2: Frequency = 98.4MHz Generator 3: Frequency = 98.8 MHz 76 db Sensitivity limited by gain This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Parameter Test Conditions Min Typ Max Unit RF level Er audio output level of 3dBV -5 dbµv Capture ratio This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 2. Measurement is made in stereo with left = right. 109/145

110 Intermediate frequency rejection The test is performed with the single signal method using a modulated signal. Measurement is made in stereo with left = right. This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Parameter Test Conditions Min Typ Max Unit Rejection RF level at -3dB limitation 82 db point Elimination of amplitude modulation The test is performed using the sequential method. This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Parameter Test Conditions Min Typ Max Unit Rejection RF level at -3dB limitation 60 db point Distortion versus frequency deviation This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Measurement is made in stereo with left = right. During measurement volume level is not changed. Parameter Test Conditions Min Typ Max Unit THD 20KHz< Deviation <75KHz 0.1 % Total harmonic distortion as a function of the tuning modification frequency This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Measurement is made in stereo with left = right. During measurement volume level is not changed. Parameter Test Conditions Min Typ Max Unit THD -30 KHz < RF Frequency Shift<30KHz 0.1 % Step 5 KHz Crosstalk attenuation This measurement is performed in the nominal test condition defined on annex1 with the set-up describe on figure 1. Parameter Test Conditions Min Typ Max Unit Crosstalk Rejection Reference audio output 38 db level of 3dBV Stereo identically factor This measurement is performed in the nominal test condition defined on annex1 with the set-up describe on figure /145

111 Parameter Test Conditions Min Typ Max Unit Stereo identically factor 0.1 db Audio frequency response This measurement is performed in the nominal test condition defined on annex1 with the setup described on figure 1. Pre-emphasis is OFF. The frequency response is a sweep from 20 Hz to 15 khz. Reference (0dB) is at 1kHz and 3dBV on output. Amplification reserve This measurement is performed in the nominal test condition defined on annex1 with the setup described on figure 1. Parameter Test Conditions Min Typ Max Unit Amplification 4 db reserve Rejection of audio intermodulation products This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Parameter Test Conditions Min Typ Max Unit IM3 Audio signal F1=1KHz 45 db Audio signal F2=1.1KHz 111/145

112 AM Receivers electrical characteriztion AM radio reception criteria In order to make a parallel with real-life situations, a distinction is made between three main criteria for characterisation of radio reception: receiver behaviour in weak field receiver behaviour in strong field behaviour in disturbed environment Receiver behaviour in weak field Signal-to-noise ratio This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. MW: Parameter Test Conditions Min Typ Max Unit S/N, Stereo RF input level = 22 dbµv RF input level = 35 dbµv RF input level = 50 dbµv db db db LW: Parameter Test Conditions Min Typ Max Unit S/N, Stereo RF input level = 21 dbµv RF input level = 40 dbµv RF input level = 55 dbµv db db db Sensitivity limited by the noise This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. MW: Parameter Test Conditions Min Typ Max Unit Sensitivity RF level for S/N=26dB 19 dbµv LW: Parameter Test Conditions Min Typ Max Unit Sensitivity RF level for S/N=26dB 21 dbµv 112/145

113 AGC - Merit factor This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. Parameter Test Conditions Min Typ Max Unit Merit Factor 47 db Receiver behaviour in strong field Total harmonic distortion as a function of the input level This measurement is performed in the nominal test condition defined on annex1 with the setup described on figure 4. Parameter Test Conditions Min Typ Max Unit THD 20dBµV< Er <60dBµV 1 % Behaviour in disturbed environment Single signal selectivity This test is made with the setup described on figure /145

114 Rejection of RF intermodulation products This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 6. Parameter Test Conditions Min Typ Max Unit Rejection Generator 1: Frequency = 216KHz Generator 2: Frequency = 103.5KHz Generator 3: Frequency = 112.5KHz 47 db Generator 1: Frequency = 1053KHz Generator 2: Frequency = 522KHz Generator 3: Frequency = 531KHz 56 Sensitivity limited by gain This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. Parameter Test Conditions Min Typ Max Unit RF level Er audio output level of 3dBV 12 dbµv Intermediate frequency rejection This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. Parameter Test Conditions Min Typ Max Unit Rejection Audio output level at -3dB Intermediate 90 db Interfering signal rejection This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. Parameter Test Conditions Min Typ Max Unit Rejection Audio output level at -3dB Fd=216KHz, IF=11.132MHz Fd=1053KHz, 90 db Audio response in AM receiver mode The audio filter response This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. Parameter Test Conditions Min Typ Max Unit Attenuation@40Hz Audio output 1KHz 4 db Attenuation@4KHz Audio output 1KHz 15 db 114/145

115 Amplification reserve This measurement is performed in the nominal test condition defined on annex1 with the setup described on figure 4. Parameter Test Conditions Min Typ Max Unit Amplification 3 db reserve Distortion versus audio frequency This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 12. The distortion is recorded while causing frequency variations from 40Hz to During measurement volume level is not changed. 115/145

116 Distorsion versus modulation factor This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure Rejection of audio intermodulation products This measurement is performed in the nominal test condition defined on annex1 with the set-up described on figure 4. Audio spectrum in the band 0-4 khz is displayed. Parameter Test Conditions Min Typ Max Unit IM3 Audio signal F1=1KHz 70 db Audio signal F2=1.1KHz 116/145

117 RDS Test RDS tests are based on standard CEI These measurements are performed in the nominal test condition defined on annex1 with the set-up described on figure 1. Parameter Test Conditions Min Typ Max Unit Detect PS in less than 17 dbµv RDS sensitivity 10 seconds RDS deviation sensitivity 0.2 KHz Maximum RDS deviation 10 KHz 117/145

118 Annex1 Radio Test Description Characterisation method The method for characterisation of tuners is based on the following standards: IEC : Test methods IEC : AM characterisation IEC : FM characterisation IEC : RDS characterisation The specification for the FM/AM receiver is based on the parameters having most impact on the quality of the audio electrical signal: signal-to-noise ratio total harmonic distortion (THD) audio output audio frequency response For all tests without a specifics measurement setting, measurement condition is described on paragraphs below. Standard measuring conditions All measured values are RMS Ambient temperature 25 C±3 C Audio output unit is dbv (0dBV = 1VRms) Output impedance of RF generator is 50Ω RF level unit is dbµv Er value corresponds to the HF level in the tuner input (level on generator is adjusted considering lost on dummy load) FM settings Stereo modulation with 75 khz excursion (L+R deviation = 88%, pilot deviation = 8.4%, RDS deviation = 1,6%) Unweighted filter 22 Hz - 22 khz. Generation of audio signal on left-hand channel only Audio signal at 1kHz without pre-emphasis Measurements taken at centre frequency 98 MHz (if not differently specified) Ref audio output voltage : 3dBV with a load of 4ohms +/-5% on Power IC outputs HF level injected at tuner input Er = 57dBµV RDS data available AM settings Audio signal at 1 khz Modulation factor 30% Unweighted filter 22 Hz - 22 khz Measurements taken at 216 khz and 1053kHz (if not differently specified) Ref audio output voltage : 3dBV with a load of 4ohms +/-5% on Power IC outputs HF level injected at tuner input Er = 57dBµV RDS settings Stereo modulation with 75 khz excursion (L+R deviation = 88%, pilot deviation = 8.4%, RDS deviation = 1,6%) Phase relation to the third harmonic of the pilot tone : 0 +/-1 118/145

119 Repetition rate for RDS group type 0A : Approximately 4/s Generation of audio signal on left-hand channel only Audio signal at 1kHz without pre-emphasis Measurements taken at centre frequency 98, 89 and 107MHz Ref audio output voltage : 3dBV with a load of 4ohms +/-5% on Power IC outputs HF level injected at tuner input Er = 57dBµV - Audio settings Barring special test conditions, the balance, fader, bass and treble settings are set to 0 and the loudness control is deactivated. - General set-up Radio module configuration Radio module FR + Power IC 4Ω FR FL + RL - 4Ω Figure 3 Radio module configuration Phantom power supply on antennas 1 and 2 is activated Standard mode Radio module outputs are connected to a power IC with characteristics close of the TDA7575 in 26dB mode. Power IC outputs are loaded with 4ohms +/-5% Vbat = 13.5V+/-0.1V, P3V3 = 3.3V +/-0.1V, P5V_SBY = 5V+/-0.1V, 91V = 9,1V +/-0.2V In FM with double antenna configuration, phase diversity is activated by the host module Measurements made on front left loudspeaker output 119/145

120 - Set-up with single generator in FM band RF generator Splitter FM antenna substitution network AM/FM1 RadioModule FM antenna substitution network FM2 Figure 4 Single source set-up in FM -Set-up with 2 generators in FM band RF generator 1 RF generator 2 Splitter Splitter FM antenna substitution network Antenna substitution network AM/FM1 FM2 RadioModule - Set-up with 3 generators in FM band Figure 5 - Two sources set-up in FM band RF generator 1 Splitter Splitter FM antenna substitution network Antenna substitution network AM/FM1 FM2 RadioModule RF generator 2 Splitter RF generator 3 Figure 6 - Three sources set-up in FM band Ref splitter: Mini circuits ZSC2 1 Lost on splitter is 3dB - Set-up with single generator in AM band 120/145

121 RF generator AM antenna substitution network AM/FM1 RadioModule FM antenna substitution network FM2 50Ω Figure 4 single source set-up in AM band - Set-up with 2 generators in AM RF generator 1 RF generator 2 Splitter AM antenna substitution network (fig 8) AM/FM1 RadioModule FM antenna substitution network (fig 7) FM2 50Ω Figure 5 Two sources set-up in AM band RF generator 1 Splitter AM antenna substitution network (fig 8) AM/FM1 RadioModule RF generator 2 RF generator 3 Splitter 50Ω FM antenna substitution network (fig 7) FM2 - Set-up with 3 generators in AM Figure 6 Three sources set-up in AM band 121/145

122 - Set-up with single antenna configuration FM band RF generator FM antenna substitution network (fig 1) AM/FM1 RadioModule FM2 FM2 input is not connected. Figure 7 Single antenna configuration 122/145

123 4.20 Audio Amplifier For the 4 channels audio power, MM propose the use the High efficiency class SB Audio Amplifier STM TDA7569 family devices by STM. This devices or similar of the same family have been used on different application with good results due to the specific IC design for car audio application. The TDA7569 is a 4 channels, H bridge power amplifier capable to deliver a power of 28W for each channel loaded with 4Ω, at Supply voltage of 14,4V and 10% of THD. The requested output power of 36W/Ω 4 at 13,8V, and 10% of THD, is achieved at supply voltage of 16V. However, the TDA7569 can deliver 15W at 1% TDH on the same load of 4Ω, at the typical system supply voltage of 12V (see figure below). The device integrate protection circuits and diagnosis circuits that allow to communicate the status of each speaker via an I2C bus serial port. The device can operate at supply voltage 6V Vbatt 18V, the absolute maximum supply being limited at 28V (continuous) and 50V (50ms). Main features of the High efficiency class SB amplifier TDA7569 include: High output power capability 14.4V, 1kHz, 10% THD, 4x50W max power Max. output power 4x72W/2Ω Full I2C bus driving: St-by Independent front/rear soft play/mute Selectable gain 26dB /12dB (for low noise line output function) High efficiency enable/disable I2C bus digital diagnostics (including DC and AC load detection) Full fault protection DC offset detection Four independent short circuit protection Clipping detector pin with selectable threshold (2%/10%) St-by/mute pin Linear thermal shutdown with multiple thermal warning ESD protection Power dissipation is internally limited by thermal warning (155 C of junction temperature Tj) and thermal protection circuit (170 C of junction temperature Tj). The device is powered from the main supply rail KL30 (or KL30_B) and a circuit for reverse battery protection will be provided. The device will be disconnected by the main supply rail during standby mode to reduce sleep current and for Vbat >16 V to protect the amplifier against over-voltages. The maximum output peak current is limited at 6A (1kHz, repetitive). The design target is to use the PSO36 package with slug-up assuring a thermal resistance junction-to-case of 1 C/W. The device will be implemented in the power board with the slug-up connected to the metallic thermal dissipator to ensure the proper thermal dissipation. Moreover the air forced by the internal FAN will ensure proper cooling as per experiences derived from similar application. 123/145

124 The TDA75xx family includes also Flexiwatt27 package and 2 channels version allowing an high flexibility to choose the best solutions. The equivalent device based on a 2 channels drivers, with the same features is the TDA7575. Consideration about Power dissipation, thermal design, flexibility and mechanical assembly design as well as agreement with customer s request will be taken into account to choose the final optimal solution based on single chip TDA7569 or dual chip solution TDA7575. Other alternative solutions, like classe D audio amplifier (digital PWM Audio Power Amplifier) have been taken into consideration; however, MM realizes that optimal solution as far as regard cost, power dissipation, size of extra circuit components and board space, is to use well known and robust class AB devices like the proposed one. Figure 89. TDA7569 Audio Power Amplifier Block Diagram 124/145

125 Figure 90. TDA7569: Power dissipation vs. average output power Figure 91. TDA7569 application circuit. 125/145

126 Figure 92. TDA7569 packages. Reference [1] TDA7569 data sheet 30 July 2009 [2] BMW DOC404: An internal analog audio amplifier shall be implemented inbox. The maximum output voltage of this amplifier shall be 2 x 4 Ohm and 2 x 2Ohm at operating voltage of 13.8V, THD < 10% per channel. For details see the system and hardware description in the Audio Subsystem section (->). For completeness and reference, the main start-up and shut down requests are reported. Final parameters implementation will be fixed during development. [3] BMW DOC404, Audio Output start up / shut down: As the internal audio amplifier must be de-mute within 1000 msec after MOST light on (or CAN wakeup), the internal and the external analogue amplifier must be synchronous according to release entertainment sources. Thus the entertainment sources must synchronously be played after max msec. See graphics below for details. To achieve a stable Delay of 25ms in times of shutdown on low voltage, it should be considered to use a discharge diode like a shottky diode in serial connection to the main supply to prevent discharging the internal Energy to the bord net. 126/145

127 4.21 CD-ROM drive The MM proposal is to use the PLDS CDM-M10 slim CD-Rom drive module that should be different from CDM-M10 only for the mechanical dimensions. The CDM-M10 module is MM Qualified. The module supports the feature consisting on recognition whether there is no CD or a new CD at the next start-up (cfr. DOC404_34) CDM-M10 drive The CDM10 is up-gradable only via specific CD media. The main features of the CDM-M10 are listed below. Mechanism: - 3 motors concept - Turntable with brushless motor for multi- application usage and for thin design - Pick up drive with stepper spindle motor with excellent track change, noise behaviour - Flexible Mounting - Small form factor - Automatic optimized Vibration / Playability by means of non-linear control techniques Loading: - CD slot loading / eject mechanism - Soft, noise reduced, rubber roller loader with easy media handling Disk Handling: - 2nd disc insertion protection - 12 cm and 8 cm CD disc handling - No damage of mechanism during insert of disc at power off condition - CD position detection and control by means of position switches. CD media compatibility: CD-DA according to Red Book CD-ROM according to Yellow Book CD-Recordable/ReWritable recorded according to Orange Book and finalized according to Red Book (CD R74min; CD R80min, CD RW74min) Copy Protected CD s complying known algorithms Multisession CD playback possible (via SW setting) CD-Text supported with information trasmitted via I2C bus messages. 127/145

128 Supported Speed: 1x (CD-DA), 2x (CD-ROM/R/RW) Main CD Interface (see next figure): Command Interface: I2C bus Data Interface: I2S bus Insertion Switch Reset Signal. Temperature sensor with reporting via I2C messages. Main CD Interface (see next figure): Command Interface: I2C bus Data Interface: I2S bus (unidirectional) Insertion Switch Reset Signal. Temperature sensor with reporting via I2C messages. 8V/3,3V power supply Speed up to 2x QCLC CD reader mounting angle and mechanic : Horizontal front to rear: Any position from horizontal to max /-30 Horizontal left to right: Tolerance of ± 15 on the side (left-right) The CD mechanic is able to resist to at least: The CD mechanic provides a solution to avoid multiple CD insertions. 128/145

129 The Block diagram in the next figure gives an overview of the main blocks of the CDM-M10 Module. Figure 93. CDM-M10 block diagram Main Board 3.3V 8V Logic Core Board INT IN_SW CD I2C I2S RST I2C I2S0 I2S1 / I2S2 I2S CD/MP3/Mic out To Main Board Figure 94. CD interface block diagram Interface Connections The CD is connected to the Logic Core Module by I2S interface for data and I2C bus for commands. The Logic Core can reset the CD via the RST signal. 3V3 (200mA max) and 8V (1,8A max ) a power supply is provided by the Main Board. The proper Power-ON Power-OFF Reset will be implemented, according to module specification. In Sleep Mode both the 3V3 and 8V supply are switched OFF in order to save sleep current. However, the insertion of CD is monitored via the insertion switch pin (47k pull up to 3V3 must be provided) that sense the status of the internal mechanical switch. Therefore an insertion of media CD generate an interrupt signal that wakes up the HU to serve CD functionalities. (see next figure) 129/145

130 Figure 95. Insertion switch wake-up concept. 130/145

131 The HU doesn t provide any external button that can command the CD drive. All required command are supposed to come via CAN messages and will be activated via I2C serial BUS. However, the CDM- M10 provides pins to handle circuits for the eject-command. Figure 96. HW eject line. 131/145

132 CDM-M10 Power Supply Voltage CDM-M10 Operating Temperature An internal Temperature sensor is provided inside the CD Module for thermal protection. The status of the thermal sensor is communicated to the logic system via I2C for thermal management and warning messages. 132/145

133 CDM-M10 Vibration 133/145

134 134/145

135 4.22 Bluetooth The proposed solution for the BT is based on the BT-CSR 63B239A module. See the CSR specific document for more information. On the rear side of the system will be placed a Fakra connector, which code will be discussed with BMW, is provided to serve the BT functionality on a passive external antenna 4.23 GPS The MM proposal for Hardware GPS and Navigation system is based on the ublox single chip UBX- G5010. The GPS Receiver is based on a high sensitivity chipset that allows for optimal GPS tracking signal strengths as low as -160 dbm. Since the solution is single chip, it is optimized for applications that require very high performance in a very small form factor. Main features of the GPS are: 50-channel GPS Correlator L1 Band MHz Accuracy SBAS: <2.0m (CEP, 50%, 24 hours static, -130dBm) Time to First Fix: < 29s (Cold Start), 29s (Warm Start), < 1s (Hot start) with all satellites at -130 db Acquisition Sensitivity: 160 dbm demonstrated with a good active antenna Tracking Sensitivity: 160 dbm demonstrated with a good active antenna Utilizes the ARM7TDMI ARM Thumb Processor Core 2 Mbits Internal RAM 3 Mbits Internal ROM 5-bit 24 MS/s ADC On-chip Single IF Architecture 3 External Interrupts Commercial peripheral 1 USB V2.0 1 UART 1 SPI 1 DDC (I2C compatible) Real Time Clock (RTC) 135/145

136 4 KBytes of Battery Backup Memory Input Power Supply : 3.3V single 56 Pin MLF(QFN) 8 x 8 x 0.85 mm External antenna type Active and Passive Benefits Fully Integrated Design With Low BOM No External Flash Memory Required Hybrid GPS, GALILEO and SBAS (WAAS, EGNOS, MSAS, GAGAN) engine 4 Hz position update rate Supports AssistNow Online and AssistNow Offline A-GPS services; OMA SUPL compliant High immunity to jamming Block Diagram Figure 97. UBX-G5010 block diagram 136/145

137 Architecture Figure 98. UBX-G5010 internal architecture 137/145

138 axis accelerometer BMW Navigation system requires 3 axes accelerometer (inertial sensor) in order to measure the linear and angular accelerations applied to the system. Accelerometers measure the linear acceleration of the system in the inertial reference frame, but in directions that can only be measured relative to the moving system (since the accelerometers are fixed to the system and rotate with the system). The LIS3LV02DQ is a three axis digital output linear accelerometer that includes a sensing element and an IC interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an I2C serial interface. Figure 99. Accelerometer Block Diagram 138/145

139 BMW Entry Nav Head Unit RFQ Technical Proposal Date: 30/10/09 The accelerometer is directly connected to MB microprocessor, via I2C bus, to realize the dead rekoning navigation during the boot of the main CPU. Figure 100. Accelerometer application circuit 139/145

140 BMW Entry Nav Head Unit RFQ Technical Proposal Date: 30/10/ OPTION: Dual DAB DAB T-DMB DAB+ functions are provided through a dual band DAB receiver module from HBAS (DAB- FBxxx).See the HBAS specific document for more information. The tuner is designed for high end DAB reception and covers VHF Band III ( MHz) and L Band ( MHz) compliant to DIN EN Two SMB Fakra antenna connectors are available, first one for VHF and second one for L band. A phantom power (VBATT) is provided to supply external active antennas, this supply is managed through a sensing current diagnosis circuit. The diagnostic is capable to detect the antenna open or short circuit or antenna right connected. During a short circuit the diagnosis is able to shut down the phantom power supply and reactivate the functionality when the short will disappear OPTION: HD Radio The HU is able to manage the HD Radio input RF signal using a TOKO module (TME1178) OPTION: VICS The HU is able to manage the VICS input RF signal using a JRC module. 140/145

141 BMW Entry Nav Head Unit RFQ Technical Proposal Date: 30/10/ OPTION: SDARS SDARS function is available using an evolution of the Multimedia board that incorporates a Sirius receiver instead of a DAB module. Similar to DAB Multimedia board, also the SDARS Multimedia board has the possibility to decode the HDradio. The SDARS Multimedia will use a Fakra antenna connector. For HU, the Sirius Gen. 4.5 module manufactured by Sirius is provided. The concept behind is using external module allow to preserve a common standard electrical pinout, while increasing features and functionality with succeeding generations. Another benefit comes for the seamless development and integration in the system, reducing the time to market. The module incorporates an internal power supply thereby further reducing the complexity of the host system. The module will be selected for horizontal moulting, RF antenna pin, integrated memory for Instant Replay function SDARS Module Type Approval MM will apply to Sirius for the Type Approval of the system (DV and PV). MM already know this procedure, since it is already on-going with it on a telematic system with a Sirius external Box for another customer. Furthermore, MM owns an R&D application center (close to the Sirius HQ) in Farmington Hills (MI) which can effectively assist in Sirius contact management. In order to speed-up the develop and test in Italy, we use a Sirius RF stream generator integrating a software Sirius toolkit made by Averna (Mindready solutions), recommended and approved by Sirius. URT-KIT-SW Signal analyzer Sirius SW toolkit + URT-DRA Dynamic Range Extender PXI-CAN Interface MM has access to the Sirius Arena environment for documentation and RX-type norm access. References [1] Sirius Satellite Radio Inc., Generation 3.0/4.0/4.2 Sirius Receiver Module, Product Specific Specification, February 11th, 2008; RX E, Generation 3.0/4.0/4.2 Sirius Receiver Module Application Note (confidential) 141/145

142 BMW Entry Nav Head Unit RFQ Technical Proposal Date: 30/10/ FPGA In the Main Board is present a FPGA used to route audio signals of the DIRANA II RADIO DSP towards to the FADO MPC5668G and the ESoC3 and to transmit the ASD I2S TDM channels to the D/A converter. The FPGA is provided by Xilinx and it is a Spartan-3E Automotive device; in particular the model that will be present in the HU is the XA3S100E. The Spartan-3E Automotive is a family completely dedicated to the automotive application able to work in an extended temperature range (-40 / +100 C) and qualified to the AEC-Q100 standard. The signals that will be routed to the FPGA are the following: o o o o o 2 x I2S rear set (coming from audio DSP and send to two TDM channels) 1 x I2S TDM ASD (2 channels) generated by the MPC5668 and passing through the FPGA, after the I2S TDM is synchronized with MLB clock 1 x I2S TDM (4 bidirectional stereo channels) 1 x I2S TTS (coming from 1 TDM channel) 1 x I2S entertainment (coming from 1 TDM channel) The ASD audio channels described above will be serialized into a SPI/I2S TDM compatible interface by the FPGA and connected to the secondary microcontroller (MPC5668G). The D-SPI (Deserial-Serial Peripheral Interface) provided by the microcontroller is a high speed channel able to achieve a 20 MHz communication. The bandwidth provided by the DSPI channel allows to merge together the audio streams Configuration The FPGA configuration will be done using the same SPI port that after the inizialization of the logic will connect the microcontroller with the audio DSP and the D/A converter for the ASD. This kind of configuration is called by Xilinx Slave serial. The configuration code, bitstream, has a maximum size of 75 kbyte stored in the internal nonvolatile memory of secondary microcontroller. Main characteristics: Power Supply: o 1.2V Core Supply o 2.5V Core Auxiliary Supply o 3.3V I/O Port Supply Operating Junction Temperature range: -40 C to 105 C Absolute Maximum Junction Temperature +125 C Technology: 90 nm 100k gates, equivalent to 2160 logic cells or 960 slices Block RAM: 72 kbits, Distributed RAM: 15 kbits Package: Very Thin Quad Flat Pack (VQFP) 100 pins Available User I/O: 66, Available Differential I/O pairs: /145

143 BMW Entry Nav Head Unit RFQ Technical Proposal Date: 30/10/ OPTION: ASD The ASD functionality is realized using the secondary microcontroller, the Freescale MPC5668G. The digital audio stream produced by the microcontroller is sent to the FPGA using the SPI channel and then the I2S TDM digital audio is translated to an analog signal using a D/A converter. Finally the analog signal is played by the Audio Power device. In case of an external top HiFi is present, the ASD is sent to it from the MPC5668 directly using the MediaLB interface PCB Main Board PCB The Main Board is designed with a 6 Layers, FR4 type PCB. Punch Through Hole (PTH) vias technology will be used as starting point. However, due to the High Density, High Speed signals and fine pitch of some components, a more complex technology like micro-via and/or Buried vias must be evaluated in detail at start of design, as well as an increasing of the number of layer up to 10. Impedance matching is necessary in order to avoid crosstalk and maintain a good signal integrity, so differential and single ended impedance characteristics will be taken into account carefully. The target is to maintain the characteristic differential impedance of the LVDS track at 100 Ω and the single ended for the RF Receiver and Tuners according at 50Ω; other high speed track without special requirements will be maintained as low as possible (typically less than 80Ω); these goals can be reached by exploiting both embedded micro-stripe and dual strip-line layout structures Power Board PCB The Power Board will be designed with a 6 Layers, FR4 type PCB. However, due to the final size of the PCB Board and complexity, an increasing of the number layer up 8 layers will be considered. The PCB it is designed with PTH vias and stackup, in a similar manner as the Main Board. Because this PCB implements power signals, particular attention will be put during design in order to define the ground plane, power planes and signal track width. If necessary, as for similar design with same complexity that has to handle the high currents of the audio power, this PCB will use a 1oz. copper foil for external layer and 2 oz. copper foil for the internal layer, in order to maintain good performance and reliability. 143/145

144 BMW Entry Nav Head Unit RFQ Technical Proposal Date: 30/10/ EMC Concepts The HU requires special attention on the EMC issues, due to the complexity and density of component as well as for implementation of RF and High Speed Circuit; moreover all functions shall coexist with high sensitive analog path and high current power switching circuits. For there reasons MMSE Electrical and EMC design rules, together with design Check-List will be applied totally during the development phase, at system integration level as well as at PCB layout design level. The main concepts of EMC design applicable to the HU are the following and are summarized in the next figures: System Level EMC concepts: The Metallic Silver Box will be exploit to shield the whole system; the metallic top and botto m cover will help to improve shielding. The CD will use conductive metallic body The Flex cables of CD connection to the Main board will be shielded type. The Logic Core Board will be internally shielded by using conductive plastic in the central part. The rear cover housing dissipator and connectors will use shielded dedicate pins and RF shielded connectors. Simulation and test will be carried out in order to check ground connections alternative and efficiency. PCB Layout EMC concepts Multi-Layer PCB approach and stake-up approach. Application Ground and Power Planes Routing of critical net (RF, Clock, etc) o Impedance Matching o Single and differential impedance tracks Placement of decoupling capacitors Pre/Post layout signal integrity and crosstalk analysis and simulations Design Review Check list with help of internal lessons learnt EMC Tests Layout is first based on schematic EMC design reviews Signal Integrity analysis for critical Nets, using simulation tools Multi-layers PCB Ground management (for entire product) Management of the placement of components Identification of critical Nets Management of power supply planes Layers stackup Particular care with decoupling capacitors, filters, Management of the electrical connections (dedicated areas) for shielding Figure 101. EMC concept at board level 144/145

145 BMW Entry Nav Head Unit RFQ Technical Proposal Date: 30/10/09 End of document 145/145

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