Journal of Signal Processing and Wireless Networks

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1 49 Journal of Signal Processing and Wireless Networks JSPWN Efficient Error Approximation and Area Reduction in Multipliers and Squarers Using Array Based Approximate Arithmetic Computing C. Ishwarya * * Department of Electronics and Communication Engineering, Dr. Nallini Institute of Engineering and Technology, Dharapuram, India. * Corresponding author drnallinicoll@gmail.com ABSTRACT In this paper a general model for array-based approximate arithmetic computing (AAAC) is proposed to guide the minimization of processing error. In this model the key building block of AAAC circuits is the Error Compensation Unit (ECU). While designing the ECU, the two most critical problems are identified viz., determination of optimal error compensation values and identification of optimal error compensation scheme. This general AAAC model achieves optimal trade-offs between accuracy, energy and area overhead. Further reduction in area, energy dissipation and delay of AAAC can be achieved by simplifying ECU's design by introducing logic don't cares. Another unit that plays a key role next to the ECU is the Compression Unit (CU). By using a 5:2 compressor, area can be further minimized. Using the same approach, significant energy consumption and area and error reduction can be achieved in a squarer unit. ARTICLE HISTORY Received 15 June 2016 Revised 30 August 2016 Accepted 09 September 2016 KEY WORDS Array based Approximate Arithmetic Coding, Array multipliers and Booth Multipliers. 1. Introduction With the scale in CMOS technology and VLSI design complexity, it becomes more challenging to design the desired functionalities while managing chip power consumption. The array-based approximate arithmetic computing (AAAC) model provides a remedy and a promising solution for applications that are inherently error resilient viz., media processing, machine learning and neuromorphic systems. In such applications one can trade off accuracy for reduction of energy and area consumed [1][2]. Modified Booth encoding algorithm is an efficient way to reduce the number of partial products by grouping consecutive bits in one of the two operands to form the signed multiples. The operand that is Booth encoded is called the multiplier and the other operand is called the multiplicand. Till now approximate multipliers and squarer has been a great work of the past and the present. Two types of approximate multipliers are in existence viz., Approximate AND array multipliers and Approximate Booth multipliers. 1.1 Approximate AND Array Multipliers It uses AND gates for partial product generation. The two proposed schemes in this type of multipliers are Constant correction and Variable correction 1.2 Approximate Booth Multipliers It uses the modified Booth's algorithm [3] to reduce the no. of partial products. In general the Booth's algorithm conserves the sign of the end result. The modified Booth's algorithm is twice as fast as Booth's algorithm. It reduces the number of partial products by grouping the consecutive bits in one of the two operands to form signed multiples. The operand that is Booth encoded is called the multiplier and the other operand is called the multiplicand. The approximate Booth multipliers are much more efficient than AND array multipliers. Hence they are intensively investigated and the linear regression analysis, estimation threshold calculation and self-compensation approach are utilized to compensate truncation error. Accuracy of approximate Multipliers is increased by using certain outputs from Booth Encoders. Energy consumption is decreased by Probabilistic Estimation Bias Scheme. Here the focus is first on the general array-based approximate arithmetic computing (AAAC) model so as to control approximation errors and attain an optimal error compensation scheme under ideal design scenarios. The proposed model offers critical insights of optimized error compensation schemes and the corresponding input signature logic which serves as a key to error compensation. The method proposed for further reduction of error and cost deals with introduction of extra signatures and logic don't cares making the AAAC circuits more general and complete. Second is by exploiting the design knowledge obtained from the model proposed, a new approximate Booth multiplier and squarer is designed that does optimum error reduction and also has the benefits of delay, area occupied and energy consumed. When the proposed model is implemented with a 90nm CMOS standard cell library, it consumes 44.85% and %

2 50 C. Ishwarya less energy and area compared to the theoretically most accurate fixed width Booth multiplier. =12 maxi,, (2) = 122. Σ =1 (,,) 2 (3) 2. Existing Models ERROR FREE MODEL n-bit inputs Error Free Computing Unit AAAC MODEL n-bit input LPCU ECU CU where N, OAAAC i and OEFCU i denote the number of all possible input combinations, output of the AAAC, and output of EFCU (error-free result), respectively, for each input combination i. Note that the above error metrics are normalized with respect to the range of the output 22n. As shown in Figure 1, for each input combination i, the ECU outputs error compensation denoted by C ompi. Hence the output of the AAAC circuit is: OAAAC i = OLPCU i + C ompi, where OLPCU i is the output of the LPCU. Importantly, the error of the LPCU, i.e., the error of the AAAC before compensation (EBC i ) and after compensation (EAC i ) is given simply by [8] EBC i = OEFCU i - OLPCU i (4) EAC i = EBC i C ompi (5) 2. 2 Model of Error Compensation Unit (ECU) M-BIT OUTPUT M-BIT OUTPUT Fig 1. Conventional Error Free model The conventional Error Free Computing scheme possesses high delay, energy, area and accuracy in contrast to the AAAC model which possesses low delay, energy, area and accuracy as shown in figure 1. The schematic representation of an Error-Free Computing Unit (EFCU) with n-bit inputs and an m-bit output (left) with its approximate counterpart modeled using the proposed AAAC model(right) is shown above [4]. The three basic building blocks in AAAC model are: Low-Precision Computing Unit (LPCU), Error Compensation Unit (ECU) and Combine Unit (CU).The LPCU in the AAAC circuit produces a low-precision approximate output, for example, based upon truncation or a fraction of the input bits, with lowered energy, delay and/or area overheads compared with the error-free EFCU [5]. To reduce the error produced by the LPCU, a low-cost ECU maybe included for error comparison. Finally, the CU combines the error compensation produced by the ECU with the result outputted by the LPCU, generating the final output of the AAAC unit with reduced approximate error. The generality of the AAAC model lies in the fact it reflects the key computing principles behind a wide range of array based arithmetic units, for example, approximate adders, multipliers and squarer. For instance, many approximate adders employ carry prediction from low input bits, which can be thought as a particular way of implementing the ECU. Likewise, error compensation is a common scheme and an important scheme in approximate multipliers and squarer [6][7]. Clearly, the key AAAC design problem is to develop an efficient LPCU and, in particular, an ECU so as to significantly reduce energy, delay and/or area overhead while achieving a low degree of approximation error. 2.1 Error Metrics A given AAAC design with n-bit inputs is evaluated by defining average error E ave, maximum error E max and mean square error E ms, respectively as =1 2. Σ,, =1 (1) Ideally, a specific C ompi can be computed by the ECU to perfectly zero out the error for each input pattern i. However, this does not serve any purpose for approximate computing as we are re-implementing the error-free operation. We present a practical yet general ECU model, which consists of a Signature Generator and a K-to-1 Mux as shown in figure 1(left). Conceptually, for a given input pattern i, the signature generator produces several signatures that encode certain essential information about the input. Based on the actual values of the extracted input signatures, this input pattern is classified into one of the K predetermined input classes with each having a predetermined error compensation C ompj (j = 1,2,...,K). The compensation for this input pattern is produced by using the signature values to select the constant compensation of its corresponding input group via the K-to-1 multiplexer. It is important to note that the structure of the ECU model may not immediately correspond to the specific logic implementation of the ECU. Nevertheless, it captures the general working principle of error compensation for AAAC Error Free Booth Multiplier Operation The operands to the multiplier are passed to the encoder, where both undergo a sequence of selection of partial products and compression of the same and finally all the partial products are added as shown in figure 2. Encoding Selection Compression Adder Fig 2. Error Free Booth Multiplier operation 3. Ideal error compensation and ECU Design To shed light on the ECU according to the proposed model, we visualize the classification of the input space based on the chosen signature for the case of two inputs in figure 1(right), where the input groups may overlap. In the extreme case, if each input group has only one input pattern, then the optimal compensation for each group/input would be simply the corresponding EBC i (eqn. 4). However, in practical cases, we need to consider the EBC i distribution within each group. Now it is evident that the key ECU design problem is to find an optimal signature generation scheme that minimizes one or more error metrics (i.e., E ave, E max and E ms ) under a given set of cost constraints [9] (e.g., area, delay and energy). Note that the cost of the ECU often strongly correlates with the number of input groups K. We show several provable results

3 51 for optimal selection of error compensation constants for a given compensation scheme. We also show an optimal error compensation scheme under an ideal scenario. The proofs are omitted due to space limitation. We first denote the number of input patterns that fall in the j th group by NG j. Theorem 1: The optimal error compensation C ompj for the j th group that minimizes Eave is the median of EBC i of the group if NG j is odd; otherwise it can be any value that falls in the inclusive interval between the two medians of EBC i.minimizing Eave leads to minimization of the sum of distances from each EBC i to C ompj. Theorem 2: The optimal error compensation C ompj for the j th group that minimizes E max is the mean of EBC min and EBC max. Where EBC min and EBC max are the minimum and maximum values of EBC i in the group respectively. Theorem 3: The optimal error compensation C ompj for the j th group that minimizes Ems is the mean of all EBC min in this group. The above three theorems suggest the following important design guidance. For a given compensation scheme, the compensation C ompj for each input group can be optimally determined according to the results above to minimize the targeted error metric. Now we turn into the other design problem by presenting the optimal error compensation scheme under an ideal scenario. Theorem 4: Assume EBC i is uniformly and continuously distributed from EBC min to EBC max, where EBC min and EBC max are the minimum and maximum values of EBC i in the entire input range, then the optimal Ems minimizing error compensation scheme with K input groups partitions the entire EBC i range into K non- overlapping equal-length intervals with one interval corresponding to a specific input group. 3.1 Further Error and Cost Reduction The results obtained from the theorems can be applied to get good error compensation scheme and the corresponding optimal compensation value for each input group. The theoretical results thus attained can be used to come up a good error compensation scheme and the corresponding optimal compensation value for each input group while considering the logic implementation complexity. For a given application, this process may help us identify a highly compact set of signatures. One effective way to reduce error in a good initial set of signatures chosen is to add extra signatures by directly considering certain input bits alone. Those signatures can further divide the predetermined input classes into a larger number of smaller groups. Besides it is also important to minimize hardware implementation cost. This is achieved by introducing don't care terms. In logic synthesis, don't cares can be expressed using special non- Boolean values, such as x. When having the design synthesized by synthesis tools such as Synopsys Design Compiler, we set constraints of minimizing power and area, so an optimal logic will be generated. In designing ECU, The compensation values of a subset of input groups are set to don t cares, thereby reducing the complexity. Now the problem is to find out the groups that can be assigned with don t care values. This can be done only by analyzing the impact on the error metrics when the groups are assigned with don t cares. For this purpose an algorithm which targets E max is applied. Let the number of input groups be M and the length of the compensation value be p bits. Each j th group is evaluated by considering the worst case E max,j when the compensation value is set to don t care X. The groups thus found to have the least E max,j are set to don t cares. There is a limit on the number of don t cares as greater their number greater the error even though it reduces the area and energy consumption. Hence the number of don t cares assigned to groups should be determined from the specification on area, delay and accuracy. 3.2 Practical ECU Design Guidance The above theoretical analysis provides optimal design strategies for minimizing a particular error metric. In practice, minimization of one error metric may often lead to near optimal minimization of other error metrics. We summarize the practical ECU design guidance that is directly resulted from these results: 1) Different input groups shall have no or little overlap on the EBC axis to minimize approximation error; 2) The EBC i spread of each group shall be largely of equal length; 3) Non-uniformity of EBC i spread may be reduced by splitting groups with a large spread into smaller subgroups 4) For a given compensation/grouping scheme, the optimal compensation values for all groups can be determined to minimize a given error metric according to Theorems Proposed Multiplier Design The AAAC model is applied to fixed-width Booth multiplier design and extended to full-width multipliers. 4.1 Basic Idea of Booth Multipliers Radix-4 Modified Booth multipliers are most widely applied and ideal for high speed applications. The encoding block applies the Radix-4 Booth Algorithm to encode the multiplier B, allowing the selection block to generate only half number of partial products needed for array multipliers. Then, the compressors in the compression block compress the number of partial products to two. Finally, a 2n-bit adder is used to generate the final product. Here the concept of n x n fixed width booth multiplier is applied to operate on two n-bit inputs and outputting a n- bit output. Assuming that the higher and lower n bits of the operands correspond to the integer and fractional parts of the inputs respectively, the output will be n-bit integer part of the exact product. The goal is to approach the accuracy of the Post-Truncated multipliers, theoretically the most accurate fixed width multipliers. In AAAC model, the accurate part (AP) and the truncation part (TP) is associated with the LPCU and the ECU respectively for the reason that bits in AP are processed by the LPCU and the TP is processed by the ECU as error compensation. 4.2 ECU Design The key problem is to group the input patterns based on the error observed before compensation i.e., EBC (here θ). This can be done using the Booth encoding table that encodes each set of 3 consecutive bits of multiplier B in to 5 signals and the partial product term is determined in terms of the multiplicand A. In this table 1, z i specifies if the partial

4 52 C. Ishwarya product is zero or not, n i specifies the sign of each partial product. The Booth encoding is applied to the entire array of partial products including the Truncation Part, the part with error. Based on the magnitude and encoded sign the input patterns are classified in to largely equal sized, nonoverlapping groups according to the EBC i values. 4 and Group3(G3) is Case 5, such that is same in each group. The error realization is done by a 3 to 1 MUX. A,B Encoding Selection AP, STP, H 5:2 Compressor Table 1: Booth Encoding Inputs Partial product Booth encoder output ECU Final Addition b2 i +1 b2 i b2 i -1 PP i n i t i o i z i c i A A A A A A Signatures for Each Partial-Product Row The first signature to be chosen is z i, based on whose value the inputs can be classified to zeros and non-zeros. The second signature to be chosen is the n i, whose value gives us the idea on the large non-zero EBC i value there by allowing the grouping of positive vs. negative error. Further reduction in approximation error is done by the third signature to split the large sized error input groups by the magnitude information of each partial product. This is done so by counting the number of non-zero bits (nza) in each partial product. Utilizing the above signatures result in a large number of input groups there by increasing the area and energy. This problem can be overcome by compressing the signatures n i and z i to get the compressed signatures CA and CB respectively 4.4. The Proposed Fixed Width Booth Multiplier In each of the input groups the target error metrics are minimized based on the theorems mentioned in section 3.4. The proposed fixed width booth multiplier is illustrated in figure 3. The ECU is designed such that it works in parallel with the selection block and the part of the compensation block so that the run time delay is reduced to some extent. Further simplification in ECU can be done by considering different combination and groups of signature values as mentioned in Table 2 thereby identifying a smaller set of redefined input groups with controlled error spread. Further simplification is done by grouping the case 2 and 3 to form Group 1 (G1), Group2 (G2) is formed by merging case 1 and Fig 3. Proposed Fixed Width Booth Multiplier Table 2: Compensation for Redefined Input Groups CA Range Case Condition TP,L [0,1] 1 CA=1&CB<3&FA= The rest when CA in [0,1] [2,5] 3 CA=2 & CB>3 & FA=0 CA=2 & CB<3 & FA = The rest when CA [6,8] 5 CA in in[2,5] [6,8] Group Case TP,L 1 2, , The same procedure is applied for Squarer [10] too. Error reduction is defined as follows. Error reduction = ( E existing E proposed / E existing ) *100% where E existing and E proposed refer to one of the error metrics (E ave, E max and E ms ). 5. Conclusion The general model for array-based approximate arithmetic computing (AAAC) is proposed in this paper to guide the minimization of processing error. This proposed general AAAC model achieves optimal trade-offs between accuracy, energy and area overhead. Also it has been found that using a 5:2 compressor, area can be further minimized and also energy consumption also reduced. References 1. M. J. Schulte and E. E. Swartzlander (1993), Truncated multiplication with Correction constant, Proceedings of the 6 th International Workshop VLSI Signal Processing,

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