AN PSoC 3 and PSoC 5LP Internal Analog Routing Considerations. Introduction

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1 AN58827 Author: Mark Hastings Associated Project: No Associated Part Family: All PSoC 3 and PSoC 5LP parts Software Version: PSoC Creator 1.0 or Higher Related Application Notes: None AN58827 discusses how internal trace and switch resistance can affect the performance of a design and how these issues can be avoided by understanding a few basic details ab the PSoC 3 and PSoC 5LP internal analog architecture. Trace and switch resistance are not a concern for most applications. However, this application note teaches the designer when resistance in the signal path may cause measurement errors. Introduction When you add a wire or trace on your PCB, you add some amount of resistance in the signal path. This is also true when adding signal paths and switches in an integrated circuit. The only difference is the scale, but Ohms law still holds true. The PSoC 3 and PSoC 5LP parts are possibly the most flexible mixed signal controllers on the market today. The internal analog switch matrix provides many options when ring signals between analog blocks and (General Purpose Input and Output) pins. The signal paths and switches required to provide this flexibility also add resistance between the signal source and its destination. A detailed diagram of the analog blocks, s, and switch matrix is located in the Appendix at the end of the application note. Calculating Path Resistance To determine the resistance of a path between an analog block and a pin, add up the resistance for each switch and trace in the signal path. Table 1 gives an approximation for the worse case resistance of each analog path and switch. Table 1. Typical Resistance of Internal Paths and Switches Item Label Typical Resistance Small Switch (colored white) Ω Large Switch (colored red) Ω XLarge Switch (colored green) ~ 50 Ω Analog Global AGL[7:0], AGR[7:0] ~ 200 Ω Analog Mux Bus AMUXBUSR, AMUXBUSL ~ 100 Ω Analog Local Bus AbusR[3:0], AbusL[3:0] ~ 100 Ω For a simple path between a pin and the ADC, an estimation of the signal path resistance can be calculated. See Figure 1 for a representation of a simple circuit where is connected to the positive input of the DelSig ADC. Document No Rev. F 1

2 Figure 1. Simple Signal Re Figure 2. Design with Equivalent Resistance V in R path Analog Block V Block R Input MUXBUSL Analog Globals R sw1 abusl0 R AG R sw2 abusl1 abusl2 abusl3 + dsm0 - ADC DelSig The two resistors R path and R Input form a voltage divider so the actual voltage seen at the input by the ADC (V Block ) is not the same as the input voltage, V in. The following equation calculates the error created due to these resistors: Rpath % Error 100 Equation 3 ( R R ) input path Substituting with the actual resistor values; 700 % Error % (100,000, ) Equation 4 The upper half of Figure 1 shows a schematic in PSoC Creator. The lower half of Figure 1 shows one possible path red by PSoC Creator to connect a pin to the positive input of the ADC block. If we analyze the signal path, the signal will pass through two switches and an analog global bus. The total resistance of this path may be approximated by the following equation for this example: Total R Total RSW1 RAG RSW2 Equation 1 R Equation 2 250SW1 200AG 250SW2 700 Substituting the actual resistance values in the equation, you get a signal path resistance of ab 700 Ω. The actual resistance may be less, because the resistance of the analog global shown in Table 1 is the worst case. Values between the absolute minimum and maximum were used for this example. Most signals follow only a section of the global, not the entire length, so its resistance will be less. After calculating an approximate signal path resistance, the designer must ask himself, Does the 700 Ω affect the design? The buffered input to the ADC has an input resistance of greater than 100 MΩ. Figure 2 shows how a voltage divider is created for any analog block that has an input resistance less than infinity and more than zero. Because the input resistance is greater than 100 MΩ and the actual path resistance is less than 700 Ω, the error introduced by the path resistance is less than % or 7 ppm, which is insignificant for most applications. This is also true when using the Comparator, Opamp, and PGA where the input resistance is also greater than 100 MΩ. When does Resistance Matter? The input resistance for most PSoC 3 and PSoC 5LP blocks is shown in Table 2. When the input resistance is greater than 100 MΩ as in the example described earlier, the error is insignificant. On the other hand, where the input resistance is less than a 100 MΩ, the path resistance may be significant. A couple of examples where this is a concern is the un-buffered mode of the DelSig ADC and the inverting input of the PGA. Table 2. Typical Input Resistance to Some Analog Blocks Analog Block DelSig ADC (Buffered Input and Internal source) DelSig ADC (Buffered Input and source) DelSig ADC (Un-buffered Input) Input Resistance >100 MΩ No Op Amp >100 MΩ No PGA >100 MΩ No Affected by Ring Resistance >10 MΩ No, but the difference here is because of the pin leakage >80 KΩ Input resistance is a function of ADC clock and input capacitor Document No Rev. F 2

3 Table 2. Typical Input Resistance to Some Analog Blocks (continued) Analog Block Inverting PGA Mixer SAR ADC (PSoC 5LP only) Input Resistance 20 KΩ or 40 KΩ 20 KΩ or 40 KΩ Yes Yes Comparator >100 MΩ No Affected by Ring Resistance >150 KΩ Input resistance is a function of the sample rate When using the DelSig ADC in the un-buffered mode, the input resistance may be low enough to adversely affect the accuracy of the design. The input resistance of the DelSig ADC is a function of the ADC clock and input capacitance. The input capacitance of the DelSig ADC is between 1 and 16 pf depending on the range and resolution. The actual input capacitance for each range of the DelSig ADC may be found in the ADC s datasheet. The following equation is used to calculate the input resistance of the DelSig ADC. 1 Rinput Equation 5 ( Cinput Fclk ) For example, if the DelSig ADC clock is 3.0 MHz, the resolution is 15 bits and the range is set to ±1 V, the input capacitance is ab 4 pf. Using this equation, the input resistance is ab 83 KΩ. Using Equation 3, a path resistance of ab 700 Ω can introduce an error of 0.7%, which may be significant. The user has the option to either use the ADC s input buffer to eliminate this error, or to continue using the unbuffered input and compensate using firmware. In the case of the Inverting PGA, the input trace resistance affects the gain. The path resistance adds to R 1 in Figure 3. Figure 3. PGA Schematic with Path Resistance V IN R path R 1 R 2 V OUT Normally the gain equation for the Inverting PGA is: Gain Equation 5 If you add the input path resistance to the equation, it is easy to see how it affects the gain in Equation 5. Gain R 2 Equation 6 ( R 1 R path ) gain error is ab 3.5% less than expected or ab 1.7% if R 1 is 40 KΩ. Example Project The example project demonstrates a method to measure the temperature of an external diode, called Delta-V BE. This is a popular method to measure the die temperature of large CPUs and FPGAs. Manufacturers of these parts place a P- N junction on the die and expose the two terminals from this junction to pins on the package. The Delta-V BE method is immune to V BE offsets and does not require temperature calibration. All that is required is an accurate voltmeter and an adjustable current source. The current source only needs to apply two different currents with a known ratio. The absolute value of these currents is not important, just the ratio of the two currents. When each of the currents is applied, the voltage across the P-N junction is measured. The ratio of the currents should be ab 10 or more so that the difference in V BE is large enough to make an accurate measurement. PSoC 3 and PSoC 5LP contain the two components required to perform this measurement, an accurate ADC and an adjustable current source. The following equation is used to calculate the temperature for this method. Where: KT V BE Equation 7 ( q ln( N)) V BE is the difference in junction voltage measured at each current K is Boltmann s constant ( x10-23 ) joules/k q is the charge of an electron ( x10-19 ) Coulombs T is absolute temperature in Kelvin N is the ratio of the two currents First solve for degrees Kelvin: VBE T K ln( N) q K Next, covert to degrees Centigrade: T C VBE ln( ) N Equation 8 Equation 9 If we fix the current ratio to 10, the equation gets even simpler. T ( V 5040) 273 Equation 10 C BE Now that the method and equation are fixed, all that is left is to implement it with a PSoC. Figure 4 shows the schematic from PSoC Creator with an external 2N3904 NPN transistor, as the temperature sensor. R 1 is either 20 K or 40 KΩ for in the Inverting PGA. If the path resistance is as high as 700 Ω and R 1 is 20 KΩ the Document No Rev. F 3

4 Figure 4. Temperature Sensor Schematic Figure 6 shows the actual internal ring for this project and correlates the schematic resistors with the actual switches. Figure 6. Actual Ring of Project C P0[5] P0[7] B E -a V0 I0 V2 I2 VIDAC Test the Project The project is implemented, compiled, and downloaded, but the temperature measurement is much higher than expected, over 60 C. You had expected something closer to 25 C, room temperature. This is an error of ab 35 C, what could have caused this error? Because the circuit uses a current source and we know that switches and internal traces are resistive, an IR drop is the most likely suspect. Adding the actual resistors to the schematic that are inherent from ring generates a more accurate schematic as shown in Figure 5. The input resistance to the ADC is relatively high; therefore, the voltage drop across,, and are insignificant. There is a voltage drop across, but it is of the measurement path. on the other hand, is directly in the measurement path. The current path between the current source (IDAC8) and the external transistor is directly through, which causes a significant IR drop across. When the ADC measures the Base-Emitter voltage (V BE ) of the external transistor, it also measures this voltage drop across. Figure 5. Schematic Showing Ring Resistance -b MUXBUSL abusl0 abusl1 abusl2 abusl3 + dsm0 - ADC DelSig With a current ratio of 10, the volts per degree Centigrade is approximately 200 µv/c. The temperature error is the measured temperature minus the actual temperature. In this case, it is ab 35 C (60 C measured 25 C actual ). So, the voltage error is 35 C 200 µv/ C or ab 7 mv. This voltage error is the IR drop across. The resistance of the switches and the path is estimated by dividing the error voltage by the difference in current. Remember, this method switches between 10 µa and 100 µa so the current delta is 90 µa. The resistance is the voltage drop divided by the current delta, 7 mv/90 µa = 78 Ω. This can easily be explained by the resistance of a switch (XLarge) and some internal ring resistance defined in Table 1 on page 1, which confirms that the error is caused by the ring resistance. IDAC Current Path B C E Document No Rev. F 4

5 Fixing the Problem Now that the mystery is solved, how do you fix the problem? One way is to re the current source to its own pin. This eliminates the switch resistance that was shared by both the current source and measurement path. The ADC now measures only V BE and not the extra voltages caused by an IR drop. See Figure 7 for the new schematic. When the project is rebuilt, compiled, and run, the calculated temperature is within a couple degrees of the actual temperature expected. This small change in the circuit has a big impact on the accuracy of the design, but does cost an extra pin. This design is a corner case, but it emphasizes how a designer should always be aware of trace resistance both inside and side the device. Review the internal ring in Figure 8. Alternative Solution With PSoC there is almost always an alternative solution to every design. In the previous solution the temperature error was eliminated, but at the cost of an additional pin. This may not always be an alternative if your design is tight on pins. Perhaps a better solution is to use the fact that there is both the standard analog global connection as well as the dedicated high current connection to. This way, the path from the IDAC8 and the path from the ADC can be separate until the actual connection to the pad at, and not require a separate pin. See the ring schematic at Figure 9. Figure 9. Alternative Solution Schematic Figure 7. Schematic with Separate Current Path IDAC Current Path P06_iDAC P05_BC R6 B C E R6 B C E Figure 8. Actual Ring of Solution P0[5] P0[7] R6 V0 I0 V2 I2 VIDAC If you evaluate the internal ring in Figure 10, you can see that the current and measurement paths are truly independent up to. If the external diode sensor is near the PSoC, or the PCB trace resistance is low, this is a good solution. If the sensor is connected via a resistive path from the PSoC, the initial solution may be a better alternative, since sharing the current and measurement path is what originally caused the problem. Figure 10. Ring of Alternative Solution P0[5] P0[7] R6 MUXBUSL abusl0 abusl1 abusl2 abusl3 + dsm0 - ADC DelSig MUXBUSL abusl0 abusl1 abusl2 abusl3 V0 I0 V2 I2 + dsm0 - VIDAC ADC DelSig Document No Rev. F 5

6 The schematic of the alternative solution and the original have the same schematic Figure 4, so how do you force this different re? As of PSoC Creator 2.0, an additional tool was added to allow the designer to review and change the re taken by any path. This tool is called the Analog Device Editor. It allows the designer to alter a signal path, and to select alternate analog blocks. The re and block can then be locked so that the re will be static even if you rebuild the project. Figure 11 shows a partial view from the Analog Device Editor of the original temperature sensor design. Notice that the template is very similar to the Analog Interconnect Diagram provide in the appendix, Figure 15. Figure 12. Analog Device Editor view of Alternative Solution Separate Current Path P0[7] Figure 11. Analog Device Editor View of Original Project Measurement Path P0[7] Analog Device Editor Documentation A complete description of the Analog Device Editor and how to use it can be found in the PSoC Creator Document Manager. To find this document, click on the Help menu and select Document Manager. See Figure 13. Shared Current and Measurement Path Figure 13. Document Manager Location By rering the design, you can see the difference in the actual re. The voltage measurement point becomes the actual,. No current from the IDAC8 flows in the measurement path from the ADC. Although these two solutions are the exact same schematic, they are red differently. The Analog Device Editor allows you to make minor changes in just a few minutes. In the case of this example project, it reduced the temperature measurement error from totally unacceptable to down to a degree or two. In the Document Manager, select PSoC Creator Help under the Contents tab and navigate down to Using Design Entry Tools/Design-Wide Resources/Analog Device Editor. This section of the help manual will show you how to examine and to edit your circuit s analog. See Figure Document No Rev. F 6

7 Figure 14. Analog Device Editor Documentation Summary This application note helps you to think ab what is going on inside the PSoC. Usually, the current through the switches and internal traces is so low, that you can completely ignore voltage drops that may occur. When dealing with current sources or inputs that do not have high input resistance, pay extra attention to the signal path and any voltage drops that may occur. Also, remember that Ohms Law is the same whether the circuit is implemented inside the PSoC or the old way, using discrete components on a PCB. Make use of the Analog Device Editor to review how you design has been red. If you do find an issue, this powerful tool can help you force a more desirable re to achieve optimal performance. Ab the Author Some Analog Device Editor features include: View actual signal paths Examine Analog Mux ring and configuration Measure the resistance of a signal path Lock components to a specific analog block Change which analog blocks are used for a given component Re-re signal paths and analog mux res View individual switch resistance Display individual switch control register address and mask values Name: Title: Background: Contact: Mark Hastings Applications Engineer MTS Mark Hastings received his BSEE degree from Washington State University in For most of the last 29 years he has been involved in embedded and mixed signal designs. In his free time he can be found hiking the North Cascades of Washington State. meh@cypress.com Document No Rev. F 7

8 Appendix Figure 15. Analog Interconnect Diagram Vssd Vcca Vdda P0[4] P0[5] P0[7] P4[2] P4[3] P4[4] P4[5] P4[6] P4[7] Vccd Vssd Vddd P6[0] P6[1] P6[2] P6[3] P15[4] P15[5] P2[0] P2[1] P2[2] P2[3] P2[4] Vddio2 AMUXBUSL swinp swinn AGL[4] AGL[5] AMUXBUSL AGL[0] AGL[6] AGL[7] AGL[1] AGL[2] AGL[3] i0 i2 Vddio0 ExVrefL ExVrefL1 P0[0] P0[1] P0[2] P0[3] opamp0 abuf_vref_int cmp0_vref cmp_muxvn[1:0] vref_cmp1 (0.256V) bg_vda_res_en Vdda Vdda/2 refbuf_vref1 refbuf_vref2 (1.2V) dac_vref (0.256V) vssd dsm0_vcm_vref1 (0.8V) dsm0_vcm_vref2 (0.7V) sc0_bgref dsm0_qtz_vref2 (1.2V) dsm0_qtz_vref1 SAR_vref1 SAR_vref2 (1.2V) Vdda Vdda/2 swinn swfol : swinp sc2_bgref vcmsel[1:0] Vdda/3 Vdda/4 refsel[1:0] PSoC 5LP Only en_resvda refbufl_ cmp vssa opamp2 cmp1_vref vssa refmux[2:0] swfol cmp1_vref refmux[2:0] TS ADC P4[0] P4[1] P12[3] sw ExVrefL2 VBE Vss ref swin bg_vda_swabusl0 P12[2] in0 0 + comp0 comp COMPARATOR sc0 Vin Vref Vin Vref sc2 comp2 ABUSL0 ABUSL1 ABUSL2 ABUSL3 v0 DAC0 i0 v2 DAC2 i2 + DSM0 - AMUXBUSL AGL[4] AGL[5] AGL[6] AGL[7] ref in refbufl vcm refs qtz_ref vref_vss_ext VIDAC ExVrefL LPF CAPSENSE Vp (+) Vn (-) SAR0 Vrefhi_ refs DSM AGL[3] AGL[2] AGL[1] AGL[0] AMUXBUSL SC/CT + comp3 - ABUSR0 ABUS ABUS ABUS v1 DAC1 i1 v3 DAC3 i3 ExVrefR in1 1 ref refbufr in SAR ADC ExVrefL1 sc1 Vin Vref Vin Vref sc3 (+) Vp SA (-) Vn Vrefhi_ refs ExVrefL2 AGR[3] AGR[2] AGR[1] AGR[0] AMUXBUSR AMUXBUSR AGR[4] AGR[5] AGR[6] AGR[7] P12[1] P15[2] P15[3] P12[0] P3[7] AMUXBUSL AMUXBUSR ANALOG ANALOG ANALOG ANALOG GLOBALS BUS BUS GLOBALS LPF + - swin sw cmp1_vref opamp3 swfol refbufr_ cmp sc1_bgref sc3_bgref refmux[2:0] P3[6] abuf_vref_int refsel[1:0] cmp0_vref Vddio3 opamp1 refbuf_vref1 refbuf_vref2 (1.2V) SAR_vref1 SAR_vref2 (1.2V) en_resvda swfol ExVrefR Vdda Vdda/2 i3 i1 AGR[7] AGR[6] AGR[5] AGR[3] AGR[2] AGR[1] AGR[4] AMUXBUSR AGR[0] AMUXBUSR swinp swinn swinp swinn P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] GPXT P15[1] GPXT P15[0] Vccd Vssd Vddd USB IO P15[7] USB IO P15[6] P5[7] P5[6] P5[5] P5[4] P12[7] P12[6] P1[7] P1[6] Mux Group Switch Group Connection P2[5] P2[6] P2[7] P12[4] P12[5] P6[4] P6[5] P6[6] P6[7] P5[0] P5[1] P5[2] P5[3] P1[0] P1[1] P1[2] P1[3] P1[4] P1[5] Vddio1 Switch Resistance Small ( ~500 to 700 Ohms ) Large ( ~ Ohms) X- Large ( ~50 Ohms) Ind Vssb Vbat Vboost Vssd XRES Notes: Denotes pins on all packages LCD signals are not shown. Rev #62 26-Mar Document No Rev. F 8

9 Document History Document Title: AN58827 PSoC 3 and PSoC 5LP Internal Analog Ring Considerations Document Number: Revision ECN Orig. of Change Submission Date Description of Change MEH 01/20/2010 New application note A SRIH 07/22/2010 Fixed branding discrepancies B MEH 12/08/2010 Changed title to Internal Ring Considerations for PSoC 3 and PSoC 5 Analog Designs. Updated description of Figure 1. Updated Analog Interconnect Diagram and added caption to diagram. C MEH 01/23/2012 Updated template according to current Cypress standards. Changed the title. Updated Figure 15. Several minor updates. D MEH 11/15/2012 Updated Associated Part Family as All PSoC 3 and PSoC 5LP parts. Replaced PSoC 5 with PSoC 5LP in all instances across the document. E MEH 4/05/2013 Add alternative ring solution and introduce the reader to the PSoC Creator analog editor. Updated the Analog Interconnect Diagram. F AESATMP8 04/19/2017 Updated logo and Copyright. Document No Rev. F 9

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