AS A USEFUL and practical circuit topology, full-bridge

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1 3896 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011 Practical Evaluations of a ZVS-PWM DC DC Converter With Secondary-Side Phase-Shifting Active Rectifier Tomokazu Mishima, Member, IEEE, and Mutsuo Nakaoka, Member, IEEE Abstract This paper presents a feasibility investigation of a zero-voltage switching (ZVS) pulsewidth modulation (PWM) dc dc converter with secondary-side phase-shifting power control scheme. The ZVS-PWM dc dc converter treated here can achieve soft commutation in all the power devices under the wide range of output power variation. By the phase-shifting control that is based on the secondary-side rectifier linked with a high-frequency planar transformer, the effective reduction of idling power in the primary-side inverter as well as snubber-less rectifications in the secondary-side rectifier can be actually attained. The essential experimental data obtained from a 100-kHz/2.5-kW prototype are described herein to validate the soft-switching circuit and control scheme, and then the effectiveness of the dc dc converter is discussed and evaluated from a practical point of view. Index Terms DC DC converter, full bridge (FB), highfrequency (HF) transformer link, phase shifting (PS), primary-side phase shifting (PPS), pulsewidth modulation (PWM), secondaryside phase shifting (SPS), zero-voltage switching (ZVS). I. INTRODUCTION AS A USEFUL and practical circuit topology, full-bridge (FB) converters have been attracting much attention in a wide variety of power supplies for industrial and renewable energy generation facilities such as a dc dc power interface for the grid-connected inverter operating from middle to high power rating [1] [10]. In addition to the unidirectional power flow processing, the high-frequency (HF)-link FB dc dc converters can be effectively applied for bidirectional dc dc power converters, socalled dual active bridge (DAB), for energy storage devices in renewable and distributed power generation systems as well as vehicular power supplies [11] [14]. As a power control scheme for FBs as well as three-level dc dc converters, a primary-side phase shifting (PPS) is a basic and typical strategy since a precise gate signal generation for Manuscript received October 22, 2010; revised December 28, 2010 and February 23, 2011; accepted March 11, Date of current version December 6, Recommended for publication by Associate Editor F. Blaabjerg. T. Mishima is with the Graduate School of Maritime Science, Kobe University, Hyogo, Japan ( mishima@maritime.kobe-u.ac.jp). M. Nakaoka is with the Electric Energy Saving Research Center, Kyungnam University, Korea and also with the Graduate School of Science and Engineering, Yamaguchi University, Yamaguchi, Japan ( mishima@harbor.kobeu.ac.jp). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TPEL switching power devices as well as reducing an electromagnetic interference (EMI) noise can be ensured [8], [15] [21]. In contrast to the advantage, the zero-voltage switching pulsewidth modulation (ZVS-PWM) dc dc converters with PPS, generally, have a severely limited soft-switching range for active switches in the PS leg of the FB inverter. Therefore, the leakage inductance of the HF transformer should be designed to be large enough for obtaining the energy that is required for the softswitching operations, which causes deterioration of the conversion efficiency and difficulty in designing the parameters of the transformer. In addition, idling power losses due to a circulating current appear in the inverter legs under the condition of large phase-shift angle. As a result, the conversion efficiency of the dc dc converters drastically decreases, in particular, for the light load power settings [8] [10], [15], [18]. Furthermore, the turn-off commutations of diodes in the secondary-side rectifier are performed by the hard-switching mode, which triggers the voltage surges and reduces the converter efficiency. Therefore, surge voltage protections such as installation of RCD snubbers are necessary for the diodes in the rectifier. In order to overcome the drawbacks of the ZVS-PWM dc dc converters, zero-voltage and zero-current switching (ZVZCS ) - PWM or improved ZVS-PWM dc dc converters with the PPS scheme have been proposed together with a variety of circuit topologies [3], [15] [18]. The primary-side idling current can be eliminated by reseting the residual energy in the leakage inductance of transformer with the aid of auxiliary circuits that are additionally introduced in the primary or secondary side. However, the total size and cost increase, and, furthermore, the power losses in the auxiliary circuits cannot be negligible, especially, for the light load power conditions. As a solution for the technical issue, the PS scheme based on an active rectifier [secondary-side phase shifting (SPS)] has been proposed and the related soft-switching PWM dc dc converter topologies have been presented for developments of power supplies [7] [9]. The SPS scheme for the first time was introduced in [7], where the saturable inductors were used as the PS-controlled switches. Although some technical challenges still remain, the SPS-controlled PWM dc dc converters are attractive due to the simple structures and the wide range of soft-switching operations. The soft-switching dc dc converters with the SPS scheme can achieve a wide range of soft-switching operations and effective reduction of the power loss deriving from the circulating current in the primary-side HF inverter bridge. Furthermore, the ZVS- PWM dc dc converter with SPS is free from diode reverse /$ IEEE

2 MISHIMA AND NAKAOKA: PRACTICAL EVALUATIONS OF A ZVS-PWM DC DC CONVERTER 3897 recovery current and the related power loss in the secondaryside rectifier, so the lossy RCD snubbers for the rectifying diodes can be eliminated completely. Discussion on the effectiveness of the SPS schemes with active rectifiers is scare in the research reports over the past few decades except for [7] [9], while many of other technical papers have been dealing with the PSP-controlled PWM dc dc converters. One of the papers [9] has already introduced the basic idea of the SPS scheme specified for a ZVS-PWM dc dc converter, and presented the fundamental operation principle together with theoretical analyses and fundamental experimental results. However, practical evaluations and discussions on output power and voltage regulations as well as the converter efficiencies under the various load conditions are unclear, which are important for constructing the high-performance PS scheme. The authors of this paper have also been proposing and experimentally evaluating the ZVS-PWM dc dc converter with SPS in a couple of previous works [22] [24], which are limitedly dedicated to discussions of the dc dc converter application for a power supply in plasma power generators. The main objective of this paper is to originally investigate actual performances of the ZVS-PWM dc dc converter with SPS in a topological aspect by newly introducing the theoretical analysis on the output power control and voltage regulations as well as the experimental verifications. By exploring the switching and steady-state characteristics of the ZVS-PWM dc dc converter with SPS from both the theoretical and experimental points of views, and comparing it with the counterpart, i.e., ZVS-PWM dc dc converter with PPS, a guideline for effective utilization of the PS schemes can be clarified. This paper is organized as follows. The circuit configuration and operation manner as well as the output power regulation strategy are described in Section II. In Section III, the theory of output voltage and power control in the ZVS-PWM dc dc converter with SPS is explained in details with the primary sidereferred equivalent circuits. The soft switching operations and conditions of the dc dc converter treated herein are theoretically clarified in Section IV. In order to demonstrate the feasibility of the DC-DC converter, the experimental results including a power loss analysis based on the newly-developed prototype are described in Section V. Furthermore, the practical effectiveness of the soft switching circuit topology with SPS scheme is discussed in the same Section V in terms of the switching performances, output voltage / power control characteristics, and conversion efficiency, respectively. II. ZVS-PWM DC DC CONVERTER WITH SPS ACTIVE RECTIFIER The circuit diagram of the ZVS-PWM dc dc converter with the SPS scheme is shown in Fig. 1. The secondary-side rectifier consists of the hybrid configuration of diode leg and active switch leg, which is synchronously operating with the primaryside HF inverter. The active switches Q 5 and Q 6 operate with Q 2 and Q 1 in the phase-shift manner, respectively, while the active switches Q 1 Q 4 in the primary-side inverter perform the switching operations in the 180 complimentary manner. Fig. 1. ZVS-PWM dc dc converter with SPS active rectifier. Fig. 2. Relevant voltage and current waveforms of proposed dc dc converter (L m L k 1,L k 2 ). Practical advantages of the ZVS-PWM dc dc converter with the SPS scheme are the following. 1) Wider range of soft-switching operation for load variation. 2) No auxiliary circuit such as auxiliary resonant commutation pole (ARCP) is necessary for performing ZVS operations of the active switches. 3) Effective reduction of the circulating current and the related idling power loss in a primary-side bridge circuit (inverter). 4) Naturally zero-current turn-on/off transitions in the rectifying diodes, so the reverse recover currents can be minimized. 5) Fast dynamical response for load variations due to the secondary-side power control scheme.

3 3898 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011 Fig. 3. Switching-mode transitions and equivalent circuits. The key operating waveforms of the ZVS-PWM dc dc converter with SPS in the buck mode (voltage step-down) are indicated in Fig. 2. In addition, the corresponding switching mode transitions and the equivalent circuits during the steadystate switching one cycle are illustrated in Fig. 3. By starting with the power delivering (mode 0), the operating transitions during the one-cycle in the buck mode are divided into the following ten stages. 1) Mode1(t 0 t<t 1 : ZVS turn-off mode for Q 2 and Q 3 ): The active switches Q 2 and Q 3 are turned off at t 0 ; then, the voltages across the two switches rise gradually by simultaneously charging their lossless snubbing capacitors C r2 and C r3. On the other hand, the voltages across Q 1 and Q 4 decrease gradually by simultaneously discharging their lossless snubbing capacitors C r1 and C r2. In this mode, the voltages across Q 1 Q 4 are written as v Q 1 = v Q 4 = Z 1 I P sin ω 1 (t t o ) (1) v Q 2 = v Q 3 = V in Z 1 I P sin ω 1 (t t o ) (2) where I P represents the magnitude of the primary-side transformer current i p at t = t 0,t 5,t 10 in Fig. 2. In addition, Z 1 =1/ωC 1 =1/(2πf s C 1 ), where f s means the switching frequency, ω 1 =1/(2 L kp C 1 ), and C 1 = C r1 = C r2 = C r3 = C r4, respectively. Note here that L kp denotes the primary-side referred series inductances of the ZVS-PWM dc dc converter, and the magnetizing inductance L m is much greater than L kp expressed as L kp = L k1 + N 2 T L k2 L m (3) where N T (= N p /N s ) represents the turn ratio of the primary- and the secondary-side transformer winding. From (1) and (2), the transition interval T c1 for the ZVS commutation in Q 1 Q 4 can be givenas T c1 = 1 ( ) Vin arcsin t 0 1 (4) ω 1 Z 1 I P where t 0 1 represents the dead time of the gate signals for Q 1 / Q 2 and Q 3 / Q 4. 2) Mode 2 (t 1 t<t 2 : ZVZCS turn-on mode for Q 1 and Q 4 / ZCS turn-off mode in D R2 ): After the edge resonance between C r1 C r4 and the series parasitic inductance L k1 with L k2 of the HF transformer is terminated, the antiparallel diodes of D 1 in Q 1 and D 4 in Q 4 are forward biased, respectively. During this interval, the gates of Q 1 and Q 4 are triggered, and then ZVZCS commutation can be achieved for Q 1 and Q 4. During mode 2 in addition to mode 1, the power-delivering operation continues via the rectifying diode D R2 and the antiparallel diode D 5 in Q 5, whereas the active switch S 5 is on-state. The magnitude of primary-side transformer current i p linearly decreases, and finally, goes down to zero level at t 2. At this moment, the current through the rectifying diode D R2 can commutate naturally to the other rectifying diode D R1.This indicates that ZCS turn-off for D R2 can be guaranteed during this interval. From the beginning of mode 1 to the end of mode 2, i p is almost defined as i p (t) = V in + N T V o (t t 0 ). (5) L kp 3) Mode 3 (t 2 t<t 3 : Inductor energy storage mode / ZCS turn-on mode in D R1 ): The direction of current through the primary-side transformer i p reverses at t 2, and the current

4 MISHIMA AND NAKAOKA: PRACTICAL EVALUATIONS OF A ZVS-PWM DC DC CONVERTER 3899 through the secondary-side transformer i s circulates via D R1 and S 5. In this interval, the energy from the input power source is stored in the series inductance L k1 and L k2. The current through Q 5, i.e., i Q5 gradually rises by the effect of the series inductances, so the ZCS turn-on commutation can be performed for Q 5. During of mode 3, i p is written as i p (t) = V in L kp (t t 2 ). (6) 4) Mode4(t 3 t<t 4 : ZVS turn-off mode for Q 5 and Q 6 ): The gate signal for S 5 in Q 5 is removed at t 3, and the edge resonance starts by C r5, C r6 and L k1, L k2. As a result, the ZVS turn-off commutation can be achieved in Q 5. The voltages across Q 5 and Q 6 are defined as v Q 5 = Z 2 I S sin ω 2 (t t 3 ) (7) v Q 6 = V o Z 2 I P sin ω 2 (t t 3 ) (8) Fig. 4. Simplified equivalent circuits of primary-side inverter for powerdelivering operation in the buck mode: L kp = L k 1 + N 2 T L k 2. where I S represents the magnitude of the secondaryside transformer current i s at t = t 3 in Fig. 2. In addition, Z 2 =1/ωC 2 =1/(2πf s C 1 ), ω 2 =1/ L ks C 2, and C 2 = C r5 = C r6, respectively. Note here that L ks denotes the secondary-side referred series inductances of the ZVS- PWM dc dc converter, and the magnetizing inductance L m is much greater than L ks given as L ks = L k2 + 1 N T 2 L k1 L m. (9) From (7) and (8), the transition interval T c2 for the ZVS commutation in Q 5 and Q 6 can be given as T c2 = 1 ω 2 arcsin ( Vo ) t 5 6 (10) Z 2 I S where t 5 6 represents the dead time of the gate signals for Q 5 and Q 6. 5) Mode 5 (t 4 t<t 5 : Power-delivering mode): Discharging of the lossless snubbing capacitor C r6 across Q 6 continues from the previous mode. Once the voltage across C r6 reaches to zero, the antiparallel diode D 6 is forward biased. Thereby, the input power is delivered to the output side via the D R1 and D 6, and the steady-state powerdelivering mode is initiated. During this interval, the gate of the active switch S 6 in Q 6 is triggered, which implies that the active switch Q 6 (Q 5 ) can always be turned ON under the ZVZCS condition. In modes 4 and 5, i p is expressed as i p (t) = V in N T V o L kp (t t 5 ). (11) The succeeding operating mode transitions from mode 6 to mode 10 (mode 0) are similar to those of mode 1 to mode 5. Fig. 5. Simplified equivalent circuits of primary-side inverter for powerdelivering operation in voltage-balancing mode: L kp = L k 1 + N 2 T L k 2. III. STEADY-STATE ANALYSIS WITH SIMPLIFIED EQUIVALENT CIRCUITS A. Voltage Conversion Ratio The primary side-referred equivalent circuits together with operating waveforms in a buck mode (d = V o /V in < 1), a voltage-balancing mode (d =1), and a boost mode (d >1)are, respectively, shown through Figs Herein, β denotes the zero cross points of i p between 0 <θ<π. 1) Buck Mode: The voltage conversion ratio V o /V in can be obtained from the average voltage across L kp given as (a) φ min <β φ, V o /V in = 1 N T where φ min =(π/2) (1 d). 1 2β/π 1 (φ β)/π (12)

5 3900 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011 Fig. 7. PS gate pulse patterns and waveforms in primary-side inverter: (a) PPS and (b) SPS. Fig. 6. Simplified equivalent circuits of primary-side inverter for powerdelivering operation in the boost mode: L kp = L k 1 + N 2 T L k 2. (b) φ<φ min <β, V o /V in = 1 N T 1 2β/π 1+(φ β)/π. (13) 2) Boost Mode: The voltage conversion ratio can be obtained from the average voltage across L kp given as (a) β<φ min φ, V o /V in = 1 N T 1 2β/π 1 (φ β)/π (14) where φ min = {(d 1)π}/d. (b) φ<φ min. In this case, the transformer current i p is discontinuous. The voltage gain can be derived from i p in the boundary between the continuous and the discontinuous conduction mode at θ = φ expressed as V o /V in = 1 1 N T 1 φ/π. (15) B. Output Power Regulations 1) Buck Mode: The output power controlled by the SPS scheme in the buck mode is given as (a) φ min <β φ, P o = V in [π(π 2β)V in { (π φ) 2 + β 2} ] N T V o 2πX L (16) where φ min =(π/2) (1 d) and X L = ωl kp =2πf s L kp (f s is a switching frequency). (b) φ<φ min <β, P o = V in 2πX L [{(π β)(π φ 2β)+φβ} V in {(π β)(π φ 2β) φβ} N T V o ]. (17) 2) Balancing Mode: In the voltage-balancing mode, the output power P o is given as P o = V in 2 {(φ 2β) φ +2(φ β)(π β) β 2} 2πX L (18) where β = φ/3. 3) Boost Mode: The output power controlled in the boost mode is written as (a) β<φ min φ, P o = V in 2πX L [ {(φ 2β) φ +(π φ)(π + φ 2β)}V in {(π φ) 2 + β 2 }N T V o ] (19) where φ min = {(d 1)π}/d. (b) φ<φ min, P o = V in 2 d 2πX L d 1 φ2. (20) IV. CONSIDERATIONS FOR SOFT-SWITCHING OPERATIONS AND CONDITIONS The SPS PWM scheme is effective for reducing the circulating current in the primary-side FB inverter as compared to the conventional PPS one. This property is attractive for expanding the ZVS range of all the active switches in the primary-side inverter. The voltage and current waveforms of the primary-side inverter are illustrated in Fig. 7 for the PPS and the SPS scheme, respectively. Since the edge resonance of the lagging phase (phase-shifted) switches Q 3 and Q 4 depends on the magnitude of circulating current in the inverter bridge, the soft-switching operation may not be ensured under the low output power settings in the lagging phase switches Q 3 and Q 4. On the other hand, the primary-side FB inverter has no lagging phase switch in the SPS scheme. Therefore, all of the four active switches Q 1 Q 4 in the primary side can be turned OFF in the ZVS mode under the same condition defined as (1/2) L kp I 2 2 P > 2C 1 V in (21) where I P represents the amplitude of primary-side transformer current at t = t 0,t 5,t 10 in Fig. 2, and the lossless snubbing capacitor C 1 = C r1 = C r2 = C r3 = C r4 as mentioned earlier.

6 MISHIMA AND NAKAOKA: PRACTICAL EVALUATIONS OF A ZVS-PWM DC DC CONVERTER 3901 TABLE I ZCS COMMUTATION POINTS (β IN FIGS. 4 6) OF D R1 AND D R2 : ξ =2πX L /R o In addition to this, (4) should be satisfied for the ZVS commutations in Q 1 Q 4. In the similar way, the condition for ZVS in the amplitude of secondary-side active switches Q 5 and Q 6 is described as (1/2) L ks I S 2 >C 2 (V in /N T ) 2 (22) where I S represents the secondary-side transformer current at t = t 3,t 8 in Fig. 2, and the lossless snubber capacitor C 2 = C r5 = C r6 as aforementioned. In addition to this, (10) should be satisfied for the ZVS commutations in Q 5 and Q 6. Equations (21) and (22) together with (4) and (10) indicate that the soft-switching range in all the active switches depends on the load power, and the ZVS becomes critical under the light load condition. In order to attain the ZVS operations for the wide load power range, introduction of dead time control into the SPS scheme is one of the suitable approaches for the light load condition. Turn-off commutations of the rectifying diodes D R1 and D R2 are naturally performed by the zero-current mode as expressed by i p (t 2,t 7 )=0in Fig. 2. Therefore, ZCS turn-off operations can be attained in the full load range. The ZCS turn-off points β (in a phase axis) of D R1 and D R2 can be specified according to the voltage conversion modes as shown in Table I. Those ZCS turn-off commutations cause no parasitic ringings in the rectifying diodes, thereby, any passive or active snubber for clamping the voltages across the rectifying diodes can be eliminated. Moreover, no current-overlapping transition appears between D R1 and D R2, thus, conduction losses can be minimized as well as switching power losses in the rectifying diodes. V. EXPERIMENTAL RESULTS AND EVALUATIONS A. Specifications of Prototype DC DC Converter The prototype of the ZVS PWM dc dc converter with SPS proposed herein has been newly built and tested for examining its practical switching operations and steady-state characteristics. The appearances of the prototype and the HF planar transformer are shown in Fig. 8. Punch through-type high switching-frequency discrete insulated gate bipolar transistors (APT80GP60JDF3, Advanced Power Technology) are employed for all the active switches Q 1 Q 6 in the primary-side FB inverter, and Fast Recovery Epitaxial Diodes (DESI 2x 101, discrete, IXYS) are used for the rectifying diodes D R1 and D R2 in the secondary-side rectifier, respectively. The specifications of the laboratory prototype are tabulated in Table II. The HF planar transformer, the structure of which is illustrated in Fig. 9, has a minimized leakage inductance as described in Table III. Therefore, the core-type additional series inductor L s is externally inserted in the primary-side FB inverter for ensuring the ZVS conditions indicated by (21) and (22). Moreover, in order to avoid the magnetic saturation of the HF planar transformer, a series capacitor C s (=30μF) is inserted in the transformer primary-side winding. In the experiments, five patterns of output voltage V o are selected: for the three cases of V o =70, 80, and 90 V, the ZVS PWM dc dc converter operates in the buck mode. The operation mode at V o = 110 V corresponds to the boost mode, while the condition of V o = 100 V is similar to the balancing mode as aforementioned. Fig. 10 illustrates the total system configuration of the laboratory experiment setup. The load resistivity is constructed with a dc electric load (KIKUSUI PLZ1004W with 2kW booster), and the gate pulses of all the active switches are generated by phase-shift PWM controller UCC 3895 (Texas Instruments). B. Design of Prototype Circuit By giving the series resonant inductor L kp = L s =3μHand the minimum value of the primary-side transformer peak current I P min =10Ain (21), the lossless resonant capacitor C r can be calculated by C r = C 1 =< 1 4 LkpIP 2 min Vin 2 =7.5nF (23) where the input voltage V in = 100 V. Thus, C r can be selected 5nF.

7 3902 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011 Fig. 8. Photographs of newly developed ZVS-PWM dc dc converter prototype: (a) exterior appearance (430 mm 600 mm 130 mm, water cooling), (b) primary-side inverter and gate drive circuit, (c) secondary-side rectifier and gate drive circuit, and (d) HF planar transformer. TABLE II SPECIFICATION OF PROTOTYPE DC DC CONVERTER AND EXPERIMENTAL CONDITION The maximum transition interval T c1max, in which I P becomes minimum for the sake of ZVS constraint, is obtained from (4): T c1max = 1 ( ) Vin arcsin =0.44 μs. (24) ω 1 Z 1 I P min By taking the switching frequency f s = 100 khz into consideration, the dead time of the primary-side bridge can be determined t 0 1 =1μs. Thus, T c1max calculated in (24) is satisfied with (4). The impedance of the series saturation-protecting capacitor C s should be small enough compared to that of L s in the switching frequency. When C r is selected in 30 μf, the voltage across C s is theoretically defined as Fig. 9. Schematic view of the HF planar transformer in prototype (core material: LC3, core shape: PEE at NCD Co. Ltd.). TABLE III PARAMETERS OF HF PLANAR TRANSFORMER V cs = 1 1+ω 2 L s C s V in =1.7V (25)

8 MISHIMA AND NAKAOKA: PRACTICAL EVALUATIONS OF A ZVS-PWM DC DC CONVERTER 3903 Fig. 10. Schematic diagram of experimental circuit. where ω =2πf s. Since V cs is small enough compared to the input voltage V in = 100 V, C s satisfies the condition mentioned earlier. The prototype evaluated herein has the transformer turn ratio N T =1, accordingly, the capacitance lossless capacitor C 2 = C r5 = C r6 in the secondary-side bridge can be similarly designed 5nF. C. Soft-Switching Operations The measured operating voltage and current waveforms in the prototype dc dc converter are shown in Fig. 11. The ZVZCS turn-on and ZVS turn-off operations can be observed in the active switches Q 1 Q 4 of the primary-side FB inverter, respectively. In the similar way, ZCS turn-on and ZVS turn-off operation can be confirmed in the active switches Q 5 and Q 6 of the secondary-side rectifier. Furthermore, it can be observed that ZCS commutations are naturally achieved both at their turn-on and turn-off transitions in the rectifying diodes D R1 and D R2. As a result, no surge voltage occurs in the rectifying diodes, which allows for employing the low-voltage diodes in D R1 and D R2. The currents through the transformer primary winding i p are compared in Fig. 12 between the SPS and the PPS scheme under the same phase-shift angle (φ =45 ). This comparison verifies that the primary-side idling power inherent to the PPS scheme can be reduced sufficiently by employing the SPS scheme. D. Steady-State Characteristics Fig. 13 depicts the steady-state characteristics of the dc dc converter regulated by the SPS scheme with an open loop control (variable output voltage conditions), and shows the actual efficiencies with a parameter of load resistance R o. In addition, the converter characteristics with a closed loop control (constant output voltage conditions) with a parameter of output voltage V o are presented in Fig. 14. It can be understood from Figs. 13(a) and 14(a) that the ZVS-PWM dc dc converter with SPS can regulate the output power over the wide range, especially, with the high output voltages. The experimental results on the output voltage and power regulations that are depicted in Figs. 13(c) and 14(a) well agree with those of the theoretical ones in Figs. 15 and 16. It can be observed from Figs. 13 and 14 that the ZVS-PWM dc dc converter with SPS attains the higher efficiency in the cases of dealing with the medium/high output voltages and low output currents. The efficiencies drop gradually in accordance with increase of the output power. This efficiency drop is concerned with the conduction losses due to the circulating current through the pairs of the rectifying diode and active switch (D R1 and Q 5 in mode 3, and D R2 and Q 6 in mode 8) of the secondary-side rectifier. The power-loss analysis for the power devices in the secondary-side rectifier is provided in Fig. 17. The power losses due to the circulating current in the secondary-side transformer become a high profile part among the total power losses in the secondary-side circuit as the load current, i.e., the output power increases. This result supports the reason of the actual efficiency drops that appear in Figs. 13(d) and 14(d), as mentioned earlier. However, it can be clearly confirmed from the analysis that the power losses caused by the reverse recovery current in the secondary-side diodes can be minimized in the whole power ranges. Thus, any power-consuming snubber can be eliminated in the active rectifier. Additionally, Fig. 17 shows that the volume of the switching power losses (mainly turn-off) is enlarged in accordance with increase of the load current. This is due to the relatively increase both of dv/dt rate and the magnitude of switching currents in Q 5 and Q 6. A pure ZVS operation based on a complete edge-resonance commutation can be ensured at all the active switches for the output power range over 600 W. Although the residual voltages

9 3904 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011 Fig. 12. Voltage and current waveforms in transformer primary winding: (a) PPS scheme (100 V/div., 10 A/div.) and (b) SPS scheme (100 V/div., 10 A/div.). Fig. 11. Switching waveforms of active switches and rectifying diodes in prototype: (a) primary-side leading-phase active switch Q 1 (100 V/div., 20 A/div.), (b) secondary-side lagging-phase active switch Q 6 (100 V/div., 20 A/div.), and (c) diodes D R5 and transformer secondary-winding current i s (10 A/div.). are observed in the lossless snubbing capacitors for the low output power region, where (22) can no more be satisfied, no significant voltage/current surge appears. Thus, the semi-zvs commutation can be ensured for low output power settings in the prototype. E. Efficiency Comparison Between PPS and SPS In contrast to the SPS scheme, the conversion efficiency of dc dc converters controlled by the PPS scheme are generally high in the high output power region, where the idling power due to the circulating current can be significantly reduced, while it is degraded in the range of the low to middle output power by nonnegligible influence of the circulating current [1] [8], [15] [21]. Comparison of the conversion efficiencies from the light to middle load between the PPS and SPS schemes is shown in Fig. 18. It can be understood from the result that the SPS scheme yields better conversion efficiency than PPS from the light to middle load range, where the secondary-side operating current is relatively small. Note here that the measured conversion efficiencies both of the SPS and the PPS scheme are actually not competitive for those of the some available products since the circuit parameters of the laboratory prototypes discussed in this paper are partially derated for the convenience of testing the prototype. As discussed in the experimental results demonstrated herein, occurrence of the secondary-side circulating current is the drawback of the ZVS-PWM dc dc converter with SPS. However, as explained in section IV and discussed in this experimental verification, the soft-switching operating range can be essentially expanded more than the PPS scheme. Hence, the SPS scheme can be considered to be more advantageous than the PPS scheme in terms of reducing EMI noises. The steady-state performances, the power-loss analysis, and the efficiency comparison from Figs. 13 and 18 actually demonstrate that the SPS scheme is more effective and better approach to improve the efficiency of the PS-controlled dc dc converter, especially, from the light to medium output power setting. Therefore, the PPS/SPS dual-mode scheme (PPS for

10 MISHIMA AND NAKAOKA: PRACTICAL EVALUATIONS OF A ZVS-PWM DC DC CONVERTER 3905 Fig. 13. Experimental steady-state characteristics with variable output voltages (parameter is resistive load R o ) : (a) output power versus phase-shift angle, (b) output current versus phase-shift angle, (c) output voltage versus phase-shift angle, and (d) actual efficiency versus output power. Fig. 14. Experimental steady-state characteristics with constant output voltages (parameter is output voltage V o ): (a) output power versus phase-shift angle, (b) output current versus phase-shift angle, (c) output voltage versus phase-shift angle, and (d) actual efficiency versus output power.

11 3906 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 12, DECEMBER 2011 Fig. 18. Comparison of actual efficiencies between PPS and SPS schemes. Fig. 15. Theoretical output voltage versus phase-shift angle characteristics under open loop control based on (12) (15). the high output power range and SPS for the low and middle output power ranges) might be potentially effective for maintaining a high efficiency in the HF-linked PWM dc dc converter by making the best use of their advantageous characteristics. Furthermore, the SPS scheme is also practically attractive for the applications of voltage step-up dc dc power conversion processing from the viewpoints of switching noise reduction and conversion efficiency as discussed in Section III-D with Figs. 13 and 14. Fig. 16. Theoretical output power versus phaseshift angle characteristics under closed loop control based on (16) (20). Fig. 17. Loss analysis for power devices in secondary-side rectifier (V o = 100 V). VI. CONCLUSION In this paper, the practical effectiveness of the HF transformerlinked ZVS-PWM dc dc converter with the SPS scheme has been discussed with the experimental verifications on the 100-kHz/2.5-kW prototype. From the experimental analysis, several advantageous properties about the ZVS-PWM dc dc converter treated here have been clarified, which are summarized as follows. 1) Soft-switching operations can be achieved in all the switching power devices by introducing 100 khz HF switching in the wide load power range. 2) No auxiliary circuit is necessary for performing ZVS operations of the active switches. 3) Reverse recovery current-less turn-off commutation can be achieved for the secondary-side rectifying diodes without any lossy passive snubber. 4) Voltage ratings of the rectifying diodes can be decreased, thereby, the conduction losses in the diodes can be reduced especially under high output voltage conditions. 5) No idling power generates in the primary-side inverter by the SPS scheme proposed, here, while a circulating current appears in the secondary-side rectifier. The occurrence of the circulating current in the secondaryside rectifier is only the technical issue of the proposed dc dc converter. Considering the pros and cons that are demonstrated and discussed in this paper, it can be concluded that the ZVS- PWM dc dc converter with SPS is effective and attractive for the medium and high output voltage applications, where the output power control is based upon the small phase-shift angles.

12 MISHIMA AND NAKAOKA: PRACTICAL EVALUATIONS OF A ZVS-PWM DC DC CONVERTER 3907 Investigations on the primary-side and SPS (dual-mode PS) PWM dc dc converter will be one of the future research topics. ACKNOWLEDGMENT The authors would like to appreciate the kind cooperations and technical supports from Daihen Corp., Osaka, Japan, for developing the prototype dc dc converter. REFERENCES [1] A. J. Mason, D. J. Tschirhart, and P. K. Jain, New ZVS phase-shift modulated full-bridge converter topologies with adaptive energy storage for SOFC application, IEEE Trans. Power Electron., vol. 23, no. 1, pp , Jan [2] A. Bellini, S. Bifaretti, and V. Iacovone, A zero-voltage transition full bridge dc dc converter for photovoltaic applications, in Proc. Intl. Symp. Power Electron., Electr. Drives, Autom. Motion, Jun. 2010, pp [3] T. Song and N. Huang, A novel zero-voltage, and zero-current-switching full-bridge PWM converter, IEEE Trans. Power Electron., vol.20,no.2, pp , Mar [4] Y. Jang and M. M. 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Nakaoka, Three-level phase-shift ZVS-PWM dc dc converter with high frequency transformer for high performance arc welding machines, in Proc. IEEE Applied Power Electron. Conf., Feb. 2010, pp [20] B. Y. Chen and Y. S. Lai, Switching control technique of phase-shiftcontrolled full-bridge converter to improved efficiency under light-load and standby conditions without additional auxiliary components, IEEE Trans. Power Electron., vol. 25, no. 4, pp , Apr [21] U. Badstuebner, J. Biela, B. Faesssler, D. Hoesli, and J. W. Kolar, An optimized 5 kw, 147 W/in 3 telecom phase-shift dc dc converter with magnetically integrated current doubler, in Proc. IEEE Applied Power Electron. Conf., Feb. 2009, pp [22] T. Mishima, Y. Oue, Y. Fukumoto, and M. Nakaoka, An active rectifierphase shifted ZVS-PWM dc dc converter with HF planar transformer-link for RF plasma power generator, in Proc. Int. Conf. Power Electron. Drive Syst., Nov., 2009, pp [23] T. Mishima, Y. Oue, Y. Fukumoto, and M. Nakaoka, A secondary-side phase-shifting ZVS-PWM dual full-bridge dc dc front-end converter for plasma RF power generator, in Proc. Int. Conf. Electr. Mach. Syst., Nov., 2009, pp [24] T. Mishima, Y. Yoshizako, and M. Nakaoka, A high frequency planar transformer-linked ZVS dc dc converter with secondary-side phaseshifting PWM rectifier, in Proc. Eur. Conf. Power Electron. Appl., Sep., 2009, pp Tomokazu Mishima (S 00 M 04) was born in Tokushima, Japan, in He received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the University of Tokushima, Japan, in 1999, 2001, and 2004, respectively. From 2003 to 2010, he was with the Kure National College of Technology, Hiroshima, Japan, where he served as an Assistant Professor for the education and research on power electronics. Since 2010, he has been with Kobe University, Hyogo, Japan, as an Associate Professor, and is engaged in the researches and developments of power electronics circuits and systems. His main research interests are soft-switching dc dc converters, resonant converters, high-frequency inverters, and multi-level inverters applied for marine and automotive power electronics, renewable and sustainable energy technologies, telecommunications and home appliances together with power converter developments for dispersed power supplies. Dr. Mishima received the Best Paper Award in the 8th IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS AND DRIVE SYSTEMS (IEEE-PEDS 2009). He is a member of The Institute of Electrical Engineering of Japan (IEEJ), the Institute of Electronics, Information and Communication Engineers (IEICE), the Japan Institute of Marine Engineering (JIME), and a member and committee member of the Japan Institute of Power Electronics (JIPE). Mutsuo Nakaoka (M 83) received the Ph.D. degree in electrical engineering from Osaka University, Osaka, Japan, in He joined the Department of Electrical and Electronics Engineering, Kobe University, Hyogo, Japan, in 1981 and served as a Professor with the Department of Electrical and Electronics Engineering, Graduate School of Engineering, Kobe University. Since 1995, he has been a Professor with the Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Yamaguchi University, Yamaguchi, Japan. He is also a Visiting Professor with Kyungnam University, Masan, Korea, and the University of Malaya, Kuala Lumpur, Malaysia. His research interests include applications and developments of power electronics circuits and systems. Dr. Nakaoka received many distinguished paper awards on power electronics such as the 2001 Premium Prize Paper Award from IEE-UK, the 2001/2003 IEEE-IECON Best Paper Award, the Third Paper Award in 2000 IEEE-PEDS, the 2003 IEEE-IAS James Melcher Prize Paper Award, the Best Paper Award of IATCf06, the IEEE-PEDS 2009 Best Paper Awards, and the IEEE-ISIE 2009 Best Paper Award. From 2001 to 2006, he served as a Chairman of the IEEE Industrial Electronics Society Japan Chapter. He is a member of The Institute of Electrical Engineering of Japan (IEEJ), The Institute of Electronics, Information and Communication Engineers (IEICE), The Institute of Electrical Installation Engineers of Japan (IEIEJ), Japan Institute of Power Electronics (JIPE), and the other institutions related to power electronics.