Switching Pattern Optimisation Algorithm for Modular Multilevel Converters

Transcription

1 Switching Pattern Optimisation Algorithm for Modular Multilevel Converters Arman Hassanpoor, Staffan orrga School of Electrical Engineering KTH Royal Institute of Technology Stockholm, Sweden Markus Lindgren Automation Technologies ABB Corporate Research Västerås, Sweden Abstract The modular multilevel converters (MMCs) are widely used in different applications in recent years Due to lowloss operation, compactness and high modularity, MMC is greatly attractive for high voltage direct current (HVDC) applications The HVDC station costs and losses are highly related to the switching frequency, capacitor voltage ripple and power quality; which are influenced by modulation algorithm and cell selection methods This paper formulates the modulation algorithm in an advanced mathematical approach in order to initiate a versatile optimisation problem for switching pattern generation The most optimised patterns can be obtained through employing various optimisation constraints for different applications To overcome the calculation complexity for the optimisation problem, a permissive implementable algorithm is proposed and studied in a time-domain simulation platform The method utilizes the current level for switching purposes in order to obtain the lossless switching at zero-current crossing Although this paper focuses on HVDC, the mathematical model is widely available for any MMC application and, consequently, can enhance the converter performance by cutting down the losses I ITRODUCTIO The first voltage source converter based on two-level scheme is experimentally commissioned in 997 in Hellsjön, Sweden [] Later on, the three-level scheme was introduced for HVDC applications in order to enhance the poor harmonic performance of two-level converters Such converter topology is commercially used on the "Cross sound cable link" and "Murraylink" projects in the United States and Australia [], [3] However, the circuit complexity for three-level converters prevented level increase for this topology In due time, modular multilevel converter (MMC) proposed by Marquardt in 3 [4] and rapidly became very attractive in HVDC applications, flexible alternating current transmission systems (FACTS) and railway feeding interties [5], [6] In comparison to previous topologies, MMC brings high modularity and more compact design A high-voltage converter can be built by cascading hundred of cells in series [7] A cell provides a voltage contribution as maintained by energy storage element of the cell, ie cell capacitor voltage In the operation of MMC, the cells are switched frequently to resemble the reference voltage which ultimately controls the transmitted power Furthermore, the cell capacitor voltages are required to evenly distribute the capacitive energy over the cascaded cells, consequently, a number of switchings are needed to maintain the capacitor voltage balancing On the other word, cells are switched both for attaining the reference voltage as well as keeping the cell voltages balanced An individual cell voltage feedback control [8] and ranking the cells based on the voltage levels [4] are two well-known balancing methods Individual cell feedback control requires no complicated control hardware while it restricts the implementation of programmed modulation methods [9], on the other hand, capturing hundred of cell voltages and rank them in a small time step requires advance control hardware Besides, cell switchings are associated with semiconductor devices which in case result in semiconductor switching losses Various modulation methods have been proposed to fulfill the MMC requirements and also cut down the switching losses by reducing the switching frequency [9], [] However, all available methods tries to bring down the switching frequency as converter switching loss is not only related to the switching frequency but also depends on the current level at the switching instance As an inventive approach the effect of current level in the generated switching pattern is considered in the proposed method in this paper in order to minimize the switching loss as well as controlling the capacitor voltage ripple based on the design criteria The modulation and cellselection problem is initially formulated as an optimisation problem in Section II which enables the minimisation of converter switching loss The analogous problems and solutions in the field of computer science is introduced in Section III Section IV is devoted to the simulation results for a proposed heuristic method which is implemented in a pointto-point HVDC model At the end, the conclusion is drawn in Section V II MMC DESCRIPTIO AD PROBLEM STATEMET A MMC Topology Circuit schematic of MMC with half-bridge cell configuration is depicted in Fig (a) A transformer links the three-phase converter to a three-phase alternative current (ac) power network at the point of common coupling (PCC) Each converter phase comprises two converter arms in which cells are connected in series Two controllable semiconductor switches (Sw n, Sw n ), ie insulated-gate bipolar transistor (IGBT), determines the voltage contribution of the corresponding cell by inserting or bypassing the cell capacitor (C), which

2 respectively exposes v capn or zero voltage level at the cell terminals Accurately enough, it is assumed that capacitor voltages are either constant during the bypassed period or differing during inserted intervals The conversion from ac to dc and contrariwise is carried out by synthesising different voltage levels in each converter arm Different voltage levels would be available by manipulating the number of inserted cells in each converter arm Therefore, the converter arm voltage (v p,n (i)) can be described as: in which S n = v p,n (i) = S n v capn () n= if n th cell is inserted if n th cell is bypassed and i indicates the phase number The switching signal (S) is the ultimate control action which determines the converter arm voltage based on the reference voltage (vp,n ref ) for the corresponding arm vp,n ref is generated, considering the amount of required active and reactive power at PCC and/or the required voltage at dc side These conditions determine the converter operating point However, the dynamic control of the converter is realized by controlling the ac current towards the grid (i s ), current towards dc side (i d ) and internal circulating current (i c ) [] The converter dynamic relations can be obtained through Kirchhoff s voltage low in an arbitrary converter phase of Fig as follows: di p v dc + v p + Ri p + L arm dt + L di s T dt + v g = () di n v dc v n Ri n L arm dt + L di s T dt + v g = (3) The dynamic relation for the output current is obtained by adding () and (3) and simply yielding as di s L eq dt = v s R i s v g (4) v s = vn vp :inner emf, driving i s i s = i p i n :converter phase current L eq = + L T :equivalent reactance in the system Similarly, the dynamic relation for circulating currents are available through subtracting () and (3) as di c L arm dt = v c Ri c (5) vc = v dc vn+vp :internal voltage, driving i c i c = ip+in :circulating current (4) and (5) defines the fundamental differential equations for current controller (i s ) and also circulating current controller (i c ) which are referred as a high level control in Fig (b) These two currents are controlled through reference voltages for inner emf and internal voltage (vs ref and vc ref ) and since the insertion indices can be selected with two degrees of freedom vg AC Grid Measured data Order data Swn Swn C Single Structure Point of Common Coupling Power Controller + vcap - Transformer n is(i) Current Controller Arm Arm 3 Arm 5 ip ip ip3 High level control R R R R R R in in in3 Arm Arm 4 Arm 6 (a) (b) Insertion umber Generation ref n p, n vp(i) vn(i) id id Measured data Modulation Strategy Low level control vdc vdc Firing Pulses (S) Fig Modular multilevel converter (a) circuit schematic, (b) control block diagram then v ref ph and vref c can be set independently However, the reference voltage for each arm can be obtained by solving v c and v s for v p and v n as: v ref p = v dc v ref s v ref c v ref n = v dc + v ref s v ref c (6) On the other hand, according to () and the assumption of nominal capacitor voltage (vcap nom ) equal to v dc for each cell, the arm reference voltages can be simply obtained as an integer numbers which determines the number of inserted cells in the corresponding arm: n ref p,n (i) = S(k) = Round( vref k= p,n (i) vcap nom ) (7) The Round function in (7) assigns the nearest integer value of the input to the insertion number of n ref p,n (i) Therefore, the converter control, ultimately, is realized by regulating the number of inserted cells according to n ref p,n (i) in each time step B Problem Statement As is explicated in previous subsection, the high-level control continuously determines the number of required level in each arm (n ref p,n ), nevertheless, there are many combinations

3 Percent [%] umber of availbale combinations [Log] 3 All available combinations for the case = to = 5 4 Eon, Tvj = 5 C Eoff, Tvj = 5 C 5 E [J] umber of required level, n ref I c [A] Fig Available combinations for = to (: number of cells/arm) Fig 3 45kV Infineon IGBT module switching energy vs collector current (ref: wwwinfineoncom) which can synthesis the n ref p,n and it can be configured as: ( )! n ref = p,n n ref p,n!( n ref p,n )! (8) (8) is valid for all n ref p,n,,, } and is numerically plotted in Fig for a converter with cells per arm in the range of,, } This Figure illustrates how many cell combinations are available for different voltage levels in each arm and also how the number of these cell combinations grows exponentially when the number of cells () arises Evidently, the converter loss and also cell voltage design is influenced by the selected cell combinations A proper cell selection method is to recognise the most suitable cells combination at each moment while considering the generated switching losses and cell capacitor voltages Therefore, the cell selection method can be formulated as an optimisation problem with different constraints and objectives for different applications The mathematical principle for the optimised cell selection method is developed in this paper However, the discussed constraints and objectives are specified for HVDC application Conventionally, the modulation and cell assignment methods either employ carrier-based pulse width modulation (PWM) [8] or sorting algorithm [4] The main objective of both methods is to maintain the balanced capacitor voltages for all cells while the required number of cells (n ref p,n ) are inserted However, neither of the aforementioned methods considers the current level at switching time As is shown in Fig 3, the semiconductor switching loss proportionally relates to the conducting current (I c ) at the switching time For instance, a turn-on event at I c = 8A exposes 4J which is two times greater than a turn-on event at I c = 4A Therefore, the total generated switching loss is not only related to the switching frequency but also is related to the current level at switching instance The proposed mathematical formulation of the cell selection method enables the integration of current level in cell selection algorithm C Mathematical Modeling Let s take the steady-state operation of a converter, rated for active power of P =MW and reactive power of Q=3MW at 5Hz The typical arm current (i p ) and insertion index (n p ) X: Y: 88 Arm Current vs insertion index [one cycle] X: 5 Y: X: 65 Y: X: 788 Y: X: 558 Y: 93 Discharging interval X: 848 Y: - Charging interval t t t k t n Fig 4 umber of inserted cells (%n p of ) vs corresponding arm current (%i p of i max p ) for an arbitrary arm are plotted in Fig 4 for one period Both curves are normalised to hundred percent of their maximum values Each arm current period is divided in two charging and discharging intervals, according to the converter operating point The positive arm current will charge up the inserted cells capacitor and the negative arm current will discharge the capacitor of inserted cells Referring to Fig 4, during each time step, the voltage of each inserted cell varies according to: v capn (t) = v capn (t ) + S n (t) v cap (t) (9) v cap (t) = C t t t i p (t)dt () ote that t is the sampling time step of control system The voltage-change vector ( v cycle ) is defined as: v cycle = S n v cap () for one cycle The " " denotes the element-wise product of two matrices S n and v cap which are the vectorised representation of switching pulses and differential capacitor voltage for the whole cycle as: S n = cell cell cell t S (t ) S (t ) S (t ) t S (t ) S (t ) S (t ) t n S (t n ) S (t n ) S (t n )

4 and + v cap (t ) + v cap (t ) + v cap (t ) + v cap (t ) v cap = + v cap (t k ) + v cap (t k ) () v cap (t k+ ) v cap (t k+ ) v cap (t n ) v cap (t n ) The row-wise study of S n determines the first problem constraint as: Constraint : n ref p (t) = S n (t) (3) t= n= This constraint ensures that the number of inserted cells is equal to the number of requested cells at each time step Further, the differential capacitor voltage matrix ( v cap ) shows the amount of voltage change in each time step Referring to () and Fig 4, the cell capacitor voltages are increased associated with the positive difference voltage from t to t k while the current crosses zero at t k and hereafter, the negative difference voltage is exposed to the inserted cells and decrease the cell capacitor voltages As is discussed in [], the cell capacitor voltage can not exceed a certain limit This limit is determined by the cell design and is related to the semiconductor blocking voltage However, the cell selection algorithm needs to ensure that all cell voltages are balanced between a maximum (V max ) and minimum (V min ) level all the time This leads to the second constraint as: Constraint : V min v capn (t) V max (4) n= t= Up to now, the cell behaviour in one period is analysed, based on an available switching pulse pattern and cell voltages However, the converter steady-state operation permits the assumption of analogous arm current in all cycles In this case, the cell selection method can determine the switching pulse pattern at the beginning of each cycle based on the arm current from the previous cycle So, the optimisation subject is to find the pulse pattern matrix of S n for the coming cycle based on the v cap matrix from the previous cycle while both constraints are satisfied in all times Hereafter, this optimisation subject is defined as X n The goal is to find an X n (t) for all moments t and all cells n, such that an objective function is minimised There are different possible variants of this function and below are two examples: ) Minimise the switching frequency: Each element of the switching pulse matrix (X n ) is either (inserted cell) or (bypassed cell), therefore, X n can be considered as a binary matrix in which each column corresponds to the status of one cell during one cycle and each row indicates the status of all cells at each time step So, considering one column of X n, we can define a switching-change matrix ( X n ) as: X n (t) = (X n (t) X n (t )) (5) which points out the switching moment for each cell in one cycle In simple words, S n is a binary matrix which is made based on the switching pulse matrix (X n ) and all its elements are zero except the moment that the status of the corresponding cell is changed So, the number of switching events are realised through column-wise summation of X n and, consequently, the first objective function can be defined as: Objective : min f (x) = n= t= which minimises the total switching frequency X n (t) (6) ) Minimise the switching power loss: As is discussed in Section II-B, the switching power loss is proportional to the current level at switching moment, see Fig 3 Moreover, the switching moment is realised in X n according to (5) Therefore, the switching cost can be determined by multiplying a weighting factor with X n The weighting factor (W F ) is computed in agreement with current level as: ( W F = i norm t ) T,, i norm, i norm t k+,, i tn (7) t k i norm t = i p (t) i max p W F represents a unity-based normalised cost function for switching events in the rang of [,] The most costly switching event is the one which occurs at W F (t)= and any switching which happens at W F (t)= (zero current crossing) is almost lossless event Indeed, the switching events at lower W F generates less switching power loss So, the second objective function, now, can be defined as follow: Objective : min f (x) = n= t= which minimises the total switching power loss III METHOD DESCRIPTIO W F (t) X n (t) (8) The cell selection method is to select the most suitable combination from all feasible solutions in (8), such that objective function (8) is minimised and constraints (3 and 4) are upheld The result would be the switching pattern which generates the minimum power loss In this case, the cell selection method is a discrete variables optimisation problem (combinatorial) which needs to be solved in the beginning of each cycle, based on the predicted arm current from the previous cycle However, there is no straightforward solution for this combinatorial optimisation problem as: The solution space is dramatically large depending on the number of cells and also the control system sampling frequency The execution time for the optimisation solver should be as short as the control system sampling time (in the range of micro seconds)

5 Two similar problems are well-known in the field of computer science which are studied firstly in this Section and later, some potential solutions are introduced in order to reduce the complexity of the method A Similar Problems ) Bin-packing problem: A similar problem to the one presented in Section II-C is bin-packing [3] Bin-packing is concerned with packing a set of k items, each with a specific weight, w j, into as few bins as possible, each with a capacity q The problem is to assign each item to a bin, without violating the bin s capacity, and find an assignment to bins which minimizes the number of used bins Mathematically the problem can be formulated as follows: minimise z = k i= y i k constraint j= w jx ij qy i, i =,, k} k constraint i= x ij =, j =,, k} if bin i is used y i = otherwise if item j assigned to bin i x ij = otherwise The main differences compared to the cell selection optimisation problem, stated in Section II-C are: The number of bins (cells) is fixed in cell selection optimisation problem At each sample there is a fixed number of bins (cells) which needs to be used (n p,n ) There is a part of cycle items (voltage) is removed from the bins (discharging interval) There is a minimum limit for the items (voltage) for each bin (cell) Bin-packing is well-known to be P-hard (non-deterministic polynomial-time hard) [4] which has no polynomial-time solver ) Knapsack problem : Knapsack problems [4] are similar to bin-packing problems with an addition condition that each item has an associated value (a j ), the goal is to maximize the value of the items which can fit in the knapsack Furthermore, there is only a single knapsack, ie, not multiple bins as in the bin-packing problem The problem is formulated mathematically as follows: maximise z = k j= a jx j k constraint j= w jx j q, j =,, k} x j = if item j is selected otherwise and w j and q are weight of the item j and the bin capacity, respectively With respect to the cell selection problem presented in Section II-C, using bin-packing as an analogy works well when minimizing the number of switches (objective (6)), while the knapsack problem more closely matches the problem of minimizing the cost of switching (objective (8)) However, similar to bin-packing problem, knapsack problem is also P-hard problem and if there are execution time constraints,which is the case in cell selection problem, there is basically no other choice than to resort to approximate solutions rather than optimal solutions B Potential Solutions The optimal solvers for P-hard problems have long execution time These solvers have to evaluate, in essence, all combinations before finding an optimal solution Therefore it is very frequent to employ heuristics to solve these kinds of problems, since these can often produce good enough solutions in short execution time ote that we have not proven that the cell selection problem is P-hard, but as is noted in Section III-A, there are strong similarities with bin-packing and the knapsack problem However, this subsection contains a brief excerpt of the available approaches for such a P-hard problem, and ends up with a heuristic solution ) Local search: Local search techniques [5] start at some point in the solution space and tries to move in a direction from the starting point which improves the solution This procedure is repeated until the solution no longer improves There are several different kinds of algorithms belong to the class of local search methods One drawback with local search is that there is a possibility to get stuck in a local minimum/maximum depends on what is being sought ) Local search + Genetic algorithm : Local search can be combined with other techniques to form hybrid approaches As an example, genetic algorithms which have higher probability of reaching close to the global optimum, may sometimes not reach the actual optimum due to lack of local search behavior By combining local search and genetic algorithms there is a potential to tackle the drawbacks of both methods 3) Pre-computed solutions(caching) : As is mentioned in Section III, the arm current can be predicted from the previous cycle when the converter operates in steady-state In case there is a little variance among the different cycles, there is a potential to pre-compute solutions to the problem or to cache good solutions which are later reused 4) Divide and conquer: In the cell selection problem there is a possibility to divide the problem into one positive and one negative period see () Potentially one could devise methods which solve these parts separately or to use one method for charging interval and one for discharging interval 5) Heuristics: Based on the available literature in the computer science field [4], it seems that heuristics have the best chance of solving the cell selection problem in sufficiently short time Heuristic bases the solution on some knowledge available from the constraints and objectives of the problem Based on that, a heuristic method is proposed in this paper that first uses the cells with high voltages during low currents

6 L=sort cells (descending) YES Start zero current crossing? O Load the previous sorted list (L) TABLE I CIRCUIT PARAMETERS USED FOR SIMULATIO Quantity otation Value Rated active power P GW Rated reactive power Q 3 MVAR Direct voltage v dc 3 kv Alternating voltage V 4 kv Rated frequency f 5 Hz umber of cells/arm 4 capacitance C 35 kj/mw Transformer leakage reactance L T 5%pu Transformer Resistance L R 5%pu Turn off cell(n) Turn on last off cell from L list Fig 5 O vcap(n) < V max YES Assign L( to np,n ref ) O YES ip,n(t) < End vcap(n) > V min YES The flowchart of proposed method, CT Boptimised O Turn off cell(n) Turn on first off cell from L list while keeps the cells with low voltages for high current intervals In this case the number of switching events are minimised during the high current intervals which leads to less generated switching loss Moreover, the proposed method utilises the zero current crossing to do the switching for balancing purposes (lossless interval) The method is named CT Boptimised, optimised cell tolerance band modulation The flowchart for the proposed method, CT Boptimised, is available in Fig 5 This method requires no current prediction for the coming cycle and is modified for online implementation in real-time control systems It is proposed to create a sorted list (L) out of the cell voltages in ascending order such: L = (v cap (highest),, v cap (lowest)) (9) at the time that corresponding arm current crossed the zero level The number of required cells (n ref p,n ) are assigned to be inserted from the sorted list L in each time step while this list is updated only at zero current crossing However, the mechanical and electrical design of the cell lays the maximum and minimum limits on cell capacitor voltages [6] So, each cell should not charge more than V max and discharge below V min These voltage limitations are defined as a tolerance band in the proposed method So, if a cell voltage reaches the V max or V min it will be bypassed and the last off-cell in L will replace it In such a trend, the cells with the highest voltages will charge up to V max in low current intervals, later, the cells with the lowest voltages are inserted during the high current levels and consequently, these cells can be kept on for a longer time and less switching for balancing purpose is required IV SIMULATIO RESULTS A point-to-point HVDC link is modeled in a time-domain simulation software (PSCAD/EMTDC) in order to study the performance of the proposed cell selection method The basic parameters of the simulated model is specified in Table I The converter under study has the topology illustrated in Fig consists of 4 cells per arm A generic high-level control based on open-loop control [7] is implemented in the converter under study Moreover, a third-order harmonic (zero sequence) is added to the reference voltage in order to maximise the converter voltage capability Fig 6 shows the simulation results for the steady-state operation of the converter works at rated operating point (P =GW, Q=3MVAR) Fig 7 clarifies how the cell capacitor voltages vary inside tolerance band (V max,v min ) according to the arm current in one cycle V max has been set to % over the nominal cell voltage of 6kV, in this study, which ends up to total average switching frequency equal to 5Hz ote that the sorted list (L) updates at zero-current crossing moment, therefore, 7% of the switching events are appeared at the current level below A which generates relatively no switching loss However, the average switching frequency for the switching events at the current above A is 95Hz, which in comparison to the conventional carrier-based pulse width modulation (PWM) methods [] shows 5% improvement In [], the switching frequency of the converter with the same condition is Hz The features of the proposed cell selection method can be summarised as: It utilises the zero-current crossing to perform the balancing switching events at lossless moment It minimises the switching events at high current intervals by reserving the cells with high voltage availability The cell capacitor voltages are directly controlled by fix tolerance bands Sorted list needs to be created only twice in each cycle Fundamental switching frequency is achievable for some operating point V COCLUSIO The modulation and cell selection problem of the modular multilevel converters are mathematically formulated as a combinatorial optimisation problem which are, continuously, subjected to the cell voltage and reference voltage constraints The objective functions are also developed to enable the minimisation of converter switching losses The comparison

7 Current [ka] Voltage [unity-based normalised] Voltage [kv] umber of inserted cells Current [ka] Converter arm current (a) umber of required cells (n p ref ) (b) capacitor voltage ripple, CTBoptimised (c) Fig 6 Simulation results for proposed method (a) Converter arm current, (b) umber of required cells (n ref p ), (c) Capacitor voltage ripple Arm current vs cell capacitor voltages, CTBsort s with high voltages s with low voltages Charging interval Discharging interval Fig 7 Arm current vs capacitor voltage ripples in one cycle for the proposed method, CT Boptimised between the cell selection problem and similar problems in the field of computer science disclosed that the heuristic methods advance the most fast solution for the cell selection problem However, a heuristic method is proposed in this paper which utilises the zero-current crossing (lossless interval) for doing the switchings for balancing purposes The proposed method requires no advanced control hardware since the method relies on a sorted list out of cell voltages which is updated only twice in each cycle The simulation results show that average switching frequency is 95Hz, considering the switching events V max at currents above A It shows an improvement of 5% in the switching frequency in comparison to the conventional carrier-based PWM methods which, ultimately, brings a lower converter operation cost REFERECES [] G Asplund, K Svensson, J Häfner, J Lindberg, and R Pȧlsson, Dc transmission based on voltage source converters, in Cigré paper o 4-3, Paris, France, 998 [] I Mattsson, B Railing, B Williams, G Moreau, and C Clarke, Murraylink, the longest underground hvdc cable in the world in Cigré Paper o B4-3, Paris, France, 4 [3] B Railing, J Miller, P Steckley, G Moreau, P Bard, L RonstrÃűm, and J Lindberg, Cross sound cable project, second generation vsc technology for hvdc, in Cigré Paper o B4-, Paris, France, 4 [4] A Lesnicar and R Marquardt, An innovative modular multilevel converter topology suitable for a wide power range, in Proc of IEEE PowerTech, Bologna, Italy, June [5] M Winkelnkemper, A Korn, and P Steimer, A modular direct converter for transformerless rail interties, in Proc IEEE ISIE, Bari, Italy, July 4-7, pp [6] M Hiller, D Kurg, R Sommer, and S Rohner, A new highly modular medium voltage converter topology for industrial drive applications, in Proc European Power Electronics Conf, Barcelona, Spain, September 8-, pp [7] H H J Dorn and D Retzmann, A new multilevel voltage sourced converter topology for hvdc applications, in Cigré Paper o B4-34, Paris, France, 8 [8] M Hagiwara and H Akagi, Control and experiment of pulsewidthmodulated modular multilevel converters, IEEE Trans Power Electron, vol 4, pp , July 9 [9] K Ilves, A Antonopoulos, S orrga, and H-P ee, A new modulation method for the modular multilevel converter allowing fundamental switching frequency, IEEE Trans Power Electron, vol 7, pp , August [] Q Jiangchao and M Saeedifard, Reduced switching-frequency voltage-balancing strategies for modular multilevel hvdc converters, IEEE Trans Power Del, vol 8, pp 43 4, August 3 [] L Harnefors, A Antonopoulos, S orrga, L Ängquist, and H-P ee, Dynamic analysis of modular multilevel converters, IEEE Trans Ind Electron, vol 6, pp , July 3 [] A Hassanpoor, S orrga, H-P ee, and L Ängquist, Evaluation of different carrier-based pwm methods for modular multilevel converters for hvdc application, in IECO - 38th Annual Conf on IEEE Ind Elec Society, Montreal, Canada, October 5-8, pp [3] S Martello and P Toth, Knapsack Problems: Algorithms and Computer Implementations, st ed John Wiely & Sons, 99 [4] T Izumi, T Yokomaru, A Takahashi, and Y Kajitani, Computational complexity analysis of set-bin-packing problem, in IEEE International Symposium on Circuits and Systems, Monterey, Canada, 3 May 3 June 998, pp vol6 [5] Y-K Kwok and I Ahmad, Benchmarking and comparison of the task graph scheduling algorithms, IEEE Trans Parallel Distrib Syst, vol 59, pp 38 4, December 999 [6] A Hassanpoor, L Ängquist, S orrga, K Ilves, and H-P ee, Tolerance band modulation methods for modular multilevel converters, IEEE Trans Power Electron, vol PP, p, February 4 [7] L Ängquist, A Antonopoulos, D Siemaszko, K Ilves, M Vasiladiotis, and H-P ee, Open-Loop Control of Modular Multilevel Converters Using Estimation of Stored Energy, IEEE Trans Ind Appl, vol 47, no 6, pp 56 54,