Specifications are at T A = 25 C

Transcription

1 DEMO MANUAL DC09B DESCRIPTI Demonstration circuit 09B is for evaluating the performance of the LTC 98 Multichael Power Supply Sequencer and Supervisor. The LTC98 sequences and monitors up to four power chaels in power-up and power-down, and it monitors those outputs in the steady state. Sequencing is accomplished by controlling the power supply enable inputs or N-chael MOSFET gates with the LTC98 outputs. Supervisory functions include undervoltage and overvoltage monitoring, and capturing the output state information in the event of a system fault. Inherent fault detection circuitry can detect: Stalled supplies (during sequencing) Supplies with the output voltage not satisfying the undervoltage or overvoltage conditions LTC98 Multichael Power Supply Sequencer and Supervisor System controller command errors Externally commanded faults Sequencing faults The board is populated with nineteen jumpers for selection of the LTC98 operation options and with twelve LEDs for displaying: The undervoltage status in the steady state CMP (D) CMP (D8) The LTC98 controlling outputs states EN (D) EN (D) The state signals of the pin (#6), the RST pin (#), the OV pin (#0), and the FLT pin (#9). Design files for this circuit board are available at L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. PERFORMANCE SUMMARY Specifications are at T A = C SYMBOL PARAMETER CDITIS MIN TYP MAX UNITS V CC V CC Input Supply Range V VHV CC HV CC Input Supply Range V V Threshold Voltage V Rising V V M(TH) Voltage Monitor Reset Threshold Voltage VSEL = V CC V V EN Enable Pin Voltage Output in State V CC +. V CC +. V CC + 6 V I EN(UP) Enable Pin Pull-Up Current Enable Pin, V EN V CC + V µa t STMR Sequence Timer Period, STMR C STMR = 0.0µF ms t PTMR Power Good Timer Period C PTMR =.µf s t RTMR Reset Timer C RTMR = 0.07μF ms V V V V TPV TPV TPV TPV V Internal and External Input V Internal and External Input V Internal and External Input V Internal and External Input V Time Position V Time Position V Time Position V Time Position V V V V dc09bf

2 DEMO MANUAL DC09B OPERATING PRINCIPLES A single LTC98 can control four positive supplies or three positive and one negative. Each supply timing position in the sequence can be any one of eight available time positions. Refer to the data sheet for the external resistor values for setting the sequence time position. Power is applied to the LTC98 through either the V CC pin (.9V to 6V) or the HV CC pin (7.V to 6.V). Each one of the four enable outputs (EN, EN, EN, EN) provides a (V CC +.V) signal to control a MOSFET gate or a power supply enable input. The LTC98 monitors four supply thresholds per supply (sequence-up, sequence-down, undervoltage, overvoltage) during a full LTC98 operation cycle. A full operation cycle includes two transient phases (sequence-up and sequence-down) and one monitor (steady state) phase. The time intervals between adjacent supplies enable or disable signal is set by the value of the sequence timer capacitor with a timing scale factor of 8670ms/µF. The sequencing-up interval is equal to the sequencing-down interval. The power good timer period defines the maximum time allowed by any input supply to reach its undervoltage threshold (in power-up) or drop to its sequencing-down threshold (in power-down). This period is set by a power good timer capacitor with a timing scale factor of 000ms/µF. During the sequence-up phase, supply monitor inputs are expected to cross their sequence-up threshold (which may be different from their undervoltage threshold). Any supply monitor input failing to cross its sequence-up threshold will stall the process and a sequence-up fault is generated. During the sequence-down phase, supply monitor inputs are expected to cross their sequence-down threshold (which can be different from their undervoltage threshold) within the selected power good time. Any supply monitor input failing to cross its sequence-down threshold will stall the process and generate a sequence-down fault. Refer to the LTC98 data sheet for sequencing threshold selection by biasing the SQT and SQT pins. dc09bf

3 DEMO MANUAL DC09B QUICK START PROCEDURE For fast evaluation of LTC98 performance, the board contains four low drop out regulators (LDO): LT76ES-., LT76ES-., LT76ES-.8, LT76ES-., and a push button with control circuitry for control signal generation. LDO outputs are +.V, +.V,.8V, and +.V. Each LDO has an enable input, and works as a power supply. Demonstration circuit 09B is easy to set up to evaluate the performance of the LTC98 with the on-board supplies. Refer to Figure for the proper circuit coection. For the load resistors R, R, R, and R use Ω W resistors. Coect four scope probes to the load resistors R, R, R, and R. Place jumpers in the following positions: JP (OPERATI) LAST JP () _ JP (V) JP (V) JP (V) JP6 (V) JP7 (SQT) JP8 (VSEL) ALL POSITIVE JP9 (RT Control) TIME POSITI JP0 (SQT) JP (V POLARITY) V_POS JP (MS) JP (RT Control) TIME POSITI JP (OVA CFIG) % JP (MS) JP6 (RT Control) TIME POSITI JP7 (V CC Select) LOW V CC JP8 (RDIS) OPEN JP9 (RT Control) TIME POSITI. With the +V power supply off, coect the supply to the V_AUX and turrets.. Turn the +V supply on and after that switch the control signal from low to high by pressing the button S.. The power-up output voltages should correlate with the transient shown in Figure (power-up phase). Acceptable tolerance in the sequence timing is ±0%.. Press the button PB (S) to change the signal from high to low and observe the output voltages. The power-down output voltages should correlate with the transient shown in Figure. (power-down phase). Acceptable tolerance in the sequence timing is ±0%.. Turn the +V power supply off and coect four external power supply terminals with DC09 as shown in Figure. Use external power supplies with output voltages +.V, +.V, +.8V, and +.V. Leave output loads as in previous experiments or replace them with W resistors.ω,.ω, Ω, and Ω accordingly to have current in each rail around A. 6. Change jumpers V (JP), V (JP), V (JP), and V (JP) positions from to EXT. 7. Turn-on all five power supplies. Pushing the button PB (S) changes the signal from low to high and after the power-up transient completes, press PB (S) a second time to initiate the power-down. The output voltage sequence timing should be similar to the timing with the internal power supplies. 8. The DC09B could be used for the original customer design. Based on the sequence timing and threshold parameters define all the optional components values, replace them on the board and verify design performance. Contact LTC Field Applications Engineers to get help in the designing or verifying your circuit with a special tool. dc09bf

4 DEMO MANUAL DC09B QUICK START PROCEDURE Figure. Demo Circuit 09 Coections for Operation with Internal Supplies dc09bf

5 DEMO MANUAL DC09B QUICK START PROCEDURE Figure. Demo Circuit 09 Coections for Operation with External Supplies dc09bf

6 DEMO MANUAL DC09B QUICK START PROCEDURE Figure. Power-Up and Power-Down Transients 6 dc09bf

7 DEMO MANUAL DC09B SCHEMATIC DIAGRAM REVISI HISTORY ECO REV DESCRIPTI APPROVED DATE B Replaced obsolete LED's Vlad Ostrerov Oct 0, 0 EN EN D D CMP CMP CMP CMP CMP CMP CMP CMP V V V V OVA OVA OVA U EN EN EN EN EN EN LTC98CUHF V 0 V V V V V EN 9 EN EN RTMR NC RTMR 8 REF PTMR REF REF PTMR 7 C C RT 6 STMR RT RT STMR 6 RT RT 7 RT VSEL VSEL VSEL RT 8 RT RT H C 0.0uF RT 9 RT RT H SQT 0 SQT SQT C.uF SQT SQT SQT RST# C uf C uf MS MS MS OV# 0 V V C MS RDIS CAS NC DE# FLT# V EN CMP CMP CMP CMP V uF MS RST# RST# MS RDIS RDIS OV# OV# FLT# FLT# B B E CAS CAS E DE# LAST NOT LAST JP OPERATI R.K CUSTOMER NOTICE APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIS; A TECHNOLOGY HOWEVER, IT REMAINS THE CUSTOMER'S RESPSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATI IN THE ACTUAL APPLICATI. COMPENT SUBSTITUTI AND PRED APP ENG. TITLE: CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT Vlad Ostrerov SCHEMATIC PERFORMANCE OR RELIABILITY. CTACT LINEAR TECHNOLOGY APPLICATIS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NE SIZE MODIFY DATE: IC NO. REV. SHEET OF dc09bf 7

8 DEMO MANUAL DC09B SCHEMATIC DIAGRAM V_AUX V_AUX EN EN EN D D EN R R R R R6 R7 R8 R9 EN EN EN EN CMP CMP D D D D CMP CMP EN EN EN EN D D6 D7 D8 YEL YEL YEL YEL CMP CMP CMP CMP CMP ORN ORN ORN ORN CMP CMP CMP EN Q Q Q Q Q Q6 Q7 Q8 RST# N700 EN N700 EN N700 EN N700 CMP N700 CMP N700 CMP N700 CMP N700 OV# RST# OV# FLT# FLT# C C R 00 R.K R.K V_AUX R.K C6 0.uF S PB U LTC90CTS8- VIN PB KILL EN/EN 6 8 R9 0K R0 0K JP _ EXT_ 7 T OFFT D9 GRN D0 RESET RED D OVERVOLTAGE RED E Q9 N700 E RST# E6 OV# E7 FLT# B B RESET OVERVOLTAGE FAULT D FAULT RED C7 700pF C8 700pF E APPROVALS TECHNOLOGY A A PCB DES. Vlad Ostrerov TITLE: SCHEMATIC APP ENG. SIZE IC NO. REV. SCALE = NE MODIFY DATE: SHEET OF 8 dc09bf

9 DEMO MANUAL DC09B SCHEMATIC DIAGRAM V_ V_ JP JP V V D D E0 EN EN EN C9 TBD R 00 E8 V_FET E V_M V_FET Q0 IRL70ZSPBF EN EN R6 00 V_M R7 V V_M R8 V V V 8K % R0 9.9K % V_POL EXT V_POL E EN C0 TBD E9 V_FET E V_M V_FET Q IRL70ZSPBF 8K % R9 9.9K % EXT C C E6 EN EN EN C TBD R 00 E V_FET E8 V_M V_FET Q IRL70ZSPBF V_M R 88.7K % V R 9.9K % V_ JP V V EXT B B E7 EN EN EN C TBD R 00 E V_FET E9 V_M V_FET Q IRL70ZSPBF V_M R 6K % V R6 9.9K % V_ JP6 V V EXT APPROVALS TECHNOLOGY A A PCB DES. Vlad Ostrerov TITLE: SCHEMATIC APP ENG. SIZE IC NO. REV. SCALE = NE MODIFY DATE: SHEET OF dc09bf 9

10 DEMO MANUAL DC09B SCHEMATIC DIAGRAM JP7 SQT JP8 VSEL V_NEG SQT SQT OPEN VSEL VSEL D D ALL POSITIVE RT RT V_POL V REF V_POL V REF JP9 RT CTROL R7 JP0 9.K FORCE SQT % TIME POSITI FORCE OFF R8 TBD JP V_POLARITY V_POS V_NEG SQT SQT OPEN FORCE JP C C OVA CFIG ABOVE UV MS OPEN OVA MS RT TIME POSITI OVA >% RT R_ FORCE OFF % FORCE H RT TIME POSITI R RT FORCE OFF.K B B JP7 Select JP8 VIN H H(8V to 6.V) RDIS E0 IN LOW Vcc:.9V-6V HVcc:8V-6.V LOW LOW (.9V to 6V) RDIS OPEN RDIS RT R0.K % R 9.K % R.0K % RT JP RT CTROL JP6 RT CTROL JP9 RT CTROL FORCE TIME POSITI FORCE OFF MS MS R_ R9 (Opt) R (Opt) 6 <% JP MS JP MS OPEN APPROVALS TECHNOLOGY A A PCB DES. Vlad Ostrerov TITLE: SCHEMATIC APP ENG. SIZE IC NO. REV. SCALE = NE MODIFY DATE: SHEET OF 0 dc09bf

11 DEMO MANUAL DC09B SCHEMATIC DIAGRAM D D V_AUX E V_AUX LOCAL BOARD JP0 SUPPLIES SELECTI EXTERNAL C 0uF 6.V R 0K U LT76ES-. IN C 0.0uF E V_ V_ V_ V_ IN OUT C 0uF 6.V C9 0uF 6.V U LT76ES-.8 BYP C 0uF 6.V V_ C SHDN. SHDN.8 C E8 U LT76ES-. E6 V_ E7 V_ R6 0K IN BYP V_ V_ V_ IN OUT C 0uF 6.V R8 0K V_ SHDN OUT C 0.0uF E E9 B SHDN. SHDN. B SHDN C0 0.0uF E U6 LT76ES-. C7 0.0uF C8 0uF 6.V BYP C 0uF 6.V SHDN OUT BYP R7 0K E V_ C6 0uF 6.V SHDN E0 E E E E APPROVALS TECHNOLOGY A A PCB DES. Vlad Ostrerov TITLE: SCHEMATIC APP ENG. SIZE IC NO. REV. SCALE = NE MODIFY DATE: SHEET OF Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the intercoection of its circuits as described herein will not infringe on existing patent rights. dc09bf

12 DEMO MANUAL DC09B DEMSTRATI BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATI PURPOSES LY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 0 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 60 McCarthy Blvd. Milpitas, CA 90 Copyright 00, Linear Technology Corporation dc09bf LT PRED IN USA Linear Technology Corporation 60 McCarthy Blvd., Milpitas, CA (08) -900 FAX: (08) LINEAR TECHNOLOGY CORPORATI 0