Using DDS Aliases to Extend the Frequency Range

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1 Using DDS Aliases to Extend the Frequency Range Sam Wetterlin 4/7/07 A DDS is typically used to generate a fundamental frequency to about 1/3 of the clock frequency. The DDS also generates well defined aliases at higher frequencies, but those are usually filtered out. But it is possible to make use of them. This is exactly what was done by Professor Baier, DQ8SAQ, in his vector network analyzer, described at and also published in QEX, March/April, The beauty of his approach is that we can make use of desired aliases without having to filter out the undesired aliases. The purpose of this paper is to refine that idea to achieve high frequency coverage with no dead spots in the coverage. If the fundamental is F Fund and the clock frequency is F Clk, then F Fund is by definition at most F Clk /2 and the aliases will appear at N*F Clk ± F Fund, where N is an integer. As a practical matter N has useable values from 1 to perhaps 3. Thus, for example, a 100 MHz fundamental with a 400 MHz clock will be accompanied by aliases at 300 MHz, 500 MHz, 700 MHz, 900 MHz, 1100 MHz and 1300 MHz. The problem with aliases is that the output level declines with frequency according to a well defined rule. The envelope of the DDS output, showing the relative amplitude of the fundamental and aliases as a function of frequency, follows a curve equal to the absolute value of sinc(pi*output_frequency/clock_frequency). [Sinc(x)=(sin x)/x] Figure 1 shows the envelope for a DDS using alternative clock frequencies of 260, 320, and 400 MHz, and a red line indicating the maximum of the three separate graphs.

2 Combined Alias Envelope Relative Magnitude MHz 320 MHz 400 MHz Max Series4 Series5 Series Figure 1 Alias Envelopes with Different Clock Frequencies The blue, yellow and green lines show different clocks. The red line shows the maximum output level achievable by using the best clock at each frequency. Look first at the 400 MHz line (green). The output drops to very low levels around the clock frequency and integer multiples of that frequency. If we tried to make use of an alias at 380 MHz (by using a fundamental of 20 MHz), the output level would be extremely low. But each curve has a different point where the output vanishes. If at any frequency we choose the best of the three curves, we can achieve the output level represented by the red line, which is the maximum of the other three. For example, to generate a 380 MHz alias, we would be best off using the 260 MHz clock with a fundamental of 120 MHz (380= ). To achieve the output level of the red line in Figure 1, we use a 400 MHz clock to about 325 MHz output, then switch to the 260 MHz clock until we reach 400 MHz output, then switch to a 320 MHz clock up to output of 500 MHz. 2

3 While shifting clock frequencies may sound complex, it is very easy with a DDS that uses a low frequency primary clock and has a selectable multiplier. With a 20 MHz primary clock, and a selectable multiplier up to 20, we can achieve the necessary clocks with multipliers of 13, 16 and 20. Figure 2 converts the output level to db and shows only the combined maximum envelope. Combined Envelope as DB 260/320/400 MHz Clocks 0-5 Relative Magnitude (DB) Figure 2 Combined Envelope of Figure 1 Expressed in db. The achievable output almost never falls more than 20 db below the maximum output all the way to 1 GHz. Note that while the alias output generally decreases with frequency, the spur output does not. That means that if the best spurious free level is -55 dbc (typical of a DDS with a 10-bit DAC), then the spur level with the envelope reduced 20 db is only -35 dbc. Depending on the application, this may be workable, or may require that we move to a 14-bit DAC, such as the AD9951. If the DDS output is used as a test signal to stimulate a DUT, and we use a similar signal (perhaps offset by a few khz) as the LO to detect the DUT 3

4 response, we want the LO signal to match the RF signal only at the desired test frequency. ( Match meaning to be offset by the desired IF.) Therefore, we want only the desired aliases of the two signals to match. This means we need the LO to be generated by a DDS with a slightly different clock frequency. Figures 3 and 4 show the output envelope of a DDS using the same frequencies as Figures 1 and 2, but each reduced by 20 MHz. If the DDS uses an internal multiplier with a 20 MHz primary clock, reducing each multiplier by one accomplishes the necessary clock changes. Combined Alias Envelope Relative Magnitude MHz 300 MHz 380 MHz Max Series4 Series5 Series Figure 3 Envelopes with each clock reduced by 20 MHz Comparing this graph to Figure 1 shows that it is feasible to have two slightly offset clocks for two separate DDS s, without a major change in output level. The optimum points at which to switch clocks does change slightly. 4

5 Combined Envelope as DB 240/300/380 MHz Clocks 0-5 Relative Magnitude (DB) Figure 4 Maximum Envelopes of Figure 3 Expressed as db We have established that we can generate two signals with the desired outputs using two separate DDS s with different clock speeds. Both DDS s will operate off the same primary clock, which should eliminate the need to coordinate them through a PLL as was done by DQ8SAQ using the AD9851, which has a clock multiplier with only two possible values, x1 and x6, and so does not work for our purposes. In general this means that if their desired aliases have the desired IF offset from one another, their other aliases are not likely to do so. However, there are so many possible combinations of fundamentals and aliases that we need to verify that there is no situation where the IF can be generated by combinations of the output signals other than the desired combination. DQ8SAQ confirmed that for his circuit, problems existed only at half-clock multiples. Figures 1 and 3 show orange dots at those multiples. Wherever such a dot falls on the red line envelope, it would be necessary to use a non-optimum clock, which can be found by dropping down to the level of the next-best clock. Of course, we could also use a fourth clock value if necessary to improve the drop-down value, as might be required for example at 750 MHz in Figure 3. 5