A Multilevel PWM Inverter Topology for Photovoltaic Applications

Transcription

1 A Multilevel PWM Inverter Topology for Photovoltaic Applications V.G. Agelidis D.M. Baker W.B. Lawrance C. V. Nayar Centre for Renewable Energy Systems Technology Australia (CRESTA) School of Electrical & Computer Engineering Curtin University of Technology GPO Box U1987, Perth, WA, 6001 AUSTRALIA Abstract - A multilevel pulse-width modulated (PWM) singlephase voltage-source inverter topology for photovoltaic applications is discussed in this paper. The use of the phase opposition (PO) carrier disposition multicarrier PWM switching technique for this topology is presented. Inverter switch control signals are derived. A 5-level and a 3-level PWM voltage waveform across the load is generated, for high and low modulation indexes respectively. Performance characteristics including total harmonic distortion for a range of operating conditions of the inverter are provided. Theoretical considerations discussed in this paper are supported with simulation and experimental results taken from a low power laboratory prototype. I. INTRODUCTION Solar technology in the form of photovoltaic based inverter controlled remote area power supplies is utilised extensively when extension of the electricity grid is not economically feasible [ 11. Appropriate voltage control methods adjusted for the various inverter topologies are used for systems that are not connected to the grid [2]. Improving the output waveform of the inverter reduces its respective harmonic content, and hence the size of the filter used and the level of the electromagnetic interference (EM) gcnerated by the switching operation of the converter. Typically two or three level waveforms are produced [2]. Multilevel technology promises a number of advantages over the conventional technology especially for high power applications [3-81. Such methods however are easily applicable in medium and low power applications [9] and a number of them suit the PV applications [ Several advantages of multilevel inverters over conventional ones include an improved output waveform, since the multilevel signal approaches the sinusoidal signal closer than the three-level signal, smaller filter size, lower switching losses, lower EM1 and lower acoustic noise. Various multilevel switching techniques have been investigated and presented within the technical literature with their respective characteristics and advantages theoretically discussed [ 121. However, regardless of the switching technique chosen, the gating signals to suit a particular inverter topology must be derived as it is not a straightforward approach. The objective of this paper is to report the application of a multicarrier PWM technique [12] to a single-phase multilevel inverter topology [ 111. The PWM technique is the phase opposition (PO) carrier disposition method which uses several triangular carriers disposed in contiguous bands, with each carrier displaced by Fig. 1: The power circuit of the multilevel inverter for photovoltaic applications. increments of the reference waveform amplitude [ 121. The inverter topology is suitalble for PV applications because the separate voltage sources required suit the use of solar arrays. The paper is organised in the following way. Section I1 presents the power iinverter topology capable of synthesising multilevel PWM waveforms across the load. Section I11 introduces a switching technique suitable for the multilevel topology. In Section IV, the control signals for the inverter switches are derived. Simulation results for the inverter system under consideration and experimental results taken from a low-power laboratory prototype are provided and discussed in Sections V and VI respectively. Finally, conclusions are made in Section VII. 11. SYSTEM DESCRIPTION The power circuit of the multilevel inverter topology under consideration is shown in Fig. 1. It is constructed by adding a bi-directional switch to the conventional bridge topology. The bi-direction(a1 switch controls current flow to and from the neutral point of the two separate DC voltage sources and is composed of the two switches Sop and So,,. The inverter power circuit, with the appropriate control used, can apply across the load five different voltage levels, namely 2E, E, 0, -E, -2E. Switches SI, S2, S3,!j.4 have a voltage rating of 2E which is the DC bus voltage (Fig. 1). Switches Sop and So, have a voltage rating of E which is half the DC bus voltage. As a consequence these two switches would be of a lower cost than switches S, through S4. The antiparallel diodes across, the switches allow continuous current flow and thus help to maintain a sinusoidal output current. Furthermore, thr: bidirectional switch could be built with the two switches Sop and So, connected simply in series and not in parallel?with the extra blocking diodes as shown in Fig. 1. IEEE Catalog Number: 97TH ISIE'97 - Guimarks, Portugal

2 Fig. 2 : Multilevel inverter switching modes with respect to the per unit (pu) amplitude of the output signal. HighLevel 11 2E I E o* -E ~ow~evel 11 E 0 I -E I -2E 2n ModeII: 0<0i<#~ and #2<~t27r (2) ModeIII: 7 c < ~ t < # ~ and # 4 < ~ t 1 2 ~ (3) Mode IV: #3 <at <-#4 (4) In order to control the inverter, a multicarrier disposition PWM technique is used. Multicarrier disposition PWM techniques recently presented in [ 121 entail the natural sampling of a single modulating or reference waveform typically being sinusoidal, through several carrier signals typically being triangular. For an n- level system, that is to produce a phase voltage waveform with n-1 levels plus the zero, n-i carrier signals are required. They all have the same frequency and peak-peak amplitude, and each structured such that all carriers are contiguous. In general, the phase displacement between any two of the contiguous triangular carriers is free, therefore a number of combinations can be studied as follows: 1. The carriers are alternatively in opposition (APO disposition). 2. All the carriers above the zero value reference are in phase but in opposition with those below (PO ~~ Table 1: Multilevel inverter modes of operation and voltage levels of the disposition). inverter unfiltered output voltage signal across the load. 3. All the carriers are in phase (PH disposition). Additional combinations of carrier phase displacement are possible for the 5-level model, however the minor differences evident between these and the aforementioned techniques selected for investigation would result in similar output waveform characteristics. The multilevel phase opposition (PO) multicarrier disposition method (Fig. 3) was used to derive the switch gating signals for the multilevel inverter under consideration (Fig. 1). The exchanging phase angles can be shown to be Table 2: Multilevel inverter switch states and state of the inverter unfiltered dependant the amp1itude index Or output voltage signal across the load. modulation index, MO, as in Fig. 4. For the 5-level PO disposition PWM technique then, the amplitude modulation index as defined as follows: 111. A MULTILEVEL PWM TECHNIQUE During One cycle of the output frequency of 50 Hz the inverter operates through four modes. These operational modes are shown in Fig. 2 with respect to the per unit (PU) output voltage signal. Each of these operational modes has a high level and a low level as shown in Table 1. The five output voltage levels are obtained by the switch combinations shown in Table 2. From Table 1 and Table 2, the voltage levels 0 and O* are the same value. However, for commutation purposes the switch configuration is different for the zero voltage level in the first half cycle of the output voltage to that in the second half cycle. As can be seen from Fig. 2, the interval of each mode 4 Ma =- 2AC where A, is the per unit (pu) carrier (triangular) peak-peak value and A, is the (pu) peak value of the modulating (sinusoidal) signal. Furthermore, the frequency modulation index is defined as: Mf =- so fc (6) wheref, is the frequency of the carrier (triangular) signal a d fo is the frequency of the modulating (sinusoidal) Whilst A, ~ A,, or equivalently when the amplitude modulation index is greater than 0.5, the exchanging phase angles are defined by: varies with the amplitude of the required output sinusoid. = sin -1 (Am] A, (7) The phase angles of mode change h, h, h and & determine also the time that the inverter operates within a 42 = 7c - 41 (8) certain mode. For clarity purposes and referring to Fig. 2, 43 = K++l (9) the four modes fall within the following boundaries: #4 =2fl-41 (10) Mode I: 41 < ~t s 42 (1) IEEE Catalog Number: 97THS ISIE 97 - Guimarbs, Portugal

3 For A, SA^, or equivalently when the amplitude modulation index is less than 0.5, the exchanging phase angles are equal to n 41 = 42 'T 3n 43 =44 =1 The variation in the mode exchange angles with the modulation index are shown in Fig. 4. Therefore for the modulation index less than 0.5 the inverter does not operate in either Mode I or Mode IV and as such produces only a three level output as shown in Fig. 10. During the first half cycle of the output voltage and assuming that the modulation index is greater than 0.5, the inverter produces three output levels namely 0, E and 2E. During the second half cycle the inverter produces another three voltage levels namely 0*, -E and -2E. As can be seen from Table 2 switch Sz is OFF during the first half cycle and ON for the second half cycle. Conversely switch S4 is ON for the first half cycle and OFF for the second half cycle. Therefore the switching frequency of switches S, and S4 is equal to the output frequency of 50 Hz and thus low frequency switches such as BJTs can be used. Also the switching function for Sz is opposite to that for S4. Table 2 also shows that the switching function for Sop is opposite to that for SI and the switching function for So, is opposite to that for S3. That is, whenever switch Sop is ON, switch SI is OFF and whenever switch So, is ON, switch S3 is OFF and vice versa. In order to operate the inverter then, the switch gating signals need to be derived. However due to the above relationships only three gating signals need to be found with these being the ones for switches Sop, So, and SZ. The gating signals for switches SI, S3 and S4 are simply the logical inverse of the gating signals for switches Sop, So, and S2 respectively. IV. CONTROL SIGNALS For illustrative purposes only, the PO carrier disposition PWM technique (Fig. 3) with a carrier frequencyf, of 1800 Hz was used. The frequency of the modulating signal was chosen to be 50 Hz. The frequency modulation index is then M~36. For this carrier disposition PWM technique as mentioned earlier, the carrier signals above zero are all in phase and out of phase with all carriers below zero. This is shown in Fig. 3. The unfiltered output voltage waveform across the load using the multilevel inverter shown in Fig. 1 then results in that of Fig. 5 when M,=0.8. From Table 2 the switch gating signals can be derived to match the output voltage level given in Fig. 5. The construction of these switch gating signals from the switching state table is shown in Fig. 6. At a particular instant in time, if the load voltage is 0 then switches Son, SI and S, are OFF and switches Sop, S3 and S4 are ON. If the load voltage is 2E then switches Sop, S2 and S3 are OFF and switches So,, SI and S, are ON. This process is followed for the whole cycle of the output waveform. Now that the switching technique and carrier frequency have been set, the derivatiion of the gating signals in the physical inverter control needs be explained. The gating signals are constructed by adding portions of the PWM decision signals together through appropriate logic gates. The PWM decision signals, as explained in Section 111, are derived from the intersectlions between the carrier signals and the modulating signal. The decision signals for the PO disposition method are given in Fig 8, and this shows the decision signals only occurring during those time intervals where the modulating signal intersects with the respective carrier signal. From Fig. 8 and referring to Fig. 3, C1 represents carrier 1 and modulating signal intersections; C2 represents carrier2 and modulating signal intersections; C3 represents carrier3 and modulating signal intersections and C, represents carrier4 and modulating signal intersections. The switch gating signals are made up of portions of these signals. There are six regions that make up one cycle of the output and these are defiined in Fig. 9. The regions are given by the mode exchange phase angles qh, &, & and b4 defined in section I11 and Fig. 9. Thus the six regions are as follows: (i) 0 < time 5 Qll, (ii) < time 5 42, (iii) (z < time s A-, (iv) n < tjme I 43, (v) 43 < time I 44, (vi) b4 < time < 2a and are shown in Fig. 9. Having the PWM decision signals of Fig. 9 and the output region pulses of Fig. 8 it is now possible to define the switching signal for each switch. The Boolean expressions that follow would be implement by the use of logical AND and OR gales. The switching functions of Fig. 6 are then given by Sop =RI +R2 *Cl +R3 +R4 *C3 +R, +& *C3 (13) So, = RI C2 + R2 +R3 C2 -I R4 +Rs C4 +& (14) s, =Top (15) S2 = R4 +R, +& (16) s3 = so, (17) S4 =Rl+R;!+R3 (18) where " + I' is a logical OR., " 0 I' is a logical AND and I' - 'I is a logical inverse or NOT. When constructing the physical circuit the signals C1, C, C3 and C4 come from comparators which compare the respective carrier signal and the modulating signal; the signals RI, R2, R3, R4, Rs and R6 come from a memory device (EPROM) which varies the pulse duration according to eqns. (7), (8)i (9) and (10). These signals are then passed through appropriate logic gates as defined by the above equations. For an amplitude modlulation index less than 0.5, the duration of the R2 and h!~ signals is zero. However the above logic still produces the appropriate switch gating signals to produce the required output. Since the amplitude modulation index is less than 0.5, the multilevel output IEEE Catalog Number: 97TH ISIE'97 - GuimarLs, Portugal

4 0..2 Fig. 3: The multicamier phase opposition (PO) disposition PWM technique for M, = 0.8, A Fig. 7: Frequency spectra of the inverter unfiltered output voltage across the load vs. modulation index, Mu for the multicanier phase opposition disposition PWM technique and form - 36, fo= 50 Hz.. L.3 3 I i... P ---- C c2 c3 niu I 'B ua I 0 I I I 1 I I I I, t Modulation Index, Ma Fig. 4 : Variation in mode exchange angles VS. modulation index, Ma Time (ms) Fig. 8: Decision signals of the multicarrier phase opposition disposition PWM technique and form, = O.S,Mf= 36, fo= 50 Hz.. RI R Thc ("6) Fig. 5: Inverter output voltage waveform (5-level) with multicarrier phase opposition disposition PWM technique for Mu = 0.8,M - 36, fo= 50 Hz. R6 I 0 41 P n 43 c Fig. 9: Output regions for gating signals whenmu > s3 ni s io 15 Time (ms) 20 Fig. 6: Inverter switch gating signals for multicarrier phase opposition disposition PWM technique form, = 0.8, Mf= 36,fo = 50 Hz. Fig. 10: Inverter output voltage waveform (3-level) with multicarrier phase opposition disposition PWM technique for M, = 0.4,M - 36, fo = 50 Hz. IEEE Catalog Number: 97THSZ ISIE'97 - GuimarHes, Portugal

5 2 1 SZ 2 s4 0 5 IO I5 20 Time (ms) Fig. 11: Inverter switch gating signals for the multicarrier phase opposition disposition PWM technique, andm, =0.4,Mf= 36, A= 50 Hz.. DF2 reduces to three level as explained in section I11 and shown in Fig. 10. The corresponding switch gating signals for M,=0.4 and M ~36 are shown in Fig. 11. V. SIMULATION RESULTS The multilevel inverter was simulated for the parameters previously discussed. The results are presented in Figs. 5 and 10 for modulation index of 0.8 and 0.4 respectively. It is revealed that the inverter produces a voltage output signal that has a different number of levels depending upon the modulation index. The performance of the inverter with the multilevel PWM technique used was evaluated for various values of the amplitude modulation inidex. The second-order distorlion factor is chosen because it reflects the amount of harmonic distortion that remains in a particular waveform x($) after ithe signal has been subjected to a second-order filter, and it is defined as follows: m %DF2 = y n=2,3... The calculated values of the distortion factor as a function of the modulation index are plotted in Fig MU Fig. 12: Distortion factor DF2 for second-order filtering for the multilevel inverter with the multicarrier phase opposition disposition PWM technique vs. modulation index and form - 36,f,= 50 Hz. VI. EXPERIMENTAL RESULTS The multilevel inverter under consideration was built and tested in the laboratory. The phase opposition disposition PWM technique was used to control the inverter. The carrier frequeincy was chosen to be 1800 Hz. The inverter output voltage is shown in Figs. 13 and 14 for modulation index of 0.8 and 0.4 respectively. Comparison of Figs. 5 and 13 and Figs. 10 and 14 reveals that the simulation and experimental results are in close agreement. Furthermore, the load current waveform for an inductive load is shown for the two modulation indexes of 0.8 and 0.4 in Figs. 13 and 14 respectively. I.I Fig. 13: Experimental results - Inverter voltage waveform for Ma=0.8, A4-36 and current waveform for inductive passive load. f VII. CONCLUSION The principles of operation of a multilevel (5-level) PWM single-phase inverter topology suitable for photovoltaic applications have been presented in this paper. A phase-opposition (PO) carrier disposition PWM technique has been used along with the appropriate logic circuit to derive the inverter switch gating signals. The inverter generates a 5-level output waveform for modulation indexes above 0.5 and a 3-level output waveform for modulation indexes below 0.5. Theoretical considerations have been verified by simulation and experimentally on a low-power laboratory prototype. VIII. ACKNOWLEDGEMENT Fig. 14: Experimental results - Inverter voltage waveform for Ma=0.4, M -36 and current waveform for inductive passive load. f The authors want to express their appreciation to Mr. Daniel Taylor for his assistance with the generation of simulated waveforms and graphics. IEEE Catalog Number: 97TH ISIE 97 - Guimar&s, Portugal

6 X. REFERENCES R. Haas "The Value of Photovoltaic Electricity for Society" Solar Energy, Vol. 54 No. 1, 1995, pp Bose B.K., Szczesny P.M., Steigerwald R.L. "Microcomputer Control of a Residential Photovoltaic Power Conditioning 'System", in IEEE Trans. on Industry Applications, Vol. IA-21, No.5, 1985 pp Bhagwat P.M., Stefanovic V.R., "Generalised Structure of a Multilevel PWM Inverter". IEEE Trans. on Industry Applications, Vol. IA-19 No.6, 1983, pp Choi N.S., Cho J.G., Cho G.H., "A General Circuit Topology of Multilevel Inverter", in IEEE Trans. on Power Electronics, Vol. 6, 1991, pp Meynard T.A., Foch H., "Multi-Level Conversion: High Voltage Choppers and Voltage Source Inverters" in IEEE Trans. on Power Electronics, 3, 1992, pp Nabae A., Takahashi I., Akagi H., "A New Neutral- Point-Clamped PWM Inverter". IEEE Trans. on Industry Applications, Vol. IA-17 No.5, 1981, pp Liu H.L., Cho G.H., Park S.S., "Optimal PWM Design for High Power Three-Level Inverter Through Comparative Studies", in IEEE Trans. on Power Electronics, Vol. 10 No. 1, 1995, pp 38-47, [SI Maruyama T., Kumano M., Ashiya M., "A New Asynchronous PWM Method for a Three-Level Inverter", in Con$ Rec. IEEE PESC 1991, pp [9] Lai R., Ngo K.D.T., "A PWM Method for Reduction of Switching Loss in a Full-Bridge Inverter", in IEEE Trans. on Power Electronics, Vol. 10 No. 3, 1995, pp [IO] Ohsato M.H., Inarida S., et al., "Characteristics of Resonant Type Five-Level PWM Inverter Used in Small-Scaled Photovoltaic Systems", in Con$ Rec. IEEE PESC 1992, pp [ll] Hinga P.K., Ohnishi T., Suzuki T. "A New PWM Inverter for Photovoltaic Power Generation System", in Con$ Rec. IEEE PESC 1994, pp [12] Carrara G, Gardella S, et al., "A New Multilevel PWM Method: A Theoretical Analysis". IEEE Trans. on Power Electronics, Vol. 7 No. 3, 1992, pp IEEE Catalog Number: 97TH ISIE'97 - Guimariies, Portugal