Not for New Design A6271. Automotive, High-Current LED Controller. Recommended Substitutions: A6271-1

Transcription

1 Not for New Design These parts are in production but have been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Date of status change: December 14, 2017 Recommended Substitutions: A NOTE: For detailed information on purchasing options, contact your local Allegro field applications engineer or sales representative. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information included herein is believed to be accurate and reliable. However, assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

2 Features and Benefits Automotive AEC-Q100 qualified Constant-current LED drive 4.2 to 50 V supply 53.3 V maximum LED string voltage Boost, buck-boost, and buck switching converters Programmable switching frequency 70 to 700 khz PWM-controlled PMOS driver allows accurate LED current control at low duty cycles Dimming via external PWM, internal PWM and/or analog dimming Frequency dither scheme for effective spread spectrum to reduce EMI Comprehensive fault protection and fault flag Package: 16-Pin etssop (LP) with Exposed Thermal Pad Description The A6271 is a DC-DC converter controller, providing a programmable constant-current output for driving high-power LEDs in series. The controller is based on a programmable fixed-frequency, peak current-mode control architecture. The DC-DC converter can be configured in a myriad of different switching configurations including boost, buck-boost, and buck (ground-referenced switch). The A6271 provides a cost-effective solution using an external logic-level MOSFET and minimum additional external components. The maximum LED current is set with a single external sense resistor and can be accurately modulated using a current reference input (analog control). External PWM dimming is possible via the PWMIN input, which also provides a shutdown mode. As an alternative, an internal PWM dimming circuit can be used by programming the PWMIN and DR pins. Either PWM scheme controls the PWMOUT output which drives an external p-channel MOSFET connected in series with the LED string. This MOSFET is also used to isolate the load during certain fault conditions, including output shorts to ground. Continued on next page... Not to scale APPLICATIONS Automotive high-power LED lighting systems Fog lights, reversing lights, daytime running lights, position lights, headlights L1 56 µh VBAT D2 C1 C2 C7 47 nf R5 150 Ω R Ω R1 2.7 kω C3 1 µf VREG GND VIN LP LN PWMOUT M2 PWM Control FAULTn DR PWMIN A6271 IREF OSC DITH COMP OVUV SG SP R8 12 Ω R9 1.3 kω M1 R7 4.3 kω C8 4.4 µf R kω LED1 LED14 C4 22 nf R kω R3 110 kω R4 39 Ω C5 680 nf C6 22 pf R10 75 mω GND Boost Switcher Driving 14 LEDs at 150 ma A6271-DS, Rev. 6 MCO January 4, 2018

3 Description (continued) The A6271 has been carefully designed to minimize electromagnetic emissions through distributed decoupling and an externally programmable frequency dither circuit configured for the EMI specification CISPR 25. It is also possible to program the fundamental switching frequency below 150 khz where most EMI standards begin. The A6271 has a comprehensive set of integrated protection features to protect the IC, the LED driver system, and the LED string against faults. Fixed-output overvoltage protection ensures no maximum voltage rating violations, even under a single point failure of the programmable-output overvoltage protection circuit. Other protection features include: LED overload (boost), output undervoltage (buck or buck-boost), input supply (VIN) undervoltage, 5 V regulator (VREG) output undervoltage, high-side supply (PWM PMOS) undervoltage, and thermal protection. Specifications Selection Guide Part Number Packing [1] Package A6271KLPTR-T 4000 pieces per 13-in. reel 16-pin TSSOP with exposed thermal pad [1] Contact Allegro for additional packing options. Absolute Maximum Ratings [2] Characteristic Symbol Notes Rating Unit VIN V IN 0.3 to 55 V PWMOUT, LP, LN, OVUV 0.3 to 58 V OSC, DITH, COMP, FAULTn, SG, SP, IREF, PWMIN, DR, VREG 0.3 to 6.5 V LP V LP With respect to LN 0.5 to 0.5 V Maximum Continuous Junction Temperature T J (max) 150 C Storage Temperature Range T stg 55 to 150 C [2] With respect to GND. Thermal Characteristics Characteristic Symbol Test Conditions [3] Value Unit etssop Package 4-layer PCB based on JEDEC standard 34 C/W R θja 2-layer PCB with 3.8in 2 of copper area each side 43 C/W R θjc Junction to thermal pad 2 C/W [3] Additional thermal information available on the Allegro website. 2

4 Pinout Diagram and Terminal List Table COMP 1 16 VIN IREF FAULTn LP LN OSC DITH 4 5 PAD PWMOUT OVUV DR 6 11 GND PWMIN 7 10 SP VREG 8 9 SG Package LP, 16-Pin etssop Pinout Diagram Terminal List Table Symbol Number Function COMP 1 Compensation pin for output of GM error amplifier. IREF 2 Analog dimming input. With a capacitor connected to this pin, provides a soft-start period when coming out of sleep mode. FAULTn 3 Open drain. Logic low indicates detection of a fault. Faults include: LED overload (boost), output undervoltage (buck or buck-boost), output overvoltage, programmable overvoltage, input supply (VIN) undervoltage, 5 V Regulator (VREG) output undervoltage. OSC 4 Oscillator input for setting switching frequency and for external synchronization. DITH 5 Dither frequency range set. Connect resistor from this pin to GND. Connect to VREG if not used. DR 6 A voltage applied to this pin programs the duty cycle of PWM internal mode. PWMIN 7 Used for either putting the device into sleep mode or analog dimming control. Can also be used for external or internal PWM control. VREG 8 5 V regulator output. Connect filter capacitor from VREG to GND. SG 9 Switch gate drive output. SP 10 Switch current sense and slope compensation. GND 11 Ground. OVUV 12 Programmable-output overvoltage and undervoltage protection input. PWMOUT 13 PWM gate drive for external p-channel MOSFET (active low). LN 14 LED current sense -ve. LP 15 LED current sense +ve. VIN 16 Main supply. PAD Exposed pad of both packages provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the ground plane preferably by multiple through-hole vias. 3

5 + A6271 R SL VBAT VIN OVUV PWMOUT LN LP VREG 5 V Linear Reg + CD Prog Output OV + CA 8 V wrt LP AA + Output OV CB + VREG FAULTn Internal Linear Reg + + CE Output UV Overload PWM Fault Block VIN UVLO VREG UVLO Prog Output OV Output OV Thermal IREF Analog DIM/ Soft Start + AB + CF R Q S SG PWMIN CG + PWM Osc AC + Dither SP GND R SLOPE R SS DR Internal PWM Generator COMP OSC DITH PWM On/Off Functional Block Diagram 4

6 ELECTRICAL CHARACTERISTICS: Valid at T J = 40 C to 150 C, V IN = 5 to 45 V, unless noted otherwise. Supply and Reference Characteristics Symbol Test Conditions Min. Typ. Max. Unit V Functional Operating Range [2] V hysteresis cleared; PWMOUT undervoltage turnon V VIN undervoltage turn off plus VIN undervoltage IN IN cleared V IN Quiescent Current I INQ SG Open Circuit ma I INS PWMIN = GND > disable time 6 20 µa I REG = 0 to 2 ma, V IN 5.3 V V VREG Output Voltage V REG I REG = 2 ma, V IN = 5 V 4.65 V VREG Output Voltage [3] V REG I REG = 2 ma, V IN = 9 to 45 V, T J = 40 C to 125 C V VREG Current Limit I REGCL 25 ma Gate Output Drive Turn-On Time t r C LOAD = 1 nf, 20% to 80% 30 ns Turn-Off Time t f C LOAD = 1 nf, 80% to 20% 30 ns Minimum Off-Time t off(min) ns T J = 25 C, I GHx = 100 ma 1.7 Ω Pull-Up On-Resistance R DS(on)UP T J = 150 C, I GHx = 100 ma 3.6 Ω T J = 25 C, I GLx = 100 ma 0.75 Ω Pull-Down On-Resistance R DS(on)DN T J = 150 C, I GLx = 100 ma 2 Ω V Output High Voltage V SGH I SG = 100 µa REG 0.1 V REG V Output Low Voltage V SGL I SG = 100 µa 0.1 V Logic Inputs and Outputs FAULTn Output (Open Drain) V OL I OL = 1 ma, fault asserted 0.4 V FAULTn Output Leakage Current [1] I OH V O = 5.5 V, fault not asserted 1 1 µa PWMIN Low Voltage V PWMINL 0.3 V PWMIN High Voltage V PWMINH 2 V Input Hysteresis V Ihys mv PWMIN Sleep Pull-Up Current [1] I PWMSLEEP 1.5 µa Oscillator R OSC = 51 kω 500 khz Oscillator Frequency f OSC R OSC = 73.4 kω khz Oscillator Frequency Range [3] f OSC khz OSC Input Low Voltage V OIL 0.8 V OSC Input High Voltage V OIH 2 V OSC Watchdog Period t OSWD Between successive rising edges 17 µs Continued on the next page 5

7 ELECTRICAL CHARACTERISTICS (continued): Valid at T J = 40 C to 150 C, V IN = 5 to 45 V, unless noted otherwise. LED Current Sense Characteristics Symbol Test Conditions Min. Typ. Max. Unit Input Bias Current LN I LN V LP = V LN = 12 V 5 µa Input Bias Current LP I LP V LP = V LN = 12 V 200 µa Differential Sense Voltage V IDL PWMIN = high, V IDL = V LP V LN, I REF > 1.2 V mv Input Common-Mode Range V CMLH V LP = V LN V Analog Dimming Disable Time t DISAN PWMIN = low ms Differential Sense Voltage V IDL V IREF = 0.5 V 102 mv V IREF = 0.25 V mv IREF Maximum Voltage V IREFMAX Corresponds to sense voltage = 200 mv 1 V IREF Minimum Voltage V IREFMIN Corresponds to sense voltage = 0 mv 0 V PWM Dimming: Internal and External PWMIN to LED Turn-On Time t DIMON C L = 2 nf between PWMOUT and LN 270 ns PWMIN to LED Turn-Off Time t DIMOFF C L = 2 nf between PWMOUT and LN 210 ns PWMOUT Low Voltage V PWMLO LED on, PWMOUT wrt LP, V IN = 10 V V Peak Pull-Up Current [1] I PULLUP PWMIN = low, PWMOUT wrt LP = 0 V 25 ma Peak Pull-Down Current I PULLDOWN PWMIN = high, PWMOUT wrt LP = 8 V 50 ma PWM Dimming: External Disable Time t DISEPWM PWMIN = low ms PWM Dimming: Internal Maximum PWM Dimming Frequency f PWM 1000 Hz Minimum PWM Dimming Frequency f PWM 200 Hz PWM Dimming Frequency f PWM 70 kω between PWMIN and GND Hz PWM Duty Cycle D PWM90 D PWM5 V DR = 3.24 V, f PWM = 200 Hz V DR = 180 mv, f PWM = 200 Hz T J = 25 C % T J = 150 C 90 % T J = 25 C % T J = 150 C 5 % D PWM0 V DR = 0 V, f PWM = 200 Hz T J = 25 C 0.3 % V DRDCMAX Minimum voltage on DR for 100% duty cycle 3.6 V Disable Time t DISIPWM PWMIN = low ms Soft-Start Startup Ramp Up Source Current [1] I SOURCE Coming out of sleep mode 1 µa Ramp Up Threshold V RAMPUP 1 V Ramp Down Threshold V RAMPDOWN 100 mv Switch Current Sense and Amplifier Input Bias Current [1] I BIASS V SP = 300 mv, R SLOPE = 1.5 kω 20 µa Switch Current Overload Threshold Voltage [3] V IDS mv Voltage Gain A CS 2.25 V/V Continued on the next page 6

8 ELECTRICAL CHARACTERISTICS (continued): Valid at T J = 40 C to 150 C, V IN = 5 to 45 V, unless noted otherwise. Slope Compensation Characteristics Symbol Test Conditions Min. Typ. Max. Unit Peak Current [1] Sawtooth current waveform added to currentsense input (SP) I SLOPE µa GM Amplifier Open Loop DC Gain A VEA 62 db Transconductance g mcomp µa/v COMP Source/Sink Current [1] I COMP ±50 µa COMP Leakage Current [1] I LCOMP ±200 na Dither Generator Dither Modulation Frequency f DITH khz Maximum Switching Frequency f OSCMAX R OSC = 72 kω, R DITH = 110 kω khz Minimum Switching Frequency f OSCMIN R OSC = 72 kω, R DITH = 110 kω khz Protection Features Fault Blank Timer [4] t FB Startup 3 ms VIN Undervoltage Turn-Off V INUV Decreasing V IN, I REG = 2 ma V VIN Undervoltage Hysteresis DV INUV mv VREG Undervoltage Turn-Off V REGUV Decreasing V REG V VREG Undervoltage Hysteresis DV REGUV 300 mv LED Overcurrent Threshold V OCLED LP wrt LN mv Fixed-Output Overvoltage Threshold V FOOV Monitored at LP pin with respect to GND V Programmable-Output Overvoltage Threshold V POOV OVUV wrt LN V Output Undervoltage Threshold V OUV OVUV wrt LN 300 mv Switch Current Overload Period t SCOP Inner loop switch current 64 clock cycles LED Overcurrent Period t OPI 2 clock cycles LED Output Undervoltage Period t OPV 30 clock cycles LED overcurrent, or output undervoltage, or Hiccup Shutdown Period t HIC overvoltage, or switch overload ms PWMOUT Undervoltage Turn-On V PWMUVON Measured at LP wrt GND 6 V PWMOUT Undervoltage Turn-Off V PWMUVOFF Measured at LP wrt GND V Overtemperature Shutdown Threshold T JF Temperature increasing C Overtemperature Hysteresis DT J Recovery = T JF DT J 20 C [1] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. [2] Function is correct, but some parameters may not meet specification. [3] Parameters guaranteed by design and characterization. [4] Fault blank timer only enabled for either output undervoltage or switch current overload. 7

9 Functional Description The A6271 is a DC-DC converter controller designed to drive series-connected high-power LEDs in automotive applications. The A6271 can be configured in a variety of switching topologies, including: boost, buck-boost, and buck (ground-referenced switch). For each switching configuration, the appropriate loop compensation (COMP) and slope compensation (SLOPE) passive components are selected for optimal performance. The A6271 integrates all the necessary control elements to provide a cost-effective solution using an external logic-level, n-channel MOSFET (switching device), p-channel MOSFET (PWM device), and minimum additional external passive components. The maximum LED current is set with a single external sense resistor and can be accurately modulated using a current reference input (analog control). Direct PWM control is possible via the PWMIN input, which also provides a shutdown mode. Circuit Operation Converter The controller is based on a fixed-frequency, peak current-mode control architecture. There are two loops within the controller. The inner loop, formed by the amplifier AC (refer to Functional Block Diagram), the slope generator, the comparator, CF, and the RS bistable, controls the inductor current as measured through the switching MOSFET by the sense resistor R SS. The outer loop, formed by the amplifier AA and the integrating GM amplifier AB, controls the average LED current by providing the current demand signal for the inner loop. The LED current is measured by the sense resistor, R SL, and is averaged and amplified to a level where it is compared to the internal reference current to produce an error signal at the output of the GM amplifier, AB. This error signal is effectively the current demand signal and determines the amount of energy transferred to the LEDs on a cycle-by-cycle basis via the inner loop. The control loops work together as follows: at the beginning of each oscillator cycle, the bistable is set and the switching MOSFET is on. The switch current builds up due to the voltage developed across the inductor, and when the corresponding signal produced at the output of amplifier AC reaches the current demand level on the output of amplifier AB, the bistable is reset and the switching MOSFET is turned off. The cycle is repeated on the next oscillator cycle. If the current through the LEDs increases, the output of AA increases, causing the current demand signal to decrease. This reduces the amount of energy transferred to the LED load by terminating the switch current sooner and reducing the LED current. External Pulse-Width Modulation Dimming The DR pin should be pulled to VREG. During PWM operation, when PWMIN is pulled low, the LED stack PWMOUT is pulled high with respect to LP, turning off the external p-channel MOSFET, isolating the LED string. In addition, the GM output (amplifier AB) is parked (COMP components disconnected) at the new level and the gate drive (SG) is disabled. As the output capacitance is isolated from the LED string, there is no loss of charge. When PWMIN goes high impedance, or is pulled high, the COMP components are reconnected (with the previous parked value ), the gate drive (SG) is enabled, PWMOUT is pulled to around 8 V with respect to LP turning on the external MOSFET and allowing current to flow through the LED string. Internal Pulse-Width Modulation Dimming Where an external PWM signal is not available, the internal PWM generator can be used for controlling the LED brightness. A resistor connected between the PWMIN pin and GND sets the PWM frequency according to the following formula: R = FREQ 14,000 f PWM where R FREQ is in kω and f PWM is in Hz. The duty cycle is controlled by applying a voltage to the DR pin. The VREG can be used for the supply voltage and a potential divider can be used to set the DR voltage. An additional resistor can be added in parallel via a MOSFET switch between DR and GND to change the duty cycle between two levels. The relationship between the DR voltage and the duty cycle is as follows: PWM Duty cycle (%) = DR voltage So, for example, with a DR voltage = 1.8 V, the programmed duty cycle = 50%. In terms of the control of the external MOSFET via the PWM- OUT pin, the control is identical as the external PWM scheme. 8

10 When using the internal PWM scheme, an n-channel MOSFET is required to open the ground connection of the resistor connected between PWMIN and GND to ensure that startup occurs. The gate of the MOSFET is connected to VREG as shown in Figures 13 and 14, or to an external control signal as shown in Figures 9 and 11. As the PWMIN input has a pull-up of only 1.1 µa in sleep mode, it is essential that the zero gate voltage, drain current (leakage) of the MOSFET does not exceed this number at maximum ambient temperatures. Analog Dimming The IREF pin can then be used for full analog control. The LED current can be linearly adjusted from zero to full (100%) LED current (I LED ) by changing the IREF pin from 0 to 1 V. This feature is useful in applications where PWM control is either not required or not available and the LEDs require some dynamic correction for brightness adjustment. Analog dimming can be used along with either pulse-widthmodulation technique, internal or external. This is useful for applications where some color correction is required along with brightness control. Soft-start can be provided via the analog dim signal when either coming out of sleep or hiccup mode. The internal 1 µa internal source current on the IREF node can be overridden by applying a ramp signal to IREF. The soft-start duration is controlled by the signal on IREF as it is ramped from 0 to 1 V. If no soft-start is required, the IREF pin should be connected to VREG. If no internal PWM is required, the DR pin should be connected to VREG. Soft-Start When the A6271 comes out of sleep mode, soft-start is required to bring the output voltage up in a controlled open-loop fashion. This minimizes the possibility of the control loop saturating during the startup phase and subsequent output voltage overshoot, which can induce high transient peak currents in the LED string prior to the loop being brought back into linear control. The soft-start period can be programmed by the selection of the appropriate capacitor between IREF pin and GND pin according to the following formula: C soft = t soft where t soft is the desired soft-start period. If analog dimming is applied, the equivalent current source from this circuit will add to the internal 1 µa source current on the IREF node. Generally speaking, when using analog dimming via VREG and a potential divider, no soft-start or negligible soft-start is provided as shown in the example below. References are taken from Figure 9 on page 23: VREG (5 V) R5 20 kω R7 10 kω C6 22 nf Figure 1 IREF Pin 1 µa From the above diagram, VREG, R5, and R7 can be simplified using Norton s Theorem. The equivalent resistance can be found: R T = = 6.67 kω The current source can be found: 750 µa I source = 5 R T = 750 µa RT 6.67 kω C6 22 nf Figure 2 IREF Pin 1 µa From the above schematic, it is clear that the 750 µa current source will dominate and almost no soft-start will be provided. In this particular case, the only option is to resize C6, or increase the values of R5 and R7, or both. 9

11 LED Current-Sense Resistor The LED current is programmed by the LED sense resistor, R SL, according to: I LED = V IDL R SL where the loop typically regulates V IDL to 200 mv when in either internal or external PWM modes. The power loss of the resistor should be taken into account to ensure the correct package size is selected. The power loss of the LED current-sense resistor, R SL is: P = I 2 LED R SL It is advisable to insert a 150 Ω resistor in series with the LN pin, as shown below, to protect the internal ESD structures between LN and LP under certain fault conditions. The 150 Ω value is selected as a balance between limiting the fault current and minimizing the LED current error caused by the bias current flowing into the LN pin. Sleep Mode LP A6271 LN Figure Ω R SL If PWMIN is held low for longer than the disable time, t DIS1 or t DIS2, then the A6271 will shut down and put the majority of the circuitry into a low-power sleep mode. When internal PWM dimming is used, the disable time, t DIS1, is 14.5 ms. When either external PWM dimming or analog dimming is used, the disable time, t DIS2 is 29 ms. 5 V Regulator, VREG To provide a filtered output and to ensure the regulator is stable, a 1 µf ceramic capacitor is required to be connected between VREG and GND. The ceramic type should be a quality type such as X5R, X7R, or X8R. The 5 V regulator is sized for driving the external switching MOSFET. However, it can be used for functions that require minimal current, e.g. pulling up the FAULTn output and providing a reference for the DR, the IREF pin, or both. To check the load that the MOSFET provides, it is necessary to check the total gate charge required for a 5 V drive. This can be derived from the gate charge, Q G, versus gate drive voltage, V GS, from the MOSFET datasheet. Once the gate charge is found, the regulator load current can be determined: I LOAD = (Q G f SW )+ I external where I external is the additional circuitry added to the VREG output. The I LOAD should not exceed the VREG external current limit (I REGCL ). Oscillator Frequency, F (khz) OSC Oscillator Resistor Value, R OSC (kω) Figure 4: R OSC Required for a Particular Oscillator Frequency 10

12 Oscillator The main oscillator may be configured as a clock source or it may be driven by an external clock signal. The oscillator is designed to run between 70 and 700 khz. When the oscillator is configured as a clock source, the frequency is programmed via an external resistor between OSC pin and GND pin. The appropriate resistor can be found: R OSC = 25,690 f OSC where R OSC is in kω and f OSC is in khz. Figure 4 shows the resulting R OSC for various frequencies. When the OSC pin is driven by an external clock source, a number of A6271s can be synchronized together. If the clock period is greater than or equal to 17 µs, a watchdog circuit causes the running frequency to default to the internal oscillator, which runs at 350 khz. If the oscillator pin goes either open circuit or short circuits to GND, the running frequency defaults to 350 khz. Frequency Dithering To assist in minimizing EMI emissions, the main oscillator can be dithered so that the energy is spread over a defined frequency band. The defined frequency band is effectively the minimum and maximum switching frequency selected. This frequency is varied above and below the selected oscillator frequency and is set via a resistor connected between Dither pin and GND pin. The frequency band can be selected as follows: Δ f= ±22 R OSC R DITH where Δf is a plus/minus percentage change with respect to the oscillator frequency. For example, if an oscillator frequency of 350 khz and a dithered frequency band of ±50 khz was selected, given a minimum switching frequency of 300 khz and a maximum switching frequency of 400 khz, the R OSC and R DITHER can be found: R = OSC 25,690 f OSC 25,690 R OSC = = 73.4 kω, say 72 kω 350 Δf as a percentage of the delta with respect to the oscillator frequency is (50 / 350) 100% = 14.3%. Therefore, R DITH can be found from: f= ±22 R OSC R DITH 72 R DITH = 22 = 110 k 14.3 The switching frequency is modulated at a rate of 10 khz via a triangular waveform. This means in one modulation cycle, the switching frequency varies linearly from a minimum to a maximum to a minimum again. If the dither feature is not required, the DITH pin should be tied to VREG. Protection The A6271 includes a number of safety features to ensure the controller, the external power components, and the LED string are protected. The Fault Flag becomes active for any fault. When the device recovers from a fault, a soft-start is performed unless analog dimming is selected and the DR pin is tied to VREG. At initial startup, when coming out of sleep mode, or when the hiccup period terminates, a fault blank period, t FB, of 3 ms is applied for two fault conditions including low-side switch current limit (inner loop) protection and LED overload protection (caused by an undervoltage), before the fault circuitry becomes active. This period allows steady-state conditions to occur before fault monitoring takes place. 11

13 Output Overvoltage Protection Two overvoltage protection circuits exist: an internal fixed circuit and an externally programmable circuit. In the majority of applications, the externally programmable circuit will provide the protection. The internal circuit is present in the event that the external feedback resistor chain of the programmable circuit goes open circuit. This feature is particularly desirable in systems that require high levels of reliability and the ability to withstand failure modes. Another advantage is the possibility, in lower voltage applications, to select reduced operating voltages for the switching MOSFET, PWM MOSFET, recirculation diode, and output filter capacitors with confidence. If an overvoltage occurs in either of the two circuits, the highside MOSFET drive (PWMOUT) and the low-side MOSFET drive (SG) are immediately disabled and FAULTn is active. After one fault mask switching cycle, the hiccup timer, t HIC, is initiated for a period of 26.5 ms. At the beginning of the hiccup period, the IREF node (soft-start) capacitor is discharged immediately. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. A potential divider is set up between the LP node (output of the converter) and the cathode end of the LED stack. The output of the potential divider is monitored by a comparator referenced to the LN node. Once this voltage decreases below 1 V(max), an overvoltage condition is reported. It is recommended that the impedance of the potential divider is kept relatively high, especially in high-voltage LED strings, to minimize the current draw. It should be noted that there is negligible bias current drawn by the comparator monitor circuit. As an example, consider an LED string which has a maximum LED string voltage of 45 V and an output overvoltage (VLED OV ) is to be reported at a minimum of 15% above this value. V OVUV = 1 V R2 can be found: R2= R1 (VLED OV V OVUV ) V OVUV Assume resistor R1 is selected to be 4.3 kω. VLED OV is = 52 V. V OVUV is a minimum of 1 V. From the above formula: OVUV Switcher Output R1 R2 Cathode: LED Stack Figure 5 LED1 LEDn VLED OV R2= 4.3 ( 52 1) = 219 kω, select 220 kω 1 12

14 Overload Protection There are two circuits: 1. LED overcurrent threshold 2. Output undervoltage threshold In the case of a LED overcurrent fault, the high-side MOSFET drive (PWMOUT) and the low-side MOSFET drive (SG) are disabled after two fault mask switching cycles, FAULTn is active, the IREF node (soft-start) capacitor is discharged, then the hiccup timer, t HIC, is initiated for a period of 26.5 ms. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. In the case of an output undervoltage fault, the high-side MOS- FET drive (PWMOUT) is immediately disabled and FAULTn is active. After thirty fault mask switching cycles, the low-side MOSFET drive (SG) is disabled, IREF node (soft-start) capacitor is discharged, and the hiccup timer, t HIC, is initiated for a period of 26.5 ms. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. Low-Side Switch Current Limit (inner loop) At startup, a 3 ms blank period is applied before the circuitry becomes active. Cycle-by-cycle current protection is provided through the low-side MOSFET. If an overcurrent occurs for longer than 64 switching clock cycles, the high-side MOSFET drive (PWMOUT) and the low-side MOSFET drive (SG) are disabled, FAULTn is active, and the hiccup timer, t HIC, is initiated for a period of 26.5 ms. During the hiccup period, the IREF node (soft-start) capacitor is discharged immediately. After the hiccup period, an auto-restart is performed under control of the soft-start capacitor. Input Undervoltage or VREG Undervoltage Protection If either condition occurs, the low-side MOSFET drive (SG) is disabled and FAULTn is active (assuming VREG is high enough, if FAULTn is pulled to VREG). In the case of the input undervoltage, the high-side MOSFET drive (PWMOUT) is also disabled. Both the input voltage and the VREG voltage must rise above their respective turn-on thresholds before a restart is possible. In the case of startup through the input voltage turn-on threshold, the system is brought up under control of the soft-start. In the case of startup through the VREG turn-on threshold, no soft-start is provided. PWM Output Undervoltage During startup, the output (LP node) must increase above 6 V to ensure the high-side MOSFET turns on. This is generally not a problem with switching topologies that can boost the output voltage with respect to the input voltage. In the case of the buck topology, the LN/LP node is referenced to VIN; therefore, the input voltage has to be equal to or greater than 6 V to guarantee a successful startup. Overtemperature Shutdown If the chip exceeds the overtemperature shutdown threshold, the low-side MOSFET drive (SG) is immediately disabled, FAULTn is active, and the IREF node (soft-start) capacitor is discharged immediately. An auto-restart is performed under control of the soft-start capacitor once the temperature drops below the overtemperature minus the hysteresis level. The table on the following page summarizes the above faults along with other pin specific faults. 13

15 Table 1: Fault Table Fault Low-Side Switch Current Limit LED Overcurrent Output Undervoltage Fixed-Output Overvoltage Programmable-Output Overvoltage Input Undervoltage VREG Undervoltage Thermal Shutdown PWMOUT Undervoltage OSC Pin Fault COMP Short to GND Action When fault occurs, cycle-by-cycle current limit operates. If fault >64 counts: low-side MOSFET (SG) and PWM MOSFET (PWMOUT) off and FAULTn active, hiccup period, then auto-restart with soft-start. Note: fault blanked for 3 ms during startup. Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately off and FAULTn active, hiccup period after 2 counts, then auto-restart with soft-start. Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately off. If fault > 30 counts: FAULTn active, hiccup period, then auto-restart with soft-start. Note: fault blanked for 3 ms during startup. Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active, hiccup period after 1 count, then auto-restart with soft-start. Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active, hiccup period after 1 count, then auto-restart with soft-start. Low-side MOSFET (SG) and PWM MOSFET (PWMOUT) immediately turns off and FAULTn active assuming there is sufficient drive to the flag. Once input voltage is above the VIN undervoltage threshold, plus hysteresis, auto-restart with soft-start occurs. Low-side MOSFET (SG) immediately turns off and FAULTn active assuming there is sufficient drive to the flag. Once VREG voltage is above the VREG undervoltage threshold, plus hysteresis, then auto-restart. Low-side MOSFET (SG) immediately turns off and FAULTn active. Auto-restart with soft start occurs after the temperature drops below the overtemperature minus hysteresis level. Low-side MOSFET (SG) off and PWM MOSFET (PWMOUT) off immediately and FAULTn active. Auto-restart with soft-start occurs. The oscillator will switch to default frequency of 350 khz. Force regulator to minimum duty cycle. 14

16 COMPONENT SELECTION Inductor The main factor in selecting the inductor value is to target a certain ripple current to ensure the peak current-mode control works correctly. A reasonable figure is a peak-to-peak ripple current of around 15% of the average inductor current. The maximum inductor current occurs at minimum input voltage and maximum duty cycle. Boost Inductor Selection The maximum duty cycle can be found: D MAX = V LED+ (V f V IN(MIN) ) V + V where V LED is the LED output voltage, V f is the forward voltage drop of the recirculation diode, and V IN(MIN) is the minimum input voltage. The maximum average inductor current can be determined: I LED I AVE = (1 D MAX ) LED The ripple current, ΔI = 0.15 I AVE. The minimum inductance can now be found: L = (V LED+ V f V IN(MIN)) (1 D MAX) ΔI f SW where f SW is the switching frequency. The peak current in the inductor is: ΔI = I + 2 I LPK AVE Buck-Boost Inductor Selection The maximum duty cycle can be found: V LED+ Vf D MAX = V + V + V LED f IN(MIN) where V LED is the LED output voltage, V f is the forward voltage drop of the recirculation diode, and V IN(MIN) is the minimum input voltage. The maximum average inductor current can be determined: I LED I AVE = 1 DMAX f The ripple current, ΔI = 0.15 I AVE. The minimum inductance can now be found: V IN(MIN) D MAX L = ΔI f SW where f SW is the switching frequency. The peak current in the inductor is: ΔI = I + 2 I LPK AVE When selecting an inductor from manufacturers datasheets, there are often two current ratings given: 1. Saturation current. This is the current level that causes the inductance to drop by between 10 and 40% depending on the manufacturer. The saturation current should be greater than the peak current, I LPK, with some margin to allow for overload conditions. 2. RMS or average current. This is the current level that determines a certain temperature rise in the inductor with a given ambient temperature. This is normally presented as a single figure: operating temperature. The RMS or average inductor current rating should be greater than the estimated maximum average current, I AVE. Recommended inductor manufacturers: Coilcraft: MSS1278T or MSS1078T Range TDK: SLF12575 type H Switch Current Sense The switch current sense of the inner loop is measured by the external sense resistor, R SS, and the switch sense amplifier, AC. As well as providing the peak current information to determine the duty cycle, it also provides pulse-by-pulse current limiting through the switching MOSFET and slope compensation to prevent subharmonic oscillations at duty cycles greater than 50%. The current limit of the inner loop is set by the input limit of the sense amplifier, V IDS, the maximum switch current that has been determined, and the effects of the slope compensation have to be taken into account. The operating duty cycle has to be calculated at maximum load and minimum operating input voltage. The amount of slope compensation can be calculated for this operating point and can then be added to the actual current-sense signal to determine the maximum signal amplitude before cycle-bycycle current limiting takes effect. Refer to Slope Compensation 15

17 Section to find di L /dt then di SLOPE / dt. R = SS ( 1.2 I + LP ( 0.32 ) di SLOPE D MAX dt F SW ) Note that the minimum value of V IDS is used with an additional 20% to allow for margin. I LP is the peak current in the inductor. The power loss of the switch current-sense resistor, R SS, can be found: Boost R SS Power Loss Using the D MAX and I AVE from the boost part of the inductor section, the power loss of R SS can be found: P loss = I 2 AVE D MAX R SS Buck-Boost R SS Power Loss Using the D MAX and I AVE from the buck-boost part of the inductor section, the power loss of R SS can be found: P loss = I 2 AVE D MAX R SS Resistor manufacturers typically derate the devices from an ambient temperature of around 70 C. The power rating including derating of the sense resistor should exceed the maximum power loss at maximum ambient temperature. Slope Compensation Slope compensation can be added to the MOSFET current-sense signal on pin SP to prevent subharmonic oscillations where the peak-to-average control error becomes increasingly larger at duty cycles in excess of 50%. A current source is provided at the SP pin as a sawtooth from 0 to 100 µa. An external resistor, R SLOPE, connected between the SP pin and the source connection of the MOSFET, is used to program the appropriate voltage level to scale the slope compensation for correct use with the appropriate topology and set up conditions that have been adopted. Boost Slope Resistor The inductor down slope is: di L V LED+ V f VIN(MIN) = dt L Buck-Boost Slope Resistor The inductor down slope is: di L V LED+ Vf = dt L The optimum down slope as illustrated by Ridley can be found from: di SLOPE di L 0.18 = ( 1 ) dt dt D MAX The slope compensation resistor can be found: R = SLOPE where R SLOPE is in ohms (Ω). di SLOPE R dt SS Control Loop Compensation The recommended way of closing the control loop is to remove the influence of the right-hand plane zero (RHPZ) in both boost and buck-boost topologies. The reason for this is that the RHPZ increases the gain by 20 db/decade and at the same time introduces a 90-degree phase lag. The minimum frequency that the RHPZ occurs at is: For boost mode: 2 V LED (1 D MAX ) f RHPZ = 2 π L ILED For buck-boost mode: 2 V LED (1 D MAX ) f RHPZ = 2 π L ILED DMAX It is recommended that the 0 db crossover point is approximately: f CROSS = f RHPZ 5 With effective peak current-mode control, it can be assumed that the second power pole is pushed high enough in the frequency domain to have no influence on the overall loop response. It is reasonable to assume the overall loop response is effectively a single pole set by the GM amplifier (COMP node). The error f SW 16

18 amp zero is set at the same frequency as the output power pole to ensure the loop is closed at a rate of 20 db/decade. The open-loop DC gain of the system can be found: Boost: DC Gain = Buck-Boost: DC Gain = V ( LED I LED ) ( ) + (n R dyn ) + R SL ) 5 1,259 R SL (1 D MAX) R SS V LED I LED V LED I LED V ( LED I LED ) ( ) + D MAX ((n R dyn) + R SL ) 5 1,259 R SL (1 D MAX) R SS where n = number of LEDs and R dyn = LED dynamic resistance. Note that the LED dynamic resistance may be given in the LED datasheet. If it is not, it can be derived by a simple measurement. Set up a power supply with a current limit at the operating point (I LED1 ). Apply the current to an individual LED and measure the voltage drop (V LED1 ). Change the current limit by a small amount, say 5% (I LED2 ), and measure the voltage drop (V LED2 ). The dynamic resistance can be estimated: R dyn = V LED1 V LED2 I LED1 I LED2 The RC constant required to achieve 0 db with a slope of 20 db/ decade at the crossover frequency, f CROSS : 1 RC = 2 π fcross The frequency of the first GM amplifier pole can be found: f p1 = 1 2 π RC DC Gain Capacitor on the output of the GM amplifier (COMP node) required to achieve the above pole position: C comp = π f p1 1,258 The frequency position of the power stage pole and the GM amplifier zero is: Boost: V LED+ I LED ((n R dyn) + R SL) f p2 and f z1 = 2 V C ((n R ) + R ) Buck-Boost: f p2 π LED OUT dyn SL and f z1 = V LED + D MAX I LED ((n R dyn ) + R SL ) 2 V C ((n R ) + R ) π LED OUT dyn SL The resistor (R comp ) in series with the compensation capacitor (C comp ) on the COMP node can be found: 1 R comp = 2 π fp2 Ccomp Low-Side Switching MOSFET A logic-level n-channel MOSFET is used as the switch for the DC-DC converter. In the boost configuration, the maximum voltage across the drain-source connection is: V DS = V LED + V f In the buck-boost configuration, the maximum voltage across the drain-source connection is: V DS = V LED + V f + V INMAX The actual rating of the MOSFET selected should be greater than the maximum voltage plus some margin. It is recommended that the minimum margin should be no less than 20% of the maximum voltage. In the case of buck-boost mode, the maximum rating should factor in load-dump conditions. In terms of the current rating, the MOSFET is generally selected for a low R DS rating to minimize the power dissipation. This means the current rating is well in excess of the actual maximum current used in the application. The power loss in the MOSFET is determined by the static loss and the switching losses. Static Loss Using the D MAX and I AVE from the boost or buck-boost part of the inductor section, the power loss of R DS can be found: 17

19 P loss = I AVE 2 D MAX R DS Note that the R DS figures are generally presented at 25 C room ambients. The actual R DS can be determined by considering the normalized R DS versus temperature graph. Another consideration of the static loss is cold-crank situations. It is important to ensure the gate-drive amplitude (derived from VREG) at the minimum input voltage provides sufficient drive that the R DS does not increase by much, therefore minimizing any increase in losses. A good quality logic-level MOSFET should have good R DS performance at drive voltages of less than 4 V. The VREG load can be determined by estimating the gate losses. From the MOSFET datasheet, the total gate charge can estimated with a gate drive of 5 V using the appropriate graph. In addition, any other circuitry that VREG is powering should also be factored. The current drawn from VREG due to the MOSFET drive can be determined: VREG MOSFETload = Q TOTALGate f SW Switching Losses The switching losses in the MOSFET are determined by the length of time of the Miller region. To minimize conducted and radiated EMI emissions, this region is deliberately extended by adding series resistance between the gate drive (SG) and the gate of the device. It is assumed that the turn-off loss is similar to the turn-on loss. In the case of the boost converter, the switching loss: P switch = (V LED + V f ) I AVE t miller f SW In the case of the buck boost converter, the switching loss: P switch = (V LED + V f + V IN(MIN) ) I AVE t miller f SW Recirculation Diode The diode should have a low forward voltage to reduce conduction losses and a low capacitance to reduce switching losses and minimize EMI. Schottky diodes can provide both features if carefully selected. The forward voltage drop is a natural advantage for Schottky diodes and reduces as the current rating increases. However, as the current rating increases, the diode capacitance also increases, so the optimum selection is usually the lowest current rating above the required maximum, in this case I LPK. In the boost configuration, the maximum reverse voltage across the diode is: V RRM = V LED + V f In the buck-boost configuration, the maximum reverse voltage across the diode is: V RRM = V LED + V f + V IN(MAX) The actual rating of the diode selected should be greater than the maximum voltage plus some margin. It is recommended that the minimum margin should be no less than 20% of the maximum voltage. In the case of buck-boost mode, the maximum rating should factor in load-dump conditions. High-Side PWM MOSFET A p-channel MOSFET is used as the PWM switch for the LED stack. In both boost and buck-boost modes, the maximum voltage across the drain-source connection is V LED. The actual rating of the MOSFET selected should be greater than the maximum voltage plus some margin. It is recommended that the minimum margin should be no less than 20% of the maximum voltage. The power loss of this MOSFET is dominated by the static loss. The switching losses can largely be ignored as the PWM frequencies are relatively low. The power loss of the MOSFET R DS can be found: P loss = I 2 LED R DS The gate drive for the PWM MOSFET is derived from the LED output rail (LP pin). In boost and buck-boost modes, this node is boosted with respect to the input voltage (V IN ), so there should be sufficient negative gate drive. In other operating modes such as buck, where the output voltage is less than the input voltage, it may be necessary to use low threshold p-channel MOSFETs to ensure adequate overdrive during cold-crank situations. 18

20 Output Capacitor There are several points to consider when selecting the output capacitor. Due to the switching topology used, the ripple current for this circuit is high since the output capacitor provides the LED current when the DC-DC converter switch is active in both boost and buck-boost modes. The capacitor is then recharged each time the inductor passes energy to the output. The ripple current on the output capacitor will be equal to the peak inductor current. The corresponding output ripple can be derived from the amount of charge transferred to the output during the switch on time. To minimize heating effects and voltage ripple, the equivalent series resistance (ESR) and the equivalent series inductance (ESL) should be kept as low as possible. This can be achieved by multilayer ceramic chip (MLCC) capacitors. To reduce performance variation over temperature, low drift types such as X7R and X5R should be used. The value of the output capacitor will typically be in the range of 3.3 to 10 µf, and it should be rated above the maximum LED stack voltage, V LED. There is an E-field effect with ceramic capacitors that causes the capacitance to fall at elevated voltages. It is therefore recommended that a good margin is selected to minimize this effect. One potential issue of ceramic capacitors is audible noise during pulse-width modulation (PWM). This is caused by the piezoelectric effect of the ceramic substrate. To minimize the effects of this, it is recommended to use multiple physically smaller capacitors. If this is still an issue, it is recommended that either low-impedance electrolytic or polymer capacitors be used. Input Capacitor The function of the input filter capacitor is to provide a lowimpedance shunt path for the current drawn by the A6271 when the switching MOSFET turns on. The objective is to minimize the ripple current reflected back into the source supply. This approach helps to minimize conducted emissions into the power source. Additional line impedance in the form of chokes can be added to improve the emissions further. In a correctly designed system, with a quality capacitor or capacitors positioned adjacent to the power train circuitry, these capacitors should supply the ripple current. The amount of capacitance required at the input is dictated by the EMI performance. This is usually distributed with series ferrite beads and either differential-mode chokes, or common-mode chokes, or both. Layout The following layout guidelines should be followed to ensure satisfactory electrical and EMI performance. Ground planes should be used on as many layers as possible. This is essential in minimizing ground bounce (differential voltage across the ground connection). Ground bounce can lead to radiated noise which can then be picked up on both input and output connections and manifest as common-mode noise. Any ground planes on different layers should be connected using multiple vias in an attempt to minimize ground impedances. The ground tab under the A6271 should also have multiple vias connecting to the ground plane or planes. The drain connection of the switching MOSFET, PWM MOS- FET, and cathode terminal of the recirculation diode are used for thermal heatsinking. It is advised to use sufficient copper around these connections on the component layer of the PCB only. The areas directly under these connections on the PCB should form part of the ground plane. The reason for restricting the copper area on these nodes is because they can radiate noise due to the nature of the dv/dt and di/dt power signals that appear. The area of the switching power loops should be minimized as much as possible. In addition, the trace connections should be as wide as possible to minimize parasitic leakage inductances, but at the same time not compromising the power loop area. There are two power loops: Loop 1: formed by the input filter, main switching MOSFET, power inductor, and inner loop sense resistor. Loop 2: formed by the power inductor, recirculation diode, LED sense resistor, PWM MOSFET, and the output capacitor or capacitors. Where practical, keep input or output filter magnetics as far away from the power-switching inductor (L1) as possible. This is to avoid or at least minimize the effects of magnetic crosstalk. One of the major noise contributors is the switching MOSFET (M1). Slowing down the gate drive without compromising the thermal solution will help to minimize noise. To comply with CISPR 25, a common-mode choke is typically required as part of the input filter. 19

21 Reducing EMI It is essential that good layout practice as defined in the Layout Section should be adopted. The following techniques are also recommended. Snubber Adding a low-loss R-C snubber network between the drain of the main switching MOSFET and ground helps to suppress the resonant ringing on the switching node. The process for selecting these components involves some trial and error on the actual printed circuit board. Step 1: Measure the voltage resonance frequency on the LX node. Step 2: Add an additional capacitance between LX and ground until the resonant frequency is halved. Note that this capacitance should be around 1 nf. Step 3: Two equations with two unknowns are now obtained: 1 F RES = 2 π L C where C new = C leak + C add. leak F RES 1 = 2 2 π L C C add = additional capacitance added. C leak = parasitic capacitance. L leak = parasitic inductance. Now to halve the frequency, C leak + C add = 4 x C leak Therefore, C leak = C add 3 leak With C leak solved, L leak can also be solved. The characteristic impedance of the parasitic components can be found: R O = L leak C leak R O can be selected as the damping resistor. Typically, either an 0805 or 0603 resistor case size is adequate. leak new Input Filter The selection of the components that form the input filter depends on the noise that is present in the system in terms of the frequency and whether it is common mode or differential mode. In addition, the common automotive standards that exist define onerous specification limit lines for the emissions in the AM band (approximately 530 khz to 1.7 MHz) and the FM band (approximately 70 to 108 MHz). Some consideration must be given to these frequency bands to understand how to filter these regions. At the lower frequencies, below a few 10s of MHz, the noise is generally dominated by differential noise with some common mode noise. At frequencies above a few 10s of MHz, the noise is dominated by common mode noise with some differential noise. To address the differential noise, a differntial inductor can be used along with differential capacitance to form an L-C filter. One problem in using standard differential inductors is that the self-resonance frequency (SRF) is typically in the region of a few 10s of MHz, even with a modest few microhenries (µh) (note: the higher the inductance, the lower the SRF). This means that above the self-resonant frequency points, these components actually amplify the noise and make matters worse. Some differential-mode inductive filtering is always necessary. Ferrite beads can be used for this function. Although ferrite beads are designed to act as a lossy resistor at particular frequency bands, they do have an inherent inductive element which can be in the region of several µh. The inductance of a ferrite bead can be extracted from the reactance information graph (refer to Figure 7). At a particular frequency, the reactance can be found and then the inductance can be derived. As a single ferrite bead may not be effective enough, a two-stage ferrite bead filter approach can be taken. These components, along with input differential-mode capacitors, can form L-C filter stages. For the best result, the first L-C filter should be placed as close to the power stage as possible. At higher frequencies, the majority of the noise problems is associated with common-mode noise. This noise is induced by ground-referenced differential noise radiating through the ground plane. This noise can be picked up on the input stage forming common-mode noise on the positive and negative power supply connections to the battery. Even with excellent layout, this noise is always present. To address this problem, a common-mode inductor is required. 20