Low-Power CMOS with Subvolt Supply Voltages

Transcription

1 394 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 2, APRIL 2001 obtained over the 1000 experiments are presented in Table II for four of the benchmark circuits (similar trends were observed for the other circuits). We can see that our dual-threshold selection heuristic performs much better than a random selection of K gates. By repeating the random experiments a large number of times (1000), we attain a high level of confidence that our algorithms can provide a very fast and near-optimal solution, as opposed to randomized optimization algorithms like simulated annealing. VI. CONCLUSION We have demonstrated a new approach to low power optimization of digital static CMOS circuits for dual-threshold voltage manufacturing processes. The algorithms developed allow the designer to assign one of two threshold voltages to all the gates in the circuit. The assignment is performed in such a way that subsequent optimization for low power operation yields a significant reduction in the total power consumption of the circuit. Experiments were conducted on several ISCAS89 benchmark circuits and results indicate that significant improvement in power consumption, over single high-v t circuits, can be achieved. The algorithm is fast and typically completes in a few CPU seconds. REFERENCES [1] A. Chandrakasan and R. Brodersen, Minimizing power consumption in digital CMOS circuits, Proc. IEEE, vol. 83, pp , Apr [2] J. Cong and C.-K. Koh, Simultaneous driver and wire sizing for performance and power optimization, IEEE Trans. VLSI Syst., vol. 2, pp , Dec [3] D. Liu and C. Svensson, Trading speed for low power by choice of supply and threshold voltages, IEEE J. Solid-State Circuits, vol. 28, pp , Jan [4] Z. Chen and J. Plummer, Low threshold voltage quarter micron MOS- FETs for low power applications, in Proc. IEEE Symp. Low Power Electronics, 1995, pp [5] P. Pant, V. De, and A. Chatterjee, Simultaneous power supply, threshold voltage and transistor size optimization for low power operation of CMOS circuits, IEEE Trans. VLSI Syst., vol. 6, pp , Dec [6] R. Gonzalez, B. M. Gorden, and M. Horowitz, Supply and threshold voltage scaling for low power CMOS, IEEE J. Solid-State Circuits, vol. 32, pp , Aug [7] J. Burr and J. Shott, A 200 mv self-testing encoder-decoder circuit using stanford ultra low power CMOS, in Proc. Int. Solid-State Circuits Conf., Feb. 1994, pp [8] L. Wei, Z. Chen, M. Johnson, K. Roy, and V. De, Design and optimization of low voltage high performance dual threshold CMOS circuits, in Proc. Design Automation Conf., 1998, pp [9] Q. Wang and S. Vrudhula, Static power optimization of deep submicron CMOS circuits for dual v technology, in Proc. Int. Conf. Computer- Aided Design, 1998, pp [10] S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, An exact solution to the transistor sizing problem for CMOS circuits using convex optimization, IEEE Trans. Comput.-Aided Design, vol. 12, pp , Nov [11] N. Hendenstierna and K. Jeppson, CMOS circuit speed and buffer optimization, IEEE Trans. Comput.-Aided Design, vol. 6, pp , Mar [12] B. Hoppe, G. Neuendorf, D. Schmitt-Landsiedel, and W. Specks, Optimization of high-speed CMOS logic circuits analytical models for signal delay, chip area and dynamic power dissipation, IEEE Trans. Computer-Aided Design, vol. 9, pp , Mar Low-Power CMOS Subvolt Supply Voltages Mircea R. Stan Abstract We first present a circuit taxonomy along the space and time dimensions, which is useful for classifying generic low-power techniques, followed by an analysis of optimal power supply and threshold voltages and transistor sizing for minimizing the energy-delay product of a class of complementary metal oxide semiconductor (CMOS) digital circuits. Index Terms Digital-complementary metal oxide semiconductor (CMOS) VLSI, low-power design, low voltage, power consumption model. I. INTRODUCTION Power consumption in complementary metal oxide semiconductor (CMOS) has two components: ac (dynamic) power that varies operating frequency and dc (static) power that is independent of frequency [1] [3]. The two major sources of dynamic power are the capacitive current for charging and discharging load capacitances and the short circuit (or overlap) current [4]. When the supply voltage is aggressively scaled down the percentage of short circuit power becomes smaller and tends to zero as V gets close to V th [5]. The two major sources of static power are the subthreshold current [6], [7] and the junction leakage current. In deep submicron technologies the junction leakage becomes negligible compared to the subthreshold current, but other leakage phenomena like gate oxide tunneling and gate induced drain leakage (GIDL) are likely to become important [8], [9]. Although recognized as an important method to reduce power [1], scaling the power supply voltage has been historically driven by reliability concerns (gate oxide breakdown voltage and leakage) and not by power reduction strategies. The SIA Technology Roadmap [10], [11] predicts a V =0:9V00:6Vin the year 2009 for a 70 nm technology, and a V =0:6V00:5Vin the year 2012 for a 50 nm technology. In what follows we show that a V as low as 0.8 V should be used for low-power circuits even current 0.25 and 0.18 processes as it provides the optimum energy-delay product for the design. A. Figures of Merit for Low-Power Design The classic two-dimensional VLSI design space tries to minimize the circuit area (A) and delay (T) in order to reduce cost and improve performance, by using optimizations objective functions such as A, AT, and AT 2 [12]. The new emphasis on low power as a third dimension (power) to the previously two-dimensional design space [13], but, except for a few cases [14], most of the research in lowpower design is still two-dimensional objective functions such as P (power), PT (energy), and PT 2 (energy-delay product). 1 The power P itself is a poor candidate for optimization as it can always be lowered trivially by reducing the clock frequency. The energy PT is an appropriate figure of merit for applications out stringent performance requirements, but, when performance is critical, the energy-delay product PT 2 is a good compromise between the need to reduce power while still operating at reasonable speed [15]. Manuscript received February 20, 1999; revised September 23, This work was supported in part by NSF CAREER Award MIP The author is the Electrical Engineering Department, University of Virginia, Charlottesville, VA USA ( mircea@virginia.edu). Publisher Item Identifier S (01) The notation PT for energy and PT for energy-delay product is used to underscore the replacement of area by power in the classic AT and AT figures of merit /01$ IEEE

2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 2, APRIL In the rest of the paper we present a circuit taxonomy for classifying low-power techniques followed by a generic low-power technique which applies directly to quasi-homogeneous and stationary circuits but can be also extrapolated to other classes of applications. II. CIRCUIT CLASSIFICATION FOR LOW-POWER TECHNIQUES Most low-power design techniques are effective only for specific types of circuits and applications. In order to classify different techniques we propose a circuit taxonomy along the space and time dimensions. In particular, according to their structure in space, circuits can be roughly classified as: quasi-homogeneous, when all the sub-blocks of a circuit are similar in terms of performance requirements (e.g., a systolic array or other regular array structures where no single critical path can be identified); nonhomogeneous, when there are a few critical paths in the circuit and the remaining logic is not on a critical path (most of the so called random logic circuits are in this class); clustered nonhomogeneous, when there are clearly separated blocks in the circuit that have different performance requirements (e.g., system-on-chip circuits blocks of different functionality, like a processor and a memory, placed on the same die). According to their time behavior circuits can be classified as: quasi-stationary, when the performance requirements do not drastically change in time (e.g., many signal processing applications); continuously nonstationary, when the performance requirements change continuously depending on computation load (e.g., CPU in a microprocessor system); nonstationary standby, when the performance requirements change abruptly between full-speed and sleep modes (e.g., circuits for portable applications). The above taxonomy is useful for classifying different low-power techniques but it should be understood that the boundary between the different classes is somewhat arbitrary, for example a quasi-homogeneous circuit at the logic or architecture level may still have critical paths at the transistor level, a continuously nonstationary circuit may have a sleep mode, etc. In this paper we specifically aress issues related to quasi-homogeneous stationary circuits, but many of the results can be extrapolated to broader classes of circuits good results as shown by our simulations. III. LOW-POWER QUASI-HOMOGENEOUS STATIONARY CIRCUITS Few circuits can be considered truly quasi-homogeneous and stationary but it is convenient to look at such circuits in order to derive some generic power optimization techniques. When scaling the voltages for quasi-homogeneous and stationary circuits there will be unique optimal V and V th values for the entire circuit. Finding these values under some general assumptions about the circuit has been previously investigated [3], [16] [19]; here we use [16] as a starting point to obtain a few novel results. A. Optimal Supply and Threshold Voltages By writing the total power consumption of the average gate in a circuit (equivalent to considering a homogeneous circuit model) as the sum of the capacitive power and subthreshold leakage power, and the delay according to the -power law model [20], we obtain the energydelay product as in [16] 2 PT 2 = K3 1 V 3 (V 0 V th ) K 2 + e0(v =V ) (V 0 V th ) (1) K 2 = C e I s 1 K 1 1 L d ; K 3 = K I s 1 L d where 1:3 0 1:5 for current technologies [16], V T = KT=q 26 mv at room temperature, =1+C di =C ox 1:5 for current processes, L d is the logic depth, I s is the leakage current for V gs = V th ; C e is the average effective switched capacitance, and K 1 depends on the technology and circuit style. The following two equations are obtained when finding the minimum energy-delay product [16]: V = V th V T (2) n f (n) = e n 1 ( 1 (n +3)1 V T ) 1 (3 0 ) 10 = K 2 (3) n = V th V T : Equations (2) and (3) provide the optimal supply and threshold voltages almost independent of the technology (except for and K 2 ; see the Appendix). With 1:3 0 1:5 [16] the optimal supply voltage can be roughly approximated as V opt 2V th. Equation (3) cannot be solved analytically [16], but numerically, for a typical current technology, the ratio V th =V T which results in an optimal V th 150 mv mv. The relationship between the optimal ratio n = V th =V T and K 2 is important because K 2 is under the control of the circuit designer. Fig. 1 shows the right-hand side of (3) for three values of (1.3, 1.5, and 2). As the curves are close to each other we conclude that there is little variation of the optimal n due to, especially for small values of K 2. For the parameters in the Appendix, K 2 0:25 which results in n opt = V th =V T 5. Smaller K 2 will result in a larger ratio V th =V T, while a larger K 2 will result in a smaller ratio V th =V T. The optimal ratio n = V th =V T will be typically less than 10 (i.e., optimal V th < 390 mv) for realistic values of K 2 (e.g., K 2 > 0:01). B. Optimal Ratio of ac to dc Power For a minimum energy solution the ac and dc power should be approximately equal [3]. Here we show that for minimum energy-delay product the ratio of ac and dc power is approximately equal to 0:67n = 0:67V th =V T (30 4 for the values in the Appendix) for 1:5 and V 2V th.for =2the optimal ratio of ac to dc power becomes larger than 10. Assuming =1:5and V =2V th (1) becomes PT 2 = 8K 3 1 V 3 th V 1:5 K 2 + e0(v =V ) V 1:5 th th = K 4 1 K 2 1 n 1:5 + e 0n (4) K 4 =8K 3 1 (V T ) 1:5 : For the optimal n = V th =V T ratio we take the derivative of (4) respect to n and set to zero to obtain e 0n =1:5K 2 1 n 0:5 : (5) 2 Note the slight inconsistency in that PT, as a notation for energy-delay product, is equal to P 1 T 1 T, not to P 1 T.

3 396 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 2, APRIL 2001 Fig. 1. f(n) for 4 n 8 and =1:3;1:5; and 2. Replacing (5) in (4) we obtain the desired result P AC P DC = PT2 AC K2 1 n1:5 opt PT 2 = 2 V th : (6) DC e 0n 3 V T This provides a simple voltage scaling rule-of-thumb for optimal energy-delay product simply by looking at the ratio of ac to dc power. A large ratio suggests that more parallelism should be used to reduce dynamic power, while a small ratio implies that a more serial implementation will be optimal by reducing leakage. C. Variation of V Until now 1:5 was assumed but at very low V the short-channel effects become less critical and approaches theidealvalue of 2. In order to observe the variation of supply voltage for a given technology we extracted an approximate value numerically from HSPICE simulations using BSIM3v3 [21] models. This extraction was done by curve fitting analytically the simulated I V characteristics for different V values to the -power law equation [20]. Fig. 2 shows that indeed, as the voltage gets into the sub-volt range 2, and for V th V T the optimal V opt 3V th as was previously determined in [3]. It should be understood though that, as the technology scales to the nanometer range, the devices become velocity saturated at even smaller supply voltages which means that becomes again <2, even for low V values. When both V and V th are aggressively scaled we cannot ignore any of the two terms in (2) and V opt 3V th +6V T. This forces us to revisit the first order results presented in the previous sections. The results concerning n do not change drastically as was seen in Fig. 1, but the optimal supply voltage becomes V opt 0:7 V00:8 V 4V th which is larger than all previously reported first order analytical results [3], [16], [22]. When 2 the optimum ratio of ac and dc power is also larger than the value computed in the previous section. Numerically, for K 2 = 0:25 and n =5, the optimal ratio is P AC =P DC 12 which again is much larger than previously published results. These analytical results have been verified through simulation. A custom designed carry-lookahead aer [23], [24] was simulated HSPICE using BSIM3v3 models [21] for a current 0.25 CMOS technology. The simulation results are a good confirmation of the analytical values, especially concerning the V to V th ratio. The optimum values obtained from the simulation are n 4; V th 150 mv, and V 0:75 V for a low activity case, and n 3; V th 100 mv and V 0:5 V for a high activity case. The optimal V values from simulation are indeed very close to 3V th +6V T, but the accuracy of V th is not as good. This is due to the low logic depth of the carry-lookahead aer and to the fact that it is not truly a homogeneous and stationary circuit. This results in a small value for n which places the optimization on the steep part of the f (n) curve in Fig. 1. D. Sizing for Minimum Energy-Delay Product Scaling the voltages has assumed an effective capacitive load C e as a function of technology, switching activity, ratio of gate to parasitic and interconnect capacitance, fanout, etc. Here we show analytically (the result was also shown graphically in [15]) that the optimal transistor sizing for minimum energy-delay product is obtained when the transistor capacitance equals the interconnect capacitance. Furthermore, this optimal sizing is independent of voltage scaling, hence it can be done in parallel optimizing V th and V. The circuit model for this section includes the fanout m and an explicit interconnect capacitance C w as in Fig. 3. From Section III-A we use the fact that the optimal ratio of ac to dc power is a fixed fraction r = P AC =P DC. Equation (1) can thus be approximated as PT 2 = (1 + 1=r)K 2 1 K 3 1 V 3 (V 0 V th ) = (1 + 1=r)K 1 1 C e 1 V 3 (V 0 V th ) : (7) K 1 and C e can be rewritten such that transistor sizes become explicit (see the Appendix) C e = a 1 C; K C 1 g L 1 = 1 1 C ox W C = m 1 (C t + C w )=m1(k 5 1 W 1 L 1 C ox + C w ) K 5 =(1+p=n) 1 (1 + d=t)

4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 2, APRIL Fig. 2. as a function of supply voltage. where a the switching activity; m the fanout; p=n the ratio of the width of the PMOS to the width of the NMOS; g the logical effort [25]; d=t the ratio of parasitic (e.g., diffusion, short-circuit equivalent, etc.) capacitance to gate capacitance; C t and C w the transistor and interconnect capacitances, respectively. C w = Y 1L1C ox can be replaced in (7) by denoting Y as the equivalent transistor width that has the same capacitance as the average wire PT 2 = K 6 1 g 1 m 2 (K 5 1 W + Y ) 2 W K 6 = (1 + 1=r)a 1 2L3 1 C ox 1 V 3 1 (V 0 V th ) : By taking the derivative of (8) respect to W and setting to zero we obtain the optimum sizing as W opt = Y=K 5. This means that the optimal sizing is such that the transistor capacitance C t = K 5 1 W 1 L 1 C ox is equal to the interconnect capacitance C w = Y 1 L 1 C ox. This result is totally independent of voltage scaling and partially contradicts the common wisdom to use minimum size transistors in low-power design. Assuming an average interconnect capacitance of 40 ff [17] it results that the optimal transistor width should be W opt 11:25 m which is many (30) times larger than the minimum size in a 0.25 technology. The result above is generic in nature and needs to be used only as a starting point for more detailed optimizations. One obvious missing item is the variation of the average interconnect capacitance (which is considered fixed here) as a function of increasing transistor sizes. A more detailed analysis could also consider the effect of the p transistor to n transistor ratio, the effect of rise time and fall time on short-circuit power [26], or even the simultaneous sizing of transistors and wires [27], [28]. (8) E. Buffered Design for Optimal Energy-Delay Product As the optimal sizing in the presence of interconnect parasitics is much larger than minimum size, it is natural to examine the effect of a buffered circuit style which can drive the interconnect more efficiently as in Fig. 4. A buffered circuit style is widely used in dynamic Domino circuits and was proposed for static logic as QuadRail [29], [30]. First we rewrite the equivalent of (8) by assuming that the effect of the large interconnect capacitance is only seen at the output buffer m 2 (K PT W 1 + Y ) 2 = K g(k W 2 ) 6 + : (9) W 2 W 1 W 1 is the sizing for the logic gate and W 2 is the sizing for the buffer, the fanout m only affects the buffer, and the logical effort for the buffer is 1. By taking the derivative respect to W 1 and W 2 and setting to zero to obtain the optimal values W Y 1opt = = 1 3K 5 3 Wopt W 2opt = 2Y 3K 5 1 m 2 g 1=3 = 23 1 m 2 g 1=3 W opt where W opt = Y=K 5 was the optimal size for the unbuffered case. The first observation is that for m =1(no fanout) and g =1(no logical effort) the optimal sizes are W 1opt = Y=3K 5 = (1=3)W opt and W 2opt = 2Y=3K 5 = (2=3)W opt. The energy-delay product in this case remains the same as in the unbuffered case. When m and g are >1 the savings can be quite large. For example for m = 5and g = 3, W 1 opt = Y=3K 5 and W 2opt 4Y=3K 5 which leads to PT 2 bu K 6 1 4Y 1 K 5(1=3m 2 +4=9g) =29=3 1 K 6 1 4Y 1 K 5 a saving of 87% in energy-delay product (PT 2 unbu =751 K 6 1 4Y 1 K 5 ).

5 398 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 2, APRIL 2001 Fig. 3. Circuit average fanout m, average interconnect load C, and logic depth L. Fig. 4. Circuit logic and buffer stages. Fig. 5. Constant energy-delay curves for K = 0:25. F. Parameter Variations Until now the analysis assumes that all parameters (V ;V th, sizes, etc.) can be precisely controlled; in reality there are always going to be parameter variations due to process, temperature, etc. The inter-die V th variations can be compensated by back-biasing [31], but intra-die random variations [32] represent a bigger problem which may limit the effectiveness of aggressive threshold scaling in the future. Energydelay curves as in Fig. 5 show a nearly flat region near the minimum for voltages slightly larger than the optimum values and a steep increase for smaller values [16]. This suggests a conservative approach: optimize for worst case such that the variations due to process and temperature will only make the actual values larger than optimum. This makes the typical design suboptimal but for small parameter variations the increase will not be significant. A variation of 25% in V th for example leads to an increase of 20% in energy-delay for the values in the Appendix. A better approach could use statistical methods [33] and let the voltages also be smaller than optimum but a small probability and thus bring the typical case closer to the optimum. IV. CONCLUSION We have presented several new results related to optimal voltages and sizing of CMOS circuits for minimum energy-delay product. These

6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 2, APRIL TABLE I TYPICAL PARAMETERS FOR A 0.25-m CMOS TECHNOLOGY where the carrier mobility = 1000 cm 2 /V1s and L =0:25 m which results in the desired i s 1 A/m [16]. K 1 and K 2 can be computed using the following: K 1 = K 2 = C 1 g 1 C ox 1 C e L W = I s 1 K 1 1 L d g 1 L d 1 V 2 T g =6as another fudge factor to account for the logical effort [25] and the reduced current drive in deep-submicron, compared to an ideal inverter. This results in K ps and K 2 0:25. a ACKNOWLEDGMENT The author would like to thank A. Forestier for help some of the simulations and T. Callaway for providing the carry-lookahead aer circuit used for simulation in Section III-C. results were presented in the context of a generic circuit classification along space and time which helps understand the limitations and applicability of various low-power techniques. APPENDIX All the computations in Section III are based on a large number of parameters depending on technology, circuit style, etc. Here some of the values are explained analytically although some of the choices are more or less arbitrary in order to track published data. Table I summarizes the results. C e and I s are the capacitance and current for the average gate while c e and i s are the values per micron of transistor width [16]. The value of c e 1 ff/m can be justified by using the following formulas and a choice of parameters as in Table I c e = C e =W ; C e = a 1 C C = m 1 (K 5 1 W 1 L 1 C ox + C w ) K 5 =(1+p=n) 1 (1 + d=t): Assuming p=n = 2(PMOS transistor twice larger than NMOS) and d=t 0:37 (a fudge factor to account for parasitic capacitances besides interconnect and for the short-circuit current), K 5 4. From Section III-D the transistor capacitance C t = K 5 1W 1L1C ox equals the interconnect capacitance C w which means that for an average C w 40 ff [17], average fanout m = 5 and average switching activity a =0:03; C e =0: ff =12fF. The equivalent interconnect transistor width Y = C w =(L1 C ox ) 46 m and the optimal transistor width W opt = Y=K 5 46=4 =11:5 m, where C ox = ( r 1 0 )=T ox =3:45 ff/m 2. Finally we obtain c e = C e =W opt 1 ff/m as in [16]. The zero-threshold current i s 1 A/m can be computed the following formulas [7]: I s = i s 1 W ; i s = 1 V 2 T 1 C ox L REFERENCES [1] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low-power CMOS digital design, Proc. IEEE, vol. 81, [2] A. P. Chandrakasan and R. W. Brodersen, Minimizing power consumption in digital CMOS circuits, Proc. IEEE, vol. 83, pp , Apr [3] J. B. Burr and A. M. Peterson, Ultra low power CMOS technology, in Proc. NASA VLSI Design Symp., [4] S. Turgis, N. Azemard, and D. Auvergne, Explicit evaluation of short circuit power dissipation for CMOS logic structures, in Proc. Int. Symp. Low Power Design, Dana Point, CA, Apr. 1995, pp [5] A. Alvandpour, P. Ededefors, and C. Svensson, Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits, in Proc. Int. Symp. Low Power Electronics Design, Monterey, CA, Aug. 1998, pp [6] T. A. Fjeldly and M. Shur, Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFET, IEEE Trans. Electron Devices, vol. 40, pp , Jan [7] T. Grotjohn and B. Hoefflinger, A parametric short-channel MOS transistor model for subthreshold and strong inversion current, IEEE Trans. Electron Devices, pp , [8] K. Roy, Low power design and leakage control techniques for deep submicron IC s, in Tutorial at VLSI Design Conf., Jan [9] A. Keshavarzi, K. Roy, and C. Hawkins, Intrinsic IDDQ: Origins, reduction, and applications in deep sub-low-power CMOS IC s, in Proc. Int. Test Conf., 1997, pp [10] SIA, The national technology roadmap for semiconductors,, [11] SIA, The international technology roadmap for semiconductors,, [12] J. Ullman, Ed., Computational Aspects of VLSI. Rockville, MD: Comput. Sci. Press, [13] D. Singh, J. M. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. J. Mozdzen, Power conscious CAD tools and methodologies: A perspective, Proc. IEEE, vol. 83, pp , Apr [14] C. Chen and C. Tsui, Toward the capability of providing power-areadelay trade-off at the register transfer level, in Proc. Int. Symp. Low Power Electronics Design, Monterey, CA, Aug. 1998, pp [15] M. Horowitz, T. Indermaur, and R. Gonzalez, Low-power digital design, in Proc. Symp. Low Power Electronics, Oct. 1994, pp [16] R. Gonzales, B. M. Gordon, and M. A. Horowitz, Supply and threshold voltage scaling for low-power CMOS, IEEE J. Solid-State Circuits, vol. 32, pp , Aug [17] A. J. Bhavnagarwala, B. Austin, and J. D. Meindl, Minimum supply voltage for bulk Si CMOS GSI, in Proc. Int. Symp. Low Power Electronics Design, Monterey, CA, Aug [18] D. Liu and C. Svensson, Trading speed for low-power by choice of supply and threshold voltages, IEEE J. Solid-State Circuits, vol. 28, pp , Jan [19] C. Svensson and A. Alvandpour, Low power and low voltage CMOS digital circuit techniques, in Proc. Int. Symp. Low Power Electronics Design, Monterey, CA, Aug. 1998, pp [20] T. Sakurai and R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE J. Solid- State Circuits, vol. 25, pp , Apr [21] U. Berkeley. (1997) BSIM3v3.1 SPICE MOS device model. [Online]. Available:

7 400 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 2, APRIL 2001 [22] M. R. Stan, Optimal voltages and sizing for low power, in Proc. VLSI Design Conf., Goa, India, Jan [23] T. K. Callaway and E. E. Swartzlander, Estimating the power consumption of CMOS aers, in Proc. Symp. Computer Arithmetic, Windsor, ON, Canada, 1993, pp [24] T. K. Callaway, Area, delay, and power modeling of CMOS aers and multipliers, Ph.D. dissertation, Dept. Elect./Comput. Eng., Univ. Texas Austin, TX, Dec [25] I. E. Sutherland and R. F. Sproull, Logical effort: Designing for speed on the back of an envelope, in Proc. Conf. Advanced Research in VLSI, Nov [26] M. Borah, R. M. Owens, and M. J. Irwin, Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint, in Proc. Int. Symp. Low Power Design, Dana Point, CA, Apr. 1995, pp [27] N. Menezes, R. Baldick, and L. T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, in Proc. Int. Conf. Computer-Aided Design, Nov. 1995, pp [28] J. Cong, C.-K. Koh, and K.-S. Leung, Simultaneous driver and wire sizing for performance and power optimization, IEEE Trans. VLSI Syst., vol. 2, pp , Dec [29] R. K. Krishnamurthy and L. R. Carley, Exploring the design space of mixed-swing QuadRail for low-power digital circuits, IEEE Trans. VLSI Syst., vol. 5, pp , Dec [30] L. R. Carley and I. Lys, QuadRail: A design methodology for lowpower ICs, IEEE Trans. VLSI Syst., vol. 2, pp , Dec [31] M. Miyazaki, H. Mizuno, and K. Ishibashi, A delay distribution squeezing scheme speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs, in Proc. Int. Symp. Low Power Electronics Design, Monterey, CA, Aug. 1998, pp [32] X. Tang, V. De, and J. Meindl, Effects of random MOSFET parameter fluctuations on total power consumption, in Proc. Int. Symp. Low Power Electronics Design, 1996, pp [33] M. Orshansky, J. Chen, C. Hu, C.-P. Wan, and P. Bendix, Direct sampling methodology for statistical analysis of scaled CMOS technologies, IEEE Trans. Semiconduct.r Manufact., vol. 12, Power Estimation for Large Sequential Circuits Joseph N. Kozhaya and Farid N. Najm Abstract A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a user-supplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value which can be quite tight (under 10% difference between the two in many cases). As a result, the power dissipation is obtained by simulating only a fraction of the potentially very large vector set. Index Terms Finite-state machine (FSM), power estimation, sequential circuit. I. INTRODUCTION Maximizing circuit speed and minimizing chip area used to be the only major concerns of VLSI designers. In recent years, power consumption of integrated circuits (ICs) has proved to be just as important of a concern. Thus, VLSI designs nowadays emerge as a tradeoff Manuscript received April 10, 1999; revised August 30, J. N. Kozhaya is the Electrical and Computer Engineering Department, University of Illinois, Urbana-Champaign, IL USA. F. N. Najm is the Electrical and Computer Engineering Department, University of Toronto, Toronto, ON M5S 3G4, Canada. Publisher Item Identifier S (01) among three goals: minimum area, maximum speed, and minimum power dissipation. Power dissipation is a major concern of the semiconductor industry. This is because excessive power dissipation causes overheating, which may lead to soft errors or permanent damage. It also limits battery life in portable equipment. Thus, there is a need to accurately estimate the power dissipation of an IC during the design phase. We should note that by power estimation we refer to the problem of average power estimation. This is different from the estimation of the worst case instantaneous power. Chip reliability and equipment lifetime are directly related to the average power. Several approaches have been proposed for power estimation [1], especially for estimation at the gate-level. However, even at the gatelevel, the problem is not yet completely solved. At least two open problems remain: 1) Accurate and fast estimation of the average power dissipated by individual gates, typically inside an optimization loop and 2) Accurate and fast estimation of the total average power dissipation in large sequential circuits. The words accurate and fast are emphasized in both cases to indicate that existing techniques are either inaccurate and fast or accurate and slow. The fact that the first problem is not yet solved has been clearly illustrated in [2]. In this paper, we will argue and demonstrate that the second problem is also still open, and we offer a new method which provides accurate and fast estimation of the total average power of large sequential circuits. Since the power is pattern-dependent, the average power dissipation of a circuit is not well-defined until a specific vector set is chosen. For combinational circuits, this may not be very critical, because different vector sets may dissipate approximately the same power, provided they have approximately equal values of switching activity. Thus, using a set of randomly generated vectors ( the right statistics) may be appropriate for these circuits. However, this does not hold for sequential circuits because a real vector set (as opposed to a randomly generated, artificial vector set) may contain specific vector sequences that put the circuit in specific operational modes or subspaces of its large state space and, in different operational modes, the circuit may dissipate quite different values of power. All one has to do is think of all the many different operational modes of a large microprocessor. Thus, for sequential circuits, the power may be critically dependent on the specific vector sequences that occur during typical operation. Most existing techniques of power estimation consider simply the average switching activity and signal probability of the input signals and use either static probability propagation methods [3] [6] or dynamic Monte Carlo simulation using randomly generated vectors [7], [8]. In either case, one runs the risk of taking the circuit into parts of its state space where it does not belong, i.e., into modes of operation that are unrealistic and may never be exercised in practice. When this happens, there is no guarantee that the estimated power has any relation to what the circuit will actually dissipate under typical operation. To illustrate this problem, we have considered a number of sequential circuits and constructed two sets of input vectors for each. Both sets of vectors have the same switching activity and signal probability for each input node. However, in one vector set, the input signals were generated at random, out any correlation between them, and in the other nonzero correlations were considered, both in space (between pairs of bits in the same vector) and in time (between pairs of consecutive vectors). The intention is that these correlations would mimic to some degree the relationships that typically exist between signals, such as signals resulting from decoded instructions or general control signals. Note that these correlations are only the simplest kinds of correlation relations because they do not model the temporal correlations that can exist in vector streams over several clock cycles. We emphasize /01$ IEEE