Powerline Communication Link and below Layers

Transcription

1 Powerline Communication Link and below Layers Notes by Rui Wang June 11, 2008 Introduction 2 Introduction Introduction Frequency-Shift Keying (FSK) Schemes 5 FSK Modulationthe transmitter side FSK Demodulationthe receiver side Questions for Consideration Spread Spectrum 9 Introduction My View Point From Simple to Complex Assumptions Interference The Vote Strategy Towards the Limit Another Viewpoint on Widening the Data Bit Maximize Code Distance Comparison between Code 1 and Code Temporary Conclusion Packet Synchronization 21 Terminologies and Assumptions The idea The Requirements of the Basic Idea Example 1: α = Example 3: α = Other Examples Bit Synchronization 28 What Why How Remark The Data Bit Recognition Algorithm The Data Bit Recognition and Synchronization Algorithm

2 Introduction 2 / 34 Introduction This talk will be about the principles and technologies below the Network Layer (NL) in our Power Line Communication Networks. Topics included in this talk are: Frequency-Shift Keying (FSK) modulation scheme. Direct-Sequence Spread Spectrum (DSSS). Synchronization. MAC Layer (ML). Link Layer (LL). Please note that I am not an expert in those topics. Up to now, I have not touch any standard textbook or literature about modulation schemes or spread spectrum. I only know what and how FSK and DSSS do algorithmically. For why, my view point may be different from standard and popular understanding. R. EastSoft The Lower Layers in PLC Networks 3 / 34 Introduction For me, talking about the communication techniques is just like waving nife in front of Guangong, like shooting at obscure moving target. The road to becoming an electronic communication wizard is long and arduous, I have not yet take even a small step on that road. Most of you are already at near or more than half way of the road, far advanced than me. Still, I want to give this talk in the hope that inspiring a intensive disputation and discussion about the principles and techniques. you will have fewer struggle and greater pleasure on the way to competent PLC experts. R. EastSoft The Lower Layers in PLC Networks 4 / 34 2

3 Frequency-Shift Keying (FSK) Schemes 5 / 34 FSK Modulation the transmitter side Frequency-Shift Keying (FSK) is a modulation scheme in which digital information is transmitted through discrete frequency changes of a carrier wave. The simplest FSK is binary FSK (BFSK). As suggest by the name, it uses two discrete frequencies to transmit binary (0 s and 1 s) data. The 1 is called the master frequency and the 0 the space frequency. Fig 2.1 illustrates the idea of BFSK. Figure 2.1: Binary Frequency-Shift Keying Modulation Schemes at transmitter side. R. EastSoft The Lower Layers in PLC Networks 6 / 34 FSK Demodulation the receiver side On the receiver side, there is a demodulation circuit (demodulator) to detect the signal of either of the two frequencies. The demodulator output 1 signal level in detecting 1 frequency, and 0 signal level in detect 0 frequency. Note that there is no third output, even if actually there is no signal frequency. These two electricity levels are feeded to CPU for it to sample. Figure 2.2: BFSK Demodulation Schemes at receiver side. R. EastSoft The Lower Layers in PLC Networks 7 / 34 3

4 Questions for Consideration The above is just an abstract model for FSK. In what ideal circumstance can it work, i.e, in which situation if the transmitter transmits 10101, the receiver will indeed get 10101? What might us have to do additionally in real practice (e.g., in power line channel) to implement the idea of the model? What in FSK schemes should be quantified and parameterized in order for further analysis? R. EastSoft The Lower Layers in PLC Networks 8 / 34 Spread Spectrum 9 / 34 Introduction Spread Spectrum techniques are methods to generate more energy for each data bit in transmission. These techniques are used for variety reasons, including for examples: 1. preventing detection by hiding the fact that communication is taking place. 2. the establishment of secure communications 3. increasing resistance to natural interference and jamming. R. EastSoft The Lower Layers in PLC Networks 10 / 34 My View Point I personally don t very agree with that spread spectrum techniques give us more information security in communication. I do agree with that the techniques can provide us with ability to resist noise. This can be explained from more than one points of view, such as energy, processing gain, and error correction code. I also believe that spread spectrum techniques offer us a way to synchronize. In fact the Pseudo Noise code (PN code) or the Pseudo Random Noise code (PRN code) used in the techniques is designed under the constraint to facilitate synchronization. R. EastSoft The Lower Layers in PLC Networks 11 / 34 4

5 From Simple to Complex Spread Spectrum is independent of modulation schemes. That is, Spread Spectrum is not necessarily base on FSK, it can also be implemented the top of other schemes like PSK, ASK, etc. The whole Spread Spectrum technique consists of many contents and thus hard to swallow at once. A system, whatever complicated, is sprouted from a simple seed and experienced a long history of growing during which new facilities shoot out like weeds to tackle practice problems the prototype model does not takes into account. I don t know the development history of Spread Spectrum, I believe there is a such one from simple to complex. In this presentation, I will try to follow a development history I guess or imagine, just for easying your understanding. R. EastSoft The Lower Layers in PLC Networks 12 / 34 Assumptions Let us first assume the following assumptions for FSK: The receiver and the transmitter have been synchronized, i.e., the receiver knows exactly when the transmitter will start to shout out the data. At the transmitter side, a 0 or 1 frequency always last for w seconds. So, at the receiver side, the the pulse produced by the demodulator to represent 0 or 1 has a width of w seconds. The CPU of the receiver samples the pules at a rate of s points per second. Thus, the receiver s CPU gets w/s sample points per data bit. E.g., in Fig. 2.1, the CPU samples at a rate of 8 points/data bit. Next we consider the situation of noisy channels. R. EastSoft The Lower Layers in PLC Networks 13 / 34 Interference If there is no interference caused by the noise or other factors, then knowing the time the transmitter begin to send data out, the receiver can begin to sample at (better at s/2 seconds after) the starting time. Then every successive w/s points would must be either or , representing a 0 or 1 corresponding data bit transmitted by the transmitter. But, practically, some of the points may be flipped, due to the noise interference existing in the channel, the timing difference between the transmitter and the receiver. This will happen in practice because there is no global clock, the local clock may tick at different rates and the synchronization mechanism can only give the receiver an approximate staring-time, leading to the first or the last sample point to be in great danger of being sampled at the pules boundary. R. EastSoft The Lower Layers in PLC Networks 14 / 34 5

6 The Vote Strategy Can the interference and the time-difference mentioned in the previous slide be thoroughly eliminated? not really. We can only try to work correctly in their existence. So, a basic strategy to deal with the interference is by votes. Count the number of 0 points and the number of the 1 points among the w/s points corresponding to a data bit. If there are more 0 points than 1 points then the data bit is reconstructed as 0, if equal we can detect errors but not correct them, otherwise we conclude the data bit is 1. If the interference flips less than half of the sample points of each data bit, the Vote strategy is able to correct all the errors. Otherwise, data bit will be flipped. R. EastSoft The Lower Layers in PLC Networks 15 / 34 Towards the Limit Clearly, that half of the width w of a data bit pulse being interfered is a limit for Vote strategy to work correctly. Theoretically, The Vote strategy needs to sample enough number of points within a data bit to reach the ability limit. However, the CPU used to sample imposes practical limit on sampling rate. A alternate solution is to widen the data bit so that each bit can accommodate more sample points. For example, by doubling the time for 0 and 1 frequencies, the number of sample points for each data bit is doubled. R. EastSoft The Lower Layers in PLC Networks 16 / 34 Another Viewpoint on Widening the Data Bit Doubling the frequency time can be equivalently viewed as before the modulation, each data bit 0 is replaced with 00 and each 1 with 11, i.e., each data bit is repeated in the information, or more generally, considering that we code every data bit with a string, 0 with 00 and 1 with 11. This perspective, though simple, raises more questions for us to consider, and provides us with more space for further investigation and study. R. EastSoft The Lower Layers in PLC Networks 17 / 34 6

7 Maximize Code Distance Available choices for code one bit into two are (symmetric cases omitted): for 0 and 11 for for 0 and 01 for for 0 and 10 for 1 Why repeat?, i.e., why the first?, why not the other two? Code 2 can be eliminated from our consideration because it has a shorter distance between the 0 and the 1 codes. The Hamming distance between two strings of equal length is the number of positions for which the corresponding symbols are different. Larger Hamming distance gives larger possibility to be distinguished. We should select the code in which one code is the complementary of the other. Both Code 1 and Code 3 satisfy the requirement. R. EastSoft The Lower Layers in PLC Networks 18 / 34 Comparison between Code 1 and Code 2 Both has its own advantages and disadvantages. Code 1 just repeats the bits it is to code, there are no changes from 1 to 0 and/or from 0 to 1 within the code. Advantage: Require less exact synchronization. Disadvantage: Unbalance, the transportation ability for data bit 0 is not the same as that for data bit 1, because practical environment and devices are often unbalance, for example, the channel tends to disturb the 0 and 1 frequencies with different strength. Code 3 has the same number of 1 s and 0 s, there are 0-1 and 1-0 changes. Advantage: Balanced, sensitive to bad synchronization. Disadvantage: A small time error in synchronization may lead to some sample points evaluated error values. R. EastSoft The Lower Layers in PLC Networks 19 / 34 Temporary Conclusion To resist interference, a practical solution is to code data bit with strings of reasonable length k. Let s term the strings PN Code. The PN Code for 1 and that for 0 should be complementary so that they have a maximum Hamming distance k. The PN code should have (near) the same number of 0 s and 1 s. For receiving, minimize the number of appearances of 01 and 10 in the PN Code, For synchronization, maximize the number. However, as discussed shortly, there are other requirements from synchronization for PN Codes. R. EastSoft The Lower Layers in PLC Networks 20 / 34 7

8 Packet Synchronization 21 / 34 Terminologies and Assumptions In this section, we adopt the following assumptions and terminologies. Let α denote the PN code for data bit 1 and α the PN code for 0. Call a bit in α or α a chip (bit). The sample rate is s points/second, in the term of chip, c points/chip. R. EastSoft The Lower Layers in PLC Networks 22 / 34 The idea The basic idea for packet synchronization is as follows. The transmitter sends a block S of consecutive 1 s. Typically S 4 B(ytes), called Synchronization head. On the chip level, S = αα... αα, containing S α chips, each data bits being coded into α chips. On the sample point level, we view a data bit as a tring consisting of α c points. This is because each chip generates c points, and each data bit α c points. We will let β be the binary string consisting of the sample points for data bit 1 (i.e., α). The receiver samples α s points, get a binary string γ of length α c = β, equal to the number of points for one data bit. Expecting that γ is a substring of ββ, i.e., a cyclic rotation of string β, the receiver search for the starting position i of γ s appearance in ββ. The starting time the transmitter send out the data bit is where b is time the receiver samples the first ponit and b (i 1)s, 1 i β = γ = α s. R. EastSoft The Lower Layers in PLC Networks 23 / 34 The Requirements of the Basic Idea The position for γ to appear in ββ must be unique. Put another way, every substring of length β of ββ should be distinct, or equivalently, every cyclic rotation of β results in a different string. Note that there are β cyclic rotations of the string β. Considering there are noise interference, we will no longer hope that γ is an exact cyclic rotation of β, Instead we just look among the β rotations for the one most similar to γ. Here the similarity is measured by the Hamming distance. So, it is highly desirable that β should be such that the minimum distance of pairs of the β rotations is maximized. The above requirement is also applicable to the PN code α. That is, we should select such a string α as PN code that the minimum distance between the α rotations is maximized. In the above sense, is certainly not qualified to be a PN code. R. EastSoft The Lower Layers in PLC Networks 24 / 34 8

9 Example 1: α = 3 Figure 4.3: Three-Bit Binary Strings. We can let α = 011, which has cyclic rotations 011, 110, and 101, with that every pair of the rotations has a distance of 2. R. EastSoft The Lower Layers in PLC Networks 25 / 34 Example 3: α = 4 Figure 4.4: 4-Bit Binary Strings. We can let α = 1100, which has cyclic rotations 1100, 1001, 0011, and 0110, with that every pair of the rotations has a distance of 2. One flaw for 1100 being a PN code is that 1100 = 0011 is one of its cyclic rotations. R. EastSoft The Lower Layers in PLC Networks 26 / 34 Other Examples α = 7: α = , which has cyclic rotations , , , , , , and , distance 2 between any two rotations. α = 15: α = The 15 cyclic rotations are , , , , ,..., Distance 8, 0-1 appearances 8. α = 31: α = The 31 cyclic rotations are , , ,..., Distance 16, 0-1 appearances 16. α = 63: α = There are 63 cyclic rotations with distance 32, 0-1 appearances 32. R. EastSoft The Lower Layers in PLC Networks 27 / 34 9

10 Bit Synchronization 28 / 34 What Bit synchronization is proposed to fine tune the (synchronization) time in the process of receiving every data bit of the packet body. That is, after recognized a data bit, bit synchronization may adjust (delay or advance) beginning time for sampling the next data bit by a time interval of a few sample points. R. EastSoft The Lower Layers in PLC Networks 29 / 34 Why When beginning to recognize the packet body, the receiver has been synchronized with the transmitter via the block S traveling ahead of the packet body. However, there may still be some time difference between the two sides (the transmitter and the receiver). The time error left by the packet synchronization. As the basic unit for time adjustment is s seconds, packet synchronization can only theoretically guarantee that the time error is no larger than s/2 seconds. The local clock respective in the transmitter and the receiver are generally tick at different rate, accumulating larger and larger time error between the two sides. The time error can cause sample points error. With a PN code of q 01 and 10 appearances, a time error of r sample points will lead to rq points being flipped. Such error in effect is the as the error cause by noise interference, therefore it weakens the ability of resisting interference. So, it is important to narrow the time error as small as possible, as what be done by bit synchronization. R. EastSoft The Lower Layers in PLC Networks 30 / 34 How There are several ways to do bit synchronization. For Examples: 1. Let the transmitter insert a synchronization block S = 11 between every two successive data bits in the packet body. The receiver can use that block to re-synchronize its time with the transmitter. 2. After Recognizing a data bit x, the receiver try to see whether by advancing or delaying the sample points for that bit x will result in a sample string more similar to β (if x = 1) or β (if x = 0), if yes, advance or delay the starting time to sample the next data bit. R. EastSoft The Lower Layers in PLC Networks 31 / 34 10

11 Remark The first method needs to do work both on the transmitting program and on the receiving program, with heavy computation for synchronization and with extra cost to transport more data bits (the length of the packet is tripled). The second idea is more neat, without the cost on communication. The computation, though seems heavy, can be on-line implemented with high skill and art. Our method is the second. R. EastSoft The Lower Layers in PLC Networks 32 / 34 The Data Bit Recognition Algorithm To save time, Data Bit Synchronization is designed to interleave with Data Bit Recognition algorithm. Alg. 1 on the right describes the Data Bit Recognition in high level, implement details are omitted. It is on line. The basic idea in Alg. 1 is to guess the data bit being transmitted is 1 : on getting the ith sample point x, compare x with the ith bit in the standard sample string β for data bit 1, the ith point contributes 1 to the guess if equal, no contribution otherwise. When finishing the sample for the data bit, check if the total contribute at least half of the total number of sample points, it is 1 if yes and 0 otherwise. Algorithm 1 DataBitRcgntn Require: B is the number of points to be sample within a data bit; A timer has been set to the time for sampling the first point of the current data bit. Ensure: Recognize and write down the data bit transmitted currently. 1: x = 0 2: for 1 i B do 3: Wait for the sample time 4: Sample a point p 5: Set the time to sample the next point 6: if p = β[i] then 7: x = x + 1 8: end if 9: end for [ 10: if x > B 2 11: print 1 12: else 13: print 0 14: end if ] then R. EastSoft The Lower Layers in PLC Networks 33 / 34 11

12 The Data Bit Recognition and Synchronization Algorithm Algorithm 2 Data Bit Recognition and Synchronization Ensure: Recognize and write down the current data bit; and adjust sample time (at most one sample point time) properly. 1: x 1 = x 0 = x +1 = 0 2: for 1 i B do 3: Wait for the sample time 4: Sample a point p 5: Set the time to sample the next point 6: if p = β[i] then 7: x 0 = x : end if 9: if p = β[i 1] then 10: x 1 = x : end if 12: if p = β[i + 1] then 13: x +1 = x : end if 15: end for 16: if x 0 > [ B 2 ] then 17: print 1 18: if max{x 1, x 0, x +1 } = x 1 then 19: delay the timer by one sample time 20: else if max{x 1, x 0, x +1 } = x +1 then 21: advance the timer by one sample time 22: end if 23: else 24: print 0 25: if min{x 1, x 0, x +1 } = x 1 then 26: delay the timer by one sample time 27: else if min{x 1, x 0, x +1 } = x +1 then 28: advance the timer by one sample time 29: end if 30: end if R. EastSoft The Lower Layers in PLC Networks 34 / 34 12