0MPV 8016 S00 / 0MPV 5016 S00 Prototype Manual

Transcription

1 0MPV 8016 S00 / 0MPV 5016 S00 Prototype Manual November 2016 Version 1.0 1

2 Contents 1 Specifications General remarks Connectors / Interface Combined Power & Sense Connector Pin Assignment for 0MPV 8016 S Combined Power & Sense Connector Pin Assignment for 0MPV 5016 S Software Configuration Application Examples Single Channel, 1Load Dual Channel with common Ground, 2 Loads Single Channel, multiple Loads

3 1 Specifications Type Channels Voltage I Max Peak Power 0MPV 8016 S to 16V 5A 50W / ch. 0MPV 5016 S to 16V 5A / 20A 50W / ch W /ch. 4 2 General remarks This manual addresses the special characteristics and features of the MPOD low voltage 0MPV 8016 S00 / 0MPV 5016 S00 prototypes. Therefore only in differences and specialities in functionality and handling of these prototypes will be explained in this document in more detail. For all general considerations and remarks regarding the MPOD HV & LV Power Supply System the MPOD System Technical Manual applies. The latest version of the MPOD System Technical Manual can be downloaded from the WIENER file server at Use the prototype modules with internal sense connection only Due to the experimental feature set of the prototype modules, the regulation of the output voltages using the external sense connection cannot be expected to work stable under all circumstances. It is not recommended to use this mode of operation with the prototype modules. Prototype module outputs do not provide overvoltage protection The outputs are not shortened out internally when deactivated. Due to their output-capacitance the outputs of the prototype module may not instantaneously go to voltage 0 on deactivation. The time interval needed for the outputs to reach 0 depends on the output current. Prototype modules do not support interlock inputs The output channels of the prototype modules do not evaluate the external interlock signal which can be supplied via the top or bottom connector. 3

4 3 Connectors / Interface 3.1 Combined Power & Sense Connector Pin Assignment for 0MPV 8016 S00 Top connector DSUB37 (Channel 0..3) female Pin Signal Comment 1 U0- Channel 0 negative output 20 U0+ Channel 0 positive output 2 U0- Channel 0 negative output 21 U0+ Channel 0 positive output 3 U0- Channel 0 negative output 22 U0+ Channel 0 positive output 4 Do not use 23 Do not use 5 U1- Channel 1 negative output 24 U1+ Channel 1 positive output 6 U1- Channel 1 negative output 25 U1+ Channel 1 positive output 7 U1- Channel 1 negative output 26 U1+ Channel 1 positive output 8 Do not use 27 Do not use 9 U2- Channel 2 negative output 28 U2+ Channel 2 positive output 10 U2- Channel 2 negative output 29 U2+ Channel 2 positive output 11 U2- Channel 2 negative output 30 U2+ Channel 2 positive output 12 Do not use 31 Do not use 13 U3- Channel 3 negative output 32 U3+ Channel 3 positive output 14 U3- Channel 3 negative output 33 U3+ Channel 3 positive output 15 U3- Channel 3 negative output 34 U3+ Channel 3 positive output 16 Do not use 35 Do not use 17 INTERLOCK0 Optional interlock input: The four channels of this connector are 36 INTERLOCK1 enabled only if a signal is applied here 18 LOOP0 Safety Loop, LOOP0 and LOOP1 are connected to each other, no 37 LOOP1 connection to other potentials 19 CHASSIS Connected to chassis / front panel 4

5 Bottom Connector DSUB37 female (Channel 4..7) Pin Signal Comment 1 U4- Channel 4 negative output 20 U4+ Channel 4 positive output 2 U4- Channel 4 negative output 21 U4+ Channel 4 positive output 3 U4- Channel 4 negative output 22 U4+ Channel 4 positive output 4 Do not use 23 Do not use 5 U5- Channel 5 negative output 24 U5+ Channel 5 positive output 6 U5- Channel 5 negative output 25 U5+ Channel 5 positive output 7 U5- Channel 5 negative output 26 U5+ Channel 5 positive output 8 Do not use 27 Do not use 9 U6- Channel 6 negative output 28 U6+ Channel 6 positive output 10 U6- Channel 6 negative output 29 U6+ Channel 6 positive output 11 U6- Channel 6 negative output 30 U6+ Channel 6 positive output 12 Do not use 31 Do not use 13 U7- Channel 7 negative output 32 U7+ Channel 7 positive output 14 U7- Channel 7 negative output 33 U7+ Channel 7 positive output 15 U7- Channel 7 negative output 34 U7+ Channel 7 positive output 16 Do not use 35 Do not use 17 INTERLOCK0 Optional interlock input: The four channels of this connector are 36 INTERLOCK1 enabled only if a signal is applied here 18 LOOP0 Safety Loop, LOOP0 and LOOP1 are connected to each other, no 37 LOOP1 connection to other potentials 19 CHASSIS Connected to chassis / front panel 5

6 3.2 Combined Power & Sense Connector Pin Assignment for 0MPV 5016 S00 Channels 0-3 are operating as separate channels Channel 4, Channel 5, Channel 6 and Channel 7 are operating in parallel; Master is Channel 4 The output connectors of the parallel operating Channels are hard wired internal Top connector DSUB37 female (Channel 0..3) Pin Signal Comment 1 U0- Channel 0 negative output 20 U0+ Channel 0 positive output 2 U0- Channel 0 negative output 21 U0+ Channel 0 positive output 3 U0- Channel 0 negative output 22 U0+ Channel 0 positive output 4 Do not use 23 Do not use 5 U1- Channel 1 negative output 24 U1+ Channel 1 positive output 6 U1- Channel 1 negative output 25 U1+ Channel 1 positive output 7 U1- Channel 1 negative output 26 U1+ Channel 1 positive output 8 Do not use 27 Do not use 9 U2- Channel 2 negative output 28 U2+ Channel 2 positive output 10 U2- Channel 2 negative output 29 U2+ Channel 2 positive output 11 U2- Channel 2 negative output 30 U2+ Channel 2 positive output 12 Do not use 31 Do not use 13 U3- Channel 3 negative output 32 U3+ Channel 3 positive output 14 U3- Channel 3 negative output 33 U3+ Channel 3 positive output 15 U3- Channel 3 negative output 34 U3+ Channel 3 positive output 16 Do not use 35 Do not use 17 INTERLOCK0 Optional interlock input: The four channels of this connector are 36 INTERLOCK1 enabled only if a signal is applied here 18 LOOP0 Safety Loop, LOOP0 and LOOP1 are connected to each other, no 37 LOOP1 connection to other potentials 6

7 19 CHASSIS Connected to chassis / front panel Bottom connector DSUB37 female (Channel 0..3) Pin Signal Comment 1 U4- Channel 4 negative output 20 U4+ Channel 4 positive output 2 U4- Channel 4 negative output 21 U4+ Channel 4 positive output 3 U4- Channel 4 negative output 22 U4+ Channel 4 positive output 4 Do not use 23 Do not use 5 U4- Channel 5 negative output 24 U4+ Channel 5 positive output 6 U4- Channel 5 negative output 25 U4+ Channel 5 positive output 7 U4- Channel 5 negative output 26 U4+ Channel 5 positive output 8 Do not use 27 Do not use 9 U4- Channel 6 negative output 28 U4+ Channel 6 positive output 10 U4- Channel 6 negative output 29 U4+ Channel 6 positive output 11 U4- Channel 6 negative output 30 U4+ Channel 6 positive output 12 Do not use 31 Do not use 13 U4- Channel 7 negative output 32 U4+ Channel 7 positive output 14 U4- Channel 7 negative output 33 U4+ Channel 7 positive output 15 U4- Channel 7 negative output 34 U4+ Channel 7 positive output 16 Do not use 35 Do not use 17 INTERLOCK0 Optional interlock input: The four channels of this connector are 36 INTERLOCK1 enabled only if a signal is applied here 18 LOOP0 Safety Loop, LOOP0 and LOOP1 are connected to each other, no 37 LOOP1 connection to other potentials 19 CHASSIS Connected to chassis / front panel 7

8 4 Software To be able to configure and utilize the special features provided by means of the CLC-Regulation mode, the MPOD low voltage prototypes have to be accessed using a special version of MUSEControl called MUSEControl CLC. This special version can be downloaded from the WIENER file server at Configuration As MUSEControl CLC bases on MUSEControl, only adding the special configuration features for the CLC-Regulation mode, the normal usage does not differ from the latest MUSEControl version. Therefore hereafter only the specialties regarding the CLC-Regulation mode will be explained in more detail. The CLC related features of an output channel can be configured by using the OutputConfiguration dialog of the channel (s. Figure 1). Figure 1: MUSEControl CLC OutputConfiguration dialog 8

9 Beside the standard controls, this dialog also contains the CLC related parameters which are described in Table 1. Parameter Meaning Comment Line Resistance [Ohm] Total resistance of the wires used to connect power supply and Load Measured or calculated line resistance. This value is used to compute the line voltage drop from the measured value of the channels output current (s. Figure 2). CLC Min. Current [A] Lower current bound for CLC-Regulation If the measured value of the channels output current falls below this bound, the CLC-Regulation mode is disabled. The channel then only outputs the nominal voltage as specified (s. Figure 2). CLC Max. Current [A] Upper current bound for CLC-Regulation (clamping) If the measured value of the channels output current exceeds this bound, the CLC-Regulation mode is clamped to a maximum value. The channel then outputs a maximum voltage, defined by this upper current bound and the given line resistance (s. Figure 2). CLC Amp. DiffMin [A] Lower bound for current difference (Slope Amplification) If the measured value of the channels output current changes more than this value in a given time interval, the dynamic behavior of the CLC-Regulation mode is enhanced by increasing the slope of the computed the line voltage drop value to provide a more dynamic reaction to larger current changes (see below). CLC Amp. Factor Amplification factor (Slope Amplification) Amplification factor for enhancing the dynamic behavior of the CLC-Regulation mode during higher changes of the channels output current. In case of a larger current change, the slope of the computed the line voltage drop value is increased by multiplying the current change with this factor. The result is a more dynamic output voltage signal. Increasing this factor to much may lead to an unstable output voltage, especially at higher capacitive loads. Table 1: Parameters related to the CLC-Regulation mode The steady-state behavior of the CLC-Regulation mode is sketched in Figure 2. 9

10 Figure 2: CLC-Regulation scheme (steady-state) To activate the CLC-Regulation mode the parameter Line Resistance has to be set to value which is unequal to 0 and the upper current bound CLC Max. Current needs be set to value greater than zero which matches the desired operating conditions (s. Figure 2). Respectively the CLC-Regulation mode is disabled if one of the two mentioned parameters is set to 0. Also configuring the channel to use the external sense connection will disable the CLC-Regulation mode for that channel. It has to be noted that a channels output voltage will not exceed its maximum nominal value, even if the computed line voltage drop exceeds the range between the specified nominal output voltage and maximum nominal output voltage (s. Figure 2). 10

11 5 Application Examples The following application examples shall demonstrate the characteristics of the CLC-Regulation mode used in der MPOD 0MPV 8016 S00 and 0MPV 5016 S00 prototypes. 5.1 Single Channel, 1Load This application example demonstrates the typical characteristics of the CLC-Regulation mode for a single power supply output channel. Here one resistive load is connected to the power supply channel via a long supply line which has a resistance of approx. 4,3 ohms and an inductance of approx. 60µH. The load is bypassed using a 45µF capacitor located at the point of load. Figure 3 schematically illustrates the used test set-up. Figure 3: Signal output channel test set-up Using the configuration described above, a load step of about 0,2A 0,7A 0,2A was performed. The nominal voltage at load was configured to be 10V. The transients of the load current (Channel 2, blue), the voltage at the load (Channel 1, yellow) as well as the voltage directly at the power supply output (Channel 3, purple) are shown in Figure 4. Figure 4: Transients during load step 0,2A - 0,7A - 0,2A 11

12 The same was done for a smaller load step of about 0,35A 0,525A 0,35A. The nominal voltage at load was configured to be 10V. Again the transients of the load current (Channel 2, blue), the voltage at the load (Channel 1, yellow) and the voltage directly at the power supply output (Channel 3, purple) are shown in Figure 5. Figure 5: Transients during load step 0,25A - 0,525A - 0,25A 12

13 5.2 Dual Channel with common Ground, 2 Loads This application example demonstrates the typical characteristics of the CLC-Regulation mode for two power supply output channels sharing a common ground. Here one resistive load is connected to each power supply channel U2 and U3 via a long supply line. The return path is a common ground line connected at both loads as well as at both power supply output channels. The return line has a resistance of approx. 1 ohm and an inductance of approx. 30µH. The supply lines have each a resistance of approx. 2 ohms and an inductance of approx. 30µH. Both loads are bypassed using a 45µF capacitor located at the point of load. Figure 6 schematically illustrates the used test set-up. Figure 6: Dual output channel test set-up with 2 loads Using the configuration described above, several combinations of load steps of about 0,35A 0,525A 0,35A and constant current loads were performed. The nominal voltage at load was configured to be 10V. The transients of the voltage at the load connected to output channel U2 (Channel 1, yellow) as well as the voltage at the load connected to output channel U3 (Channel 3, purple) are shown in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11. Figure 7: Transients for U2: 0,35A 0,525A 0,35A, U3: 0,35A 0,525A 0,35A Figure 8: Transients for U2: 0,35A 0,525A 0,35A, U3: 0A constant 13

14 Figure 9: Transients for U2: 0,35A 0,525A 0,35A, U3: 0,5A constant Figure 10: Transients for U2: 0,5A constant, U3: 0,5A constant Figure 11: Transients for U2: 0,5A constant, U3: 0A constant 14

15 5.3 Single Channel, multiple Loads This application example demonstrates the typical characteristics of the CLC-Regulation mode for one power supply output channel with multiple loads connected in parallel. Here 12 resistive loads are connected to the power supply channel U4 via long parallel supply lines. The return path is modeled as 12 ground lines in parallel. The supply lines and loads are modeled as one single load supplied by one single line and 11 loads supplied by one wire each. All 12 supply lines are connected in parallel at the power supply. The return path has a resistance of approx. 0,166 ohm and an inductance of approx. 30µH. The supply line for the single load has a resistance of approx. 2 ohms and an inductance of approx. 30µH.The 11 parallel supply lines have a resistance of approx. 0,184 ohms and an inductance of approx. 30µH. Each load is bypassed using a 45µF capacitor located at the point of load. Figure 12 schematically illustrates the used test set-up. Figure 12: Single output channel test set-up with 12 loads Using the configuration described above, several combinations of load steps of about 3,85A 5,8A 3,85A and constant current loads were performed. The nominal voltage at load was configured to be 10V. The transients of the voltage at the single load connected to output channel (Channel 1, yellow) as well as the voltage at the 11 parallel loads (Channel 3, purple) are shown in Figure 13, Figure 14, Figure 15, Figure 16 and Figure

16 Figure 13: Transients for 11 loads: 5,8A 3,85A 5,8A, single load: 0A constant Figure 14: Transients for 11 loads: 0A constant, single load: 0,35A 0,525A 0,35A Figure 15: Transients for 11 loads: 5,8A 3,85A 5,8A, single load: 0,35A 0,525A 0,35A Figure 16: Transients for 11 loads: 5,8A constant, single load: 0,35A 0,525A 0,35A Figure 17: Transients for 11 loads: 5,8A 3,85A 5,8A, single load: 0,525A constant 16