Date: 25 April, Abstract:

Transcription

1 Date: 25 April, 2011 Abstract: Bit patterned media (BPM) recording is a possible option for the recording at the density of Tb/in 2. The writing in BPM system experiences the unique error types due to write-in errors. Due to the head field gradient, adjacent bits may be erroneous causing substitution errors. Previous works focus on the use of lowdensity parity-check (LDPC) codes to improve the performance and the write margin. Given the write-error probability p, the log-likelihood ratio (LLR) information can be modified for the LDPC decoder. In practice, the soft-output Viterbi algorithm (SOVA) detector precedes the LDPC detector, therefore, the SOVA detector can handle these errors as well. In this work, we propose two approaches to tackle this issue. In the first method, given p, the LLR at the input of the SOVA detector is modified. The performance and write margin improvement at various conditions will be illustrated. When p is unknown, the window-based Viterbi or SOVA detector can be used to estimate the optimal p to yield the lowest bit error rate (BER) performance. In the second method, we propose the use of mixed scheduling method of LDPC codes to improve the system performance. The forward and backward scheduling based on check nodes are analyzed and mixed to improve the LDPC decoder. In addition, we will simulate a BPM system with substitution errors from adjustable recording parameters. Proponent(s) and affiliation(s): Name/Title: Assoc. Prof. Pornchai Supnithi Affiliation : Telecommunication Engineering Department, Faculty of Engineering and College of Data Storage Innovation King Mongkut s Institute of Technology Ladkrabang THAILAND Designated contact person: Assoc. Prof. Pornchai Supnithi

2 I. Modified SOVA detector and scheduled LDPC decoder for bit patterned media with written-in errors a) Complete description of the research matter and its connection with ASTC stated goals Related ASTC topic: BPM Coding and Detection for BPM Recording System Bit patterned media (BPM) storage appears as a candidate for the future magnetic recording at the areal density of Tb/in 2. However, there remain a number of challenges to be tackled before the BPM system becomes possible for reliable and mass-produced disk drives. Signal processing and coding designed to handle BPM-specific issues such as written-in errors is one important area. The written-in errors in BPM system can be categorized into two types corresponding to their root causes. Firstly, for an island, there is a time window that recording can be done successfully. Due to fluctuations of the switching field, the disturbing fields from neighboring islands and position fluctuations, the writing may occur outside this specific time window. The accumulative phase shift can cause the insertion/deletion errors [1-2]. Secondly, the switching field of each island needs to be smaller than the head field. Otherwise, the bit cannot be recorded. But due to variations of the switching field and the demagnetization field, this requirement may not always be satisfied, and the substitution errors may appear [3-4]. In this research proposal, we focus on the substitution errors. The fundamental recording concepts of bit patterned media are that the head field must be large enough to saturate the target dot that is being written and, simultaneously, the field must not re-switch the polarity of the previously written dot, small enough to avoid re-magnetization [5]. The worst situation takes place when the dot magnetization is in parallel and the magneto-static field (demagnetization field) reduces head field. The ideal recording satisfies the condition Hmax Hd Hc, (1) where the applied head field is H max, the demagnetization field from adjacent dot is H d and the media coercivity is H c. Figure 1 shows the writing scheme for the write error

3 channel. Fig. 1. The write error scheme for write error channel [5]. In the figure, the main pole of the writing head is located above the dots, and its trailing edge is at the center of dot#3, target dot. Figure 1(a) shows the occurrence of the write error at the previous dot when the write head position shift to left. With regard to the condition that the magnetization of the previous dot be unchanged, there is no limitation in the parallel magnetization situation, because the same polarity field never switches back. For the anti-parallel case shown in the figure, the grey arrow of dot#2 has different polarity with two neighboring dots so the demagnetization field from dot#1 and dot#3 increase the head field. If the head field gradient larger than the media coercivity of dot#2, the dot magnetization is switched to the same direction as the head field, the dashed arrow has shown. HMAX ( Xdp x2) dh Hd1 Hd 3 ( Hc Hc2) dx (2) In the figure 1(b), we focus the occurrence of the write error at dot#3, the target dot when the write head position shift to right. The adjacent dots have the parallel magnetization with centre dot, the demagnetization field from dot#2, dot#4 reduced the head field. Therefore, the head field is not large enough to write the target dot. HMAX ( Xdp x3) dh Hd 2 Hd 4 ( Hc Hc3) dx

4 (3) We assume that the each dot has the inherent fluctuations such as the SFD ( ) and the demagnetization field coercivity H. The dot position field c Hc H d which are the deviation of the standard media x has the standard deviation position. The head H MAX for each dot decreases with the distance from the trailing edge of head according to the head field gradient dh / dx [6]. We consider a discrete-time BPM channel with written-in errors [7] as shown in Fig. 2. The model for BPM channel with write-in errors can be considered a composite channel of a binary symmetric channel (BSC) and an additive white Gaussian noise (AWGN) channel, where a k is the information sequence, b k is the actual written data, x k is the mapped sequence from {-1,1}, n k is the additive white Gaussian noise (AWGN) with zero mean and unit variance, and y k is the noisy readback sequence. We assume thatp a b q 1 p, i.e., the crossover probability of the binary symmetric channel (BSC) is p. k k a k BSC p b k x k + n k y k Fig. 2. The discrete-time channel model of BPM with the written-in errors Most works [6-9] so far have focused on the use of the binary or nonbinary LDPC codes to improve the BER performance or the write margins in the case of substitution errors. In [6], the error locators are determined from the log-likelihood ratio (LLR) at the LDPC decoder, so the write-errors are corrected. In [6],[8], the binary and nonbinary LDPC codes are shown to widen the write margin as a function of the writer offset. In [9], given the write-error probability p, the LLR at the input of the LDPC decoder is modified to give the better performance. The method in [9] is summarized in Fig. 3.

5 a k BSC p b k LDPC encoder c k x k + n k y k LDPC decoder p a ˆk Fig. 3. The LDPC decoder with modified LLR for BPM system with written-in errors. b) Proposed research approach(es) i. Computational Since in the read channel of the BPM channel, the soft-output Viterbi algorithm (SOVA) detector, or alternatively, BCJR algorithm, is used to handle the intersymbol interference (ISI) as well as the intertrack interference (ITI), it is placed before the LDPC decoder. Therefore, we will modify the SOVA detector based on the writeerror probability p. If this probability is unknown, then the window-based Viterbi/SOVA detector can be used to estimate the probability ˆp. Given p, the BER performance degradation due to the mismatched probability at various write-error conditions and SNR levels can be shown. The first proposed system is shown in Fig. 4. a k BSC p b k LDPC encoder c k H(D) x k n k + y k SOVA ˆp x ˆk LDPC decoder a ˆk Estimate p Fig. 4. The SOVA decoder with modified LLR for BPM system with written-in errors. Traditional method to decode LDPC codes is based on belief propagation (BP) method. The LDPC decoder can be improved via serial scheduling methods. In the BP algorithm, all check nodes propagate the reliability information to their connected

6 variable nodes simultaneously before the propagation of updated information L(q ij ) from the variable nodes can start. In Fig. 5, the information exchange between the check nodes and variable nodes are shown. (a) (b) Fig. 5: The exchange of reliability between the nodes over a Tanner graph. The layered belief propagation(lbp) algorithm [10]. Unlike the BP algorithm, the LBP algorithm applies a different scheduling method to update the check nodes. For the LBP strategy, after each check node c j passes the reliability information to its connected variable nodes, then each of these variable nodes will send the updated information to their connected check nodes, except the check node c j. Figure 6 shows a graphical illustration of the LBP strategy based on the Tanner graph in Fig. 5. The check node c 1 will first propagate the reliability information to the variable node v 1, v 5 and v 8, respectively, as shown in Fig. 6(a). Afterward, the information is sent from the variable node v 1, v 5 and v 8 to the check node c 6, c 2 and c 5, respectively, as shown in Fig. 6(b). An iteration of the LBP (a) (b) Fig. 6: Illustration of the LBP strategy.

7 strategy is finished after all the check nodes completely propagate the information L(r ji ). Shuffled belief propagation (SBP) [11] is another type of serial scheduling, which also converges faster than the traditional BP decoding. The shuffled belief propagation (also called the vertical shuffle scheduling) is used to sequentially update the variable nodes instead of the check nodes in LBP. The graphical illustration of the SBP strategy is shown in Fig. 7. For the LBP strategy, each check node will propagate all the information L(r ji ) to its connected variable nodes. On the other hand, the SBP strategy does not schedule to propagate all the L(r ji ) from the same check node c j but will schedule to propagate L(r ji ) from the check nodes connected to a variable node as shown in Fig. 7(a). Afterward, this variable node will send back the information to all the connected check nodes as shown in Fig. 7(b). An iteration of SBP strategy will be counted after all variable nodes are completely updated. (a) Fig. 7. Illustration of the SBP strategy. (b) c) Likely outcome of research i. An alternative method to handle the write-error in BPM channels with the SOVA detector ii. An algorithm to estimate the write-error probability on the receive side using window-based Viterbi/SOVA detector iii. Obtain a mixed scheduling method for the LDPC decoder which is superior to the serial schedulings for the BPM channels with and without write-errors. II. Resources required to perform project a) 2 graduate students

8 b) personal computer with high-processing capability c) MATLAB, C-language software III. Resources other than ASTC funding dedicated to perform project A small part of this project is being funded by National Electronics and Computer Technology Center (NECTEC), Thailand at the moment. However, the funding will end on September 30 th. IV. Resources requested from ASTC and how they will be utilized a) Funding Budget Category 1 st Year ($) 2 nd Year ($) Total Category 1 Honorarium for Research Team 1. Assoc. Prof. Dr. Pornchai Supnithi 10,000 10,000 20,000 Total: Category 1 10,000 10,000 20,000 Category 2 Student Stipends and tuitions 1. Ms. Warangrat Wiriya 8,000 8,000 16, Mr. Watid Phakphisut 8,000 8,000 16,000 Total: Category 2 16,000 16,000 32,000 Category 3 Expense for Material and others 1. Materials Computer-related such as hard disks, RAM, monitor Office-related such as papers, printer cartridges, CD-ROMs, etc. 2. Traveling expense 3,000 3,000 6,000 Conference/Workshop/Seminar/Progress 13,000 13,000 26,000 Update Total: Category 3 16,000 16,000 32,000 Total: Category ,000 36,000

9 Budget Category 1 st Year ($) 2 nd Year ($) Total 72,000 Category 4 Project Administration fee (overhead = 15% of total project budget) 6,353 6,353 12,706 GRAND TOTAL 42,353 42,353 84,706 ** The budget above does not include the expense related to the students internship, if it possible. b) Expected technical cooperation with sponsor(s): materials to be provided by sponsor(s) (e.g., targets, devices, engineering support, etc.) b.1) Specification of various channel parameters b.2) Specification of island size, track pitch, reader geometry suitable for the areal density in the range of Tb/in 2 c) Sponsors facility utilization None d) Expected students internships Summer of 2012 V. Time line Research Plan 1.1 Derive the new LLR at the input of the SOVA detector which incorporates the writeerror probability p Months Simulate BER performance of (1.1) for various p

10 1.3 Investigate the bit error statistics of the forward and backward schedulings based on check nodes of layered belief propagation (LBP) 2.1 Simulate the write-error margin using (1.1) for various p Develop the write-error estimation method based on windowed Viterbi/SOVA detector 2.3 Develop a mixed scheduling method based on (1.3) 3.1 Simulate the BPM system with substitution error events due to adjacent bit writing error (head field gradient, coercivity, demagnetization can be adjusted) Evaluate the performance of the (1.1) and (2.2) in a full BPM system in (3.1) Evaluate the performance of the (2.3) in a full BPM system in (3.1) 4.1 Investigate the hardware side of the proposed method in (1.1), (2.2) and (2.3) 19-24

11 VI. Not more than one page: Home institutions & resources King Mongkut s Institute of Technology Ladkrabang (KMITL), THAILAND Project location 1. Telecommunications Engineering Department, Faculty of Engineering, KMITL. 2. Research Unit on Signal Processing and Advanced Data Storage, College of Data Storage Technology Innovation, KMITL. VII. Not more than one-half page per contributor: contact information and biographical sketch of researcher. Project Leader: Assoc. Prof. Pornchai Supnithi Contact Information: Telecommunication Engineering Department, Faculty of Engineering King Mongkut s Institute of Technology Ladkrabang No. 1 Soy Chalongkrung 1, Ladkrabang, Bangkok 10520, THAILAND Tel: Fax: ksupornc@kmitl.ac.th, pornchai.supnithi@gmail.com Website: Dr. Pornchai Supnithi received the B.S. degree from University of Rochester, New York, USA, in 1995, M.S. degree from University of Southern California, Los Angeles, California, USA, in 1997 and Ph D. from Georgia Institute of Technology, Atlanta, Georgia, USA, in 2002, all in electrical engineering. Since 2003, he has been with the Telecommunications Engineering Department, King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok, Thailand. He was promoted to Associate Professor in His current research interests are in the area of signal processing and coding techniques for communication and data storage technology. In addition, he is

12 interested in ionospheric/tropospheric study with applications in satellite communication and aeronautical aviation Graduate student: 1. Mr. Watid Phakphisut (Doctoral student) 2. Ms. Warangrat Wiriya (Master student) (Same contact information as above)

13 Reference 1. Y. Tang et al., IEEE Trans. Magn., vol. 45, no. 2, pp , Feb H. J. Richter et al., IEEE Trans. Magn., vol. 42, no. 10, pp , Oct S. Zhang et al., IEEE Trans. Magn., vol. 46, no. 6, pp , Jun K. Takano and M. Sakai, Relationship between head design and media remanent magnetization in perpendicular magnetic recording, IEEE Trans. Magn., vol. 43, no. 2, H. Muraoka, S. J. Greaves, and Y. Kanai, Modeling and simulation of the writing process on bit-patterned perpendicular media IEEE Trans. Magn, 44, , November Y. Nakamura et al., Performance evaluation of LDPC coding and iterative decoding system in BPM R/W channel affected by head field gradient, media SFD and demagnetization field, Digest of PMRC 2010, pp , Sendai, May J. Hu, et al., Bit-patterned media with written-in errors: modeling, detection and theoretical limits, IEEE Trans. Magn., vol. 43, no. 8, pp , Aug Y. Nakamura et al., A study on NB-LDPC coding in BPM R/W channel, IEEE Intermag 2011, EU-04, Taipei, Taiwan. 9. Y. Nakamura et al., A Study of LDPC Coding and Iterative Decoding System in Magnetic Recording System Using Bit-Patterned Medium With Write Error, IEEE Trans. Magn., vol. 45, no. 10, pp , Oct A.R. Iyengar, P.H. Siegel and J.K. Wolf, LDPC codes for the cascaded BSC-BAWGN channel, The 47th Annual Allerton Conference on Communication, Control and Computing, Sep. 2009, Monticello, IL, USA. 11. D.E. Hocevar, "A reduced complexity decoder architecture via layered decoding of LDPC codes," in Proc. IEEE Workshop Signal Process. Syst. (SIPS), pp , M. Fossorier, "Shuffled belief propagation decoding," in Proc. 36th Asilomar Conf. Signals, Syst. and Comput., pp. 8-15, 2002.