PARALLEL AND SERIAL LDPC DECODERS FOR WIFI AND WIMAX RECEIVERS

Transcription

1 Chuyên san Công nghệ thông tin và Truyền thông - Số (4-205) PARALLEL AND SERIAL LDPC DECODERS FOR WIFI AND WIMAX RECEIVERS Nguyen Tung Hung, Nguyen Van Duan 2, Do Quoc Trinh 2 Abstract In this paper, we introduce new parallel and serial LDPC decoders with predefined parity check matrices and adaptive channel LDPC decoders with equivalent parity check matrices based on channel information. Simulation results show that these new decoders can improve the performance of WiFi and WiMAX receivers with acceptable complexity. Bài báo giới thiệu các bộ giải mã LDPC nối tiếp và song song với ma trận kiểm tra xác định trước và bộ giải mã LDPC thích nghi với ma trận kiểm tra được tính toán dựa trên thông tin của kênh truyền. Kết quả mô phỏng cho thấy các bộ giải mã mới này có thể nâng cao chất lượng của máy thu của hệ thống WiFi và WiMAX với độ phức tạp chấp nhận được. Index terms LDPC code, soft syndrome, parallel LDPC decoder, parallel LDPC decoder, trapping set.. Introduction LDPC codes were invented by Robert Gallager [] in the early 0 s and have received widespread adoption in next-generation wireless standards such as IEEE 802.n (WiFi) [2], IEEE 802.e (WiMAX) [] and in many other applications to improve both bandwidth efficiency and reliability. LDPC decoding is an iterative decoding algorithm called BPA (Belief Propagation Algorithm) []. In BPA decoding, dominant failures are generally caused by trapping sets [4]. The trapping sets are formed by a combination of short cycles in the Tanner graph [5] of parity check matrix H. To reduce the influence of trapping sets, some researchers proposed decoding algorithms that consist of two stages. In the first stage, the BPA decoding is carried out; if codeword is invalid after a maximum number of iterations, the second stage will be executed. In the second stage, [], [7] propose a re-decoding method using G-LDPC decoder while [8], [9], [5] use the Ordered Statistic Decoding technique (OSD) and adaptive BPA- OSD. The disadvantage of these methods is too complex and difficult to implement with great length LDPC codes and furthermore they have a post-processing delay as the decoding process requires two-stage. With the word adaptive regarding following channel LDPC decoder in this work, we mean the ability of an LDPC decoder to improve the performance by using different parity check matrices, calculating based on original parity check matrix and channel information. ()Telecommunications University. (2)Le Quy Don Technical University. 84

2 Tạp chí Khoa học và Kỹ thuật - Học viện KTQS - Số 7 (4-205) The paper introduces parallel and serial decoders with predefined and adaptive channel parity check matrices which can be applied in WiFi and WiMAX to improve the performance with acceptable complexity. The paper is organized as follows. Section 2 provides a brief introduction to LDPC code, parity check matrix H and BPA decoding. Section gives an overview of equivalent parity check matrix and equivalent decoder. Section 4 proposes parallel and serial LDPC decoders based on predefined parity check matrices and equivalent check matrices. Section 5 presents an overview of adaptive channel LDPC decoders classifying them on the calculation methods and decoding schedules. Section compares the simulation results and complexity between proposed decoders and conventional LDPC decoder in WiFi and WiMAX receivers. Finally, section 7 draws the conclusions. 2. LDPC code LDPC codes are a special class of linear block codes. An LDPC code can be represented by a m n sparse matrix (m = n k), usually called H matrix. In following, binary error coding for BPSK modulation and AWGN channel is considered. Information bits u = u, u 2,..., u k are encoded into a codeword Y = y, y 2,..., y n, then modulated and transmitted through the channel. After that, we obtain the corrupted sequence x i = 2y i + z i at the receiver, where z i is an independent Gaussian random variable with a distribution of N(O, s 2 ). The input of the BPA decoder is the channel information (Log Likelihood Ratio- LLR): where P r( ) is the conditional probability. L in (ŷ i ) = log P r(x i ŷ i = ) P r(x i ŷ i = 0) = 2x i σ 2 () The H matrix contains mostly zeros and a small number of s and can be described by a bipartite Tanner graph with the Bit Nodes () v, v 2,..., v n and the Check Nodes (Check Node) s, s 2,..., s m. Corresponding to the locations of H with the value "", there is a connection between the and the. BPA is an iterative decoding algorithm with two main phases: ) make calculation in rows to update information for all and send information from to, 2) make calculation in columns to update information for and send information from to. In each iteration, the output of the BPA decoder is the LLR of bits L out (ŷ i ), which is used for hard decision to become a codeword Ŷ = (ŷ, ŷ 2,..., ŷ n ). If the syndrome is: s = Ŷ.HT = [0, 0,..., 0] (2) the process will stop and give a valid codeword. Otherwise, the process repeats until the number of iterations I reaches the maximum value I max.. Equivalent LDPC decoder Definition. The equivalent parity check matrix H e of the parity check matrix H of size m n [0] is a matrix of size of (m + E) n under the form: [ ] H H e = () Ha 85

3 Chuyên san Công nghệ thông tin và Truyền thông - Số (4-205) where H is an additional matrix with E rows and n columns, each row is obtained from the sum of any two rows of the matrix H. From the theory of linear codes, we have: is a system of linear equations, so we also have: Y.H T = [0, 0,..., 0] (4) Y.H e T = [0, 0,..., 0] (5) Thus H e is a parity check matrix of the equivalent LDPC code. If E m, H e is a sparse matrix and the decoder with H e is called an equivalent LDPC decoder. Perfomance of equivalent LDPC decoder is not good as conventional LDPC decoder because of many sort cycles with girth 4 maybe exist in the Tanner grapth (usually eliminated in H). The authors in [], [7], [] provide the method of combination of into Super Check Nodes (S), so that information from the error-free TS can correct the error TS for the Margulis code (240,20). The parity check matrix generated by adding modulo 2 of the matrix rows corresponding to the combination of is called generalized - parity check matrix. The decoder with generalized - parity check matrix is called G-LDPC (Generalized - LDPC decoder). Thus, the equivalent parity check matrix is a case of G-LDPC and redundant parity check matrix []. The disadvantage of the above methods is the it requires to predefine the most dominant TS. If the length of the LDPC code is large, the calculation to find TS will be very complicated. On the other hand, at the low E b /N 0, a frame error event usually contains a combination of multiple TS and different TS have not been considered yet. In [4], the authors introduced Multiple-basesbeliefpropagation (MBBP) algorithm which has M LDPC decoders with different equivalent matrices working in parallel setting. In [] a general method to construct a set of equivalent parity-check matrices for PEG-constructed codes and in [4] a novel approach for WiMAX LDPC codes were presented. These works were focused on predefined equivalent parity check matrices that means these matrices are not changed in the decoding process. Contrary, in this paper we present a simple method to construct a set of adaptive equivalent parity-check matrices based on the order of soft syndrome and the order of reliabilities of bits for any LDPC codes (the structure of these matrices depends on receiving information (LLR) from the channel). In [0], we proposed G-LDPC with the Oder of Soft Syndrome (G-LDPC-OSS) algorithm does not have to predefine dominant TS. The performance of the G-LDPC-OSS algorithm is better than BPA, G-LDPC and can approach the MLD (Maximum Likelihood Decoding) performance. The G-LDPC-OSS algorithm consists of two stages. In stage, decode LDPC with the input of () using the BPA algorithm with the conventional check matrix H. In stage 2, compute H e based on the Oder of Soft Syndrome using output of the stage and re-decode (). The disadvantage of the above method is that they have a post-processing delay. Next sections present different methods to calculate equivalent parity-check matrices and apply to the different LDPC decoder architectures. 4. Parallel and Serial LDPC decoders Fig. and Fig.2 describe the diagram of a Parallel decoder (P-decoder) and Serial decoder (S-decoder). P-decoder contains M LDPC decoders working in parallel mode as shown in 8

4 Tạp chí Khoa học và Kỹ thuật - Học viện KTQS - Số 7 (4-205) Fig.. The first decoder is a conventional LDPC decoder and M other decoders use M different equivalent parity matrices with each additional matrix H γ use M - different equivalent parity matrices with each additional a (γ = matrix, 2,..., MH a ) obtained ( =... from M -the ) obtained modulo-2 from sum the modulo-2 of E rows sum and of E different rows and rows E different of H. rows In the of process H. In of parallel the process decoding, of parallel if onedecoding, of the decoders if one of the satisfies decoders (4), satisfies the process (4), the will process stop and will give stop and a valid codeword. give a valid If all codeword. of the decoders If all of are the decoders in trapping are sets, in trapping the codeword sets, the selector codeword will selector select will invalid codeword with the least errors, according to the first decoder (conventional LDPC decoder select invalid codeword with the least errors, according to the first decoder (conventional with H which usually has not girth 4). LDPC decoder with H which usually has not girth 4). Fig. Fig.. The parallel LDPC decoder Fig.2a showcases an S-decoder. This decoder has M LDPC decoders with equivalent Fig.2a showcases an S-decoder. This decoder has M LDPC decoders with equivalent parity parity matrices, working in serial mode. At the first time of decoding, codeword selector matrices, working in serial mode. At the first time of decoding, codeword selector stores the stores the code word of conventional LDPC decoder with H. In the number of times of code word of conventional LDPC decoder with H. In the number of times of decoding γ, the additional decoding matrix, the Hadditional γ matrix H a is obtained from the sum of E rows and E different a is obtained from the sum of E rows and E different rows of H. In each decoder, rows of if H. () In is each satisfied, decoder, stop if the() decoding is satisfied, process stop give the decoding the valid codeword. process give Otherwise, valid the codeword. selector Otherwise, will the select codeword invalidselector codeword will select with invalid the least codeword errors, with according the least toerrors, the first decoder according (conventional to the first LDPC decoder decoder (conventional with H). LDPC Fig.2b decoder showcases with H). a practical Fig.2b showcases serial decoder a with practical only one serial decoder decoder working with only in iterative one decoder mode. working This decoder in iterative is simpler mode. This thandecoder a P-decoder, is butsimpler it has than a delay a P-decoder, because but of re-decoding. it has a delay because of re-decoding. 5. Parallel and serial adaptive channel LDPC decoders In conventional and above parallel or serial LDPC decoders, the parity check matrix is predefined and not changed in the decoding process. In this section, we propose two types of adaptive channel LDPC decoders (parity a) check matrix depends on the channel): Parallel Adaptive (PA-decoder) channel decoder and Serial Adaptive (SA-decoder) channel decoder. PA-decoder is a P-decoder with equivalent parity matrices based on Least Reliable Basis (LSB) and Most Reliable soft Syndromes (MRS), where the LSB is the ascending order of absolute values of L in (ŷ i ) and MRS is the descending order of absolute values of soft syndrome defined as follows. b) Fig.2 The serial LDPC decoder 4 87

5 a rows of H. In each decoder, if () is satisfied, stop the decoding process give the valid codeword. Otherwise, the codeword selector will select invalid codeword with the least errors, according to the first decoder (conventional LDPC decoder with H). Fig.2b showcases a practical serial decoder with only one decoder working in iterative mode. This decoder is Chuyên san Công nghệ thông tin và Truyền thông - Số (4-205) simpler than a P-decoder, but it has a delay because of re-decoding. a) b) Fig.2 The serial LDPC decoder Fig. 2. The serial LDPC decoder Definition. The soft syndrome defined in [0] is the LLR of the check nodes s i=,2,...m with: L(s i=,2...m ) = log Pr (s i = L (ŷ j=,2...n )) () Pr (s i = 0 L (ŷ j=,2...n )) We have: 4 s i = (ŷ j H (i, j)), j V i, i =...m (7) where V i is the set of branches connecting from bit node to check nodes on Tanner graphs (where the i th row of the matrix H has a value of "") and the calculation is the modulo 2 operator. Based on the studies of LLR algebra in [], [2], we have: (e L(ŷ j ) +)+ j V i L(s i ) = log (e L(ŷ j ) +) j V i sign (L(ŷ j )). min L(ŷ j ) j V j V i i j V i (e L(ŷ j ) ) j V i (e L(ŷ j ) ) The first equivalent parity matrix H a is obtained from modulo-2 sum of E check nodes related and first e consecutive bit nodes in the LRB with the first E consecutive check nodes in MRS. The next equivalent parity matrix H γ a is obtained by next different e consecutive bit nodes in the LRB. Fig. describes an example of creating H γ a with assumptions of e = 2, M = 2 on a Tanner graph established from an H matrix whose rows and columns are permuted by π and π according to the MRS and LRB, respectively. The H a matrix is created by modulo - 2 sum of the E(π, π2 ) rows and the E(π, π4 ) rows that are related to e(π, π2 ). The matrix H 2 a is created by modulo - 2 sum of the E(π, π2, π ) rows and the E(π4, π5, π ) rows that are related to e(π, π4 ). In order to generate more H γ a, we can replace the next first rows in MRS. Consider the case of the BPA decoder falling into the TS with the error bit node π (least Reliable Bit) and sign of relevant node π are not large enough to change the sign of π as 88 (8)

6 According to (8), the bits corresponding to the bit node connected to the node will (least Reliable Bit) and sign of relevant node are not large enough to change the sign of be the most reliability and less prone to error bits. If combine node with, the most as shown in Fig. and assuming the node is the node with the largest. reliable information from highly reliable bit nodes will be passed through to, According to (8), the bits corresponding to the bit node connected to the node will allowing recovery from the trapping set Tạperror chí Khoa event. học và Kỹ thuật - Học viện KTQS - Số 7 (4-205) be the most reliability and less prone to error bits. If combine node with, the most reliable information Ascending from order highly reliable bit nodes will be passed through to, allowing recovery from the trapping set error event. 2 4 Ascending order Bit nodes Bit nodes 2 4 Descending order Check nodes Fig.. The Tanner graph of matrix H with permuted Descending order Fig.. The Tanner graph rows of and matrix columns H with permuted rows and columns Fig.. The Tanner graph of matrix H with permuted Fig. 4 describes an SA-decoder rows (is and the columns same as G-LDPC-OSS in [0]). This decoder shown has in two Fig. stages: ) decode by the conventional LDPC decoder and 2) decode by decoders with Fig. and 4 describes assuming an SA-decoder the node (is π the is the node with the largest π. According to (8), the equivalent bits corresponding parity check tomatrices bitbased nodeon π same as G-LDPC-OSS in [0]). This LSB and MRS calculated at the output of the connected to the node π decoder has two stages: ) decode by the conventional LDPC decoder and will be the most reliability conventional and less LDPC prone decoder to error L ˆ out( yi). bits. In the If second combine stage, node the equivalent π 2) decode by decoder can work in with π decoders with the equivalent parity check matrices based on LSB and MRS calculated at the output, theof most the reliable information parallel conventional or from serial LDPC highly mode decoder and reliable codeword L bit ˆ selector nodesoperates will bein passed the same through above way. π to π, allowing out( yi). In the second stage, the equivalent decoder can work in recovery from the trapping set error event. parallel or serial mode and codeword selector operates in the same above way. LLR LLR LDPC decoder LDPC ( H decoder ) ( H ) 5 LDPC decoder LDPC ( H decoder e ) H ) ( e Check nodes Codeword Codeword selector selector Fig.4 The serial adaptive channel LDPC decoder Fig.4 The serial adaptive channel LDPC decoder Fig. 4. The serial adaptive channel LDPC decoder.. Performance and and complexity of proposed decoders In the are in Fig. 4 describes In the next-generation an SA-decoder wireless (is communication the same as G-LDPC-OSS systems, codes in [0]). are adopted This decoder in has two stages: wireless ) metropolitan decode by area the network conventional (WMAN) LDPC IEEE 802.e decoder WiMAX and 2) standard decode and and bywireless decoders with the equivalent local local area area network parity check (WLAN) matrices IEEE 802.n based WiFi on LSB standard. andboth MRS standards calculated have various at the code output of the lengths and and code code rates [2], []. conventional LDPC decoder L out (ŷ i ). In the second stage, the equivalent decoder can work in parallel or serial mode and codeword selector operates in the same above way.. Performance and complexity of proposed decoders In the next-generation wireless communication systems, LDPC codes are adopted in wireless metropolitan area network (WMAN) IEEE 802.e WiMAX standard and wireless local area network (WLAN) IEEE 802.n WiFi standard. Both standards have various code lengths and code rates [2], []. Fig. 5 depicts simulation results for the WiFi LDPC code with a code rate R = /2, length n = 48 bits and n = 944 bits with the assumption of I max = 00 (maximum number of iterations in LDPC decoding) and M = 20 corresponding to E b /N 0 =.5 db (E b is bit 89

7 should choose e = and for the WiFi LDPC code with length n = 944 bits, we should choose e = 2. We can see that the value of E is depend on positions of e bits in the LSB. For the first code with e =, the maximum value of E is 2= and the minimum value of E is 2= (the maximum and minimum numbers of in the rows of H are 2 and 2). For the second code with e =2, the maximum value of E is 2=22 and the minimum value of Chuyên sane Công is 22=4. nghệ thông tin và Truyền thông - Số (4-205) Fig. 5 BER with different values of e Fig. 5. BER with different values of e Figs. depicts simulation results for the WiFi LDPC code with a code rate R = /2, length n = 48 bits. This figure compares the Bit Error Rate (BER) and Frame Error Rate energy and (FER) N 0 = of σthe 2 /2) different and with decoders the error with number the assumption being 50 of and Imax different 00 and values M = 20 of. e. We Based can on Fig. 5, realize we can that, see in comparison that for the with WiFi the conventional LDPC codeldpc with length decoder, n the = performance 48 bits, we of should the P- choose e decoder = and (with forpredefined the WiFiequivalent LDPC code check with matrices length and n E = =2), 944 PA-decoder bits, weand should SA-decoder choose e = 2. We ( e can =) see improves that the considerably value of Eand is depend the best onldpc positions decoder of e bits is the in the SA-decoder. LSB. ForThe the first codeperformance with e =, of the the maximum PA-decoder value is better of than E isp-decoder 2 =because and the equivalent minimum check value matrices of E is 2 = are (the calculated maximum based and on minimum LLR of channel. numbers of in the rows of H are 2 and 2). For the secondimproved code Fig. with considerably. 7 compares e = 2, the theif BER maximum M = 00, the and FER value decoding of SA-decoder of is 2=22 performance for this and of code the with minimum SA-decoder the assumption value will of of 5 E is 2 2=4. e improve = and about different 0.4 db values at BER= of M 0. We. observe that, if M increases, the performance will be 7 Fig. BER and FER comparisons between Fig.. BER and FER comparisons BPA decoder, between P, PA, BPA SA decoder, decoders with P, PA, M=20 SA decoders with M = 20 90

8 Tạp chí Khoa học và Kỹ thuật - Học viện KTQS - Số 7 (4-205) Fig. depicts simulation results for the WiFi LDPC code with a code rate R = /2, length n = 48 bits. This figure compares the Bit Error Rate (BER) and Frame Error Rate (FER) of the different decoders with the assumption of I max = 00 and E = 20. We can realize that, in comparison with the conventional LDPC decoder, the performance of the P-decoder (with predefined equivalent check matrices and E = 2), PA-decoder and SA-decoder (e = ) improves considerably and the best LDPC decoder is the SA-decoder. The performance of the PA-decoder is better than P-decoder Fig. BER because and FER comparisons equivalentbetween check matrices are calculated based on LLR of channel. BPA decoder, P, PA, SA decoders with M=20 Fig. 7. BER and FER with various M Fig. 7. BER and FER with various M Fig. 8 compares BER and FER of IEEE 802.n code with code rates R = /2, R = 2/, R = / 4, length n = 944 bits and Fig. 9 compares BER and FER of IEEE Fig. 7 compares the BER and FER of SA-decoder for this code with the assumption of 802.e code with code rates R = /2, R = 2/ (code A), R = / 4 (code A), length e = and different values of M. We observe that, if M increases, the performance will n = 204 bits (with the assumption of e =2). We can realize that, in comparison with the be improved considerably. If M = 00, the decoding performance of the SA-decoder will improve about 0.4 db at BER=0 5. Fig. 8 compares BER and FER of IEEE 802.n code with code rates R = /2, R = 82/, R = /4, length n = 944 bits and Fig. 9 compares BER and FER of IEEE 802.e code with code rates R = /2, R = 2/ (code A), R = /4 (code A), length n = 204 bits (with the assumption of e = 2). We can realize that, in comparison with the conventional LDPC decoder, BER and FER of SA-decoder with M = 20 can improve about 0. db at BER=0. Because matrix H e received from the matrix H with E = 2 (very small in comparison with number of rows of the matrix H) is also a sparse matrix, the complexity of the P and PA decoders is M times more complicated than conventional LDPC decoder. The P decoder is simpler the PA decoder because it does not need H e computing in the decoding process. In the P and PA decoders, the receiver can change the number of operating decoders to have a tradeoff between the calculation in decoding process and the required performance. The P and PA decoders not only improve the decoding performance in comparison with conventional LDPC decoder, but also have not delay by using only one stage. In comparison with conventional LDPC decoder, the complexity S and SA is not increased too much because they operate in 9

9 conventional LDPC decoder, BER and FER of SA-decoder with M = 20 can improve about Chuyên san Công nghệ thông tin và Truyền thông - Số (4-205) 0. db at BER= 0. conventional LDPC decoder, BER and FER of SA-decoder with M = 20 can improve about 0. db at BER= 0. Fig. 8 BER and FER of WiFi LDPC codes Fig. 8. BER and FER of WiFi LDPC codes Fig. 8 BER and FER of WiFi LDPC codes Fig. 9 BER and FER of WiMAX LDPC codes Because matrix Fig. H e 9 received BER and FER from of the WiMAX matrix LDPC Hcodes with E =2 (very small in comparison with number Fig. 9. of BER rows and of FER the matrixh of WiMAX) LDPC is also codes a sparse matrix, the complexity of the P and Because PA decoders matrix is H M- times more complicated than conventional LDPC decoder. The e received from the matrix H with E =2 (very small in P decoder is simpler the PA decoder because it does not need He computing in the decoding serial mode. comparison The disadvantage with number of rows theseof methods the matrixh is that ) is they also have a sparse a post-processing matrix, the complexity delay of as the decoding the process. P and process In PA the decoders requires P and PA is two M- decoders, stages. times the more receiver complicated can change than conventional the number of LDPC operating decoder. decoders The P to decoder have a trade-off is simpler between the PA the decoder calculation because in decoding it does not process need Hand the required performance. e computing in the decoding The P and PA decoders not only improve the decoding performance in comparison with process. In the P and PA decoders, the receiver can change the number of operating decoders 7. Conclusion conventional LDPC decoder, but also have not delay by using only one stage. In comparison to have a trade-off between the calculation in decoding process and the required performance. with conventional LDPC decoder, the complexity S and SA is not increased too much because This paper The P proposes and PA decoders new parallel not only and improve serial LDPC the decoding decoders performance with predefined comparison parity check with and equivalent conventional parity LDPC check decoder, matrices, but also allowing have not improvement delay by using of only theone LPDC stage. decoding In comparison performance. with Weconventional also propose LDPC adaptive decoder, channel the complexity LDPCS decoders and SA is with not increased equivalent too much paritybecause check 9 matrices based on the channel information. Parallel decoder needs only one stage, therefore it 92 9

10 Tạp chí Khoa học và Kỹ thuật - Học viện KTQS - Số 7 (4-205) is not delayed as other two-stage proposed algorithms. Serial decoder has lower complexity, but it needs two-stage and redecodings. The simulation results for WiFi and WiMAX LDPC code show that, in comparison with the conventional LDPC decoder, the performance of new decoders can be significantly improved with acceptable complexity. References [] R. G. Gallager, Low Density Parity Check Codes, Cambridge, MA: MIT. [2] IEEE standard for local and metropolitan area networks, pdf. [] IEEE standard for Information technology Telecommunications and information exchange between systems, [4] T. Richardson, "Error floors of LDPC codes", Proceedings of The 4st Annual Allerton Conference on Communication, Control, and Computing, 200. [5] R. Tanner. "A recursive approach to low complexity codes," IEEE Transactions on Information Theory, vol. IT-27, no. 5, pp , 98. [] Yang Han, W.E. Ryan, "Low-floor decoders for LDPC codes," IEEE Transactions on Communications, vol. 57, [7] Yang Han, W.E. Ryan, "LDPC decoder strategies for achieving low error floors," Information Theory and Applications Workshop, [8] M. Fossorier, "Iterative reliability based decoding of LDPC codes," IEEE International Symposium on Information Theory, 200. [9] Guangwen Li, Guangzeng Feng, "Generalized reliability-based syndrome decoding for LDPC," arxiv: v2 [cs.it], [0] Nguyen Tung Hung, "A New Decoding Algorithm based on Equivalent Parity Check Matrix for LDPC codes," REV Journal on Electronics and Communications The Radio Electronics Association of Vietnam, vol., no. 2, 20. [] J. Hagenauer, E. Offer and L. Papke, "Iterative decoding of binary block and convolutional codes," IEEE Transactions on Information Theory, vol. 42, no. 2, pp , March 99. [2] G. Battail, "Building long codes by a combination of simple ones, thanks to the weighted-ouput decoding," Proc URSI, pp 4-7, 989. [] S. Ländner, T. Hehn, O. Milenkovic, J. B. Huber, "The Trapping Redundancy of Linear Block Codes," IEEE Transactions on Information Theory, vol. 55, no., pp. 5-, [4] T. Hehn,. B. Huber, S. Ländner, "Improved Iterative Decoding of LDPC Codes from the IEEE WiMAX Standard," Proceedings of 8th International ITG Conference on Systems, Communications and Coding, 200. [5] A. Kothiyal, O.Y. Takeshita, W. Jin; M. Fossorier, "Iterative reliability-based decoding of linear block codes with adaptive belief propagation," IEEE Communications Letters, vol. 9, no. 2, pp , Manuscript received ; accepted Nguyen Tung Hung was born in Hung Yen, Vietnam, in 99. He received the B. Eng, the M. Eng. and Dr. Eng from Le Qui Don Technical University, Hanoi, Vietnam respectively, in 992, 999 and 200. Since 200, he has been working at Telecommunications University, Nha Trang, Vietnam. He is currently the dean of the Faculty of Telecommunications Technology. His main interests are channel coding theory and its applications. tunghung@tcu.edu.vn 9

11 The Cuong Dinh was born in Hanoi, Vietnam, Chuyên san Công nghệ thông tin và Truyền thông - Số (4-205) Nguyen Van Duan was born in 974. He received the Master degree from Le Qui Don Technical University, Hanoi, Vietnam, in From 200 to 20, he was lecturer at Telecommunications University, Nha Trang, Vietnam. He is currently a PhD student in Le Qui Don Technical University, Hanoi, Vietnam. His main interests are channel coding theory and its applications. duannv@tcu.edu.vn N. Q. Tuan et al.: BICM-ID and Partial Reusing QAM Signal Points 5 [5] B. M. Hochwald and S. ten Brink, Achieving nearcapacity on a multiple-antenna channel, IEEE Transactions on Communications, vol. 5, no., pp , 200. [] A. J. Viterbi and J. K. Omura, Principles of Digital Communication and Coding. McGraw-Hill, 979. [7] J. Tan and G. L. Stuber, Analysis and design of symbol mappers for iteratively decoded BICM, IEEE Transactions on Wireless Communications, vol. 4, no. 2, pp. 2 72, Mar Nguyen Quang Tuan was born in 94 in Hanoi. He received his B.Eng. at the University of Communication Technology in 995, and M.Eng. at Hanoi University of Science and Technology in 99. He works as a researcher at Department of Communications, Vietnam Ministry of Public Security. He is currently pursuing a PhD study at Le Qui Don Technical University. Do Quoc Trinh was born in in He He received received University his B.Eng. in 982 and and Ph.D. 200, degrees respectively. at Le Qui Dr. Do Quoc Trinh is currently a lecturer of Faculty his B.Eng. and Ph.D. degrees at Le Qui Don Technical Don of Radio-Electronics Technical University Engineering, 982 and Le Qui 200, Don Technical University, Hanoi, Vietnam. His research respectively. interests are Dr. in areas Do Quoc of mobile Trinhcommunication is currently and channel coding. a lecturer trinhdq@gmail.com of Faculty of Radio-Electronics Engineering, Le Qui Don Technical University, Hanoi, Vietnam. His research interests are in areas of mobile communication and channel coding. Xuan Nam Tran is currently an associate professor at Department of Communications Engineering at Le Quy Don Technical University Vietnam. He received his master of engineering (ME) in telecommunications engineering from University of Technology Sydney, Australia in 998, and doctor of engineering in electronic engineering from The University of Electro-Communications, Japan in 200. From November 200 to March 200 he was a research associate at the Information and Communication Systems Group, Department of Information and Communication Engineering, The University of Electro-Communications, Tokyo, Japan. Dr. Tran research interests are in the areas of adaptive antennas, space-time processing, space-time coding and MIMO systems. He is the author and co-author of more than thirty technical papers published in international journals and conference proceedings. Dr. Tran is a recipient of the 200 IEEE AP-S Japan Chapter Young Engineer Award. He is a member of IEEE, IEICE, and the Radio- Electronics Association of Vietnam. 94