ENPIRION. EP5352Q/EP5362Q/EP5382Q 500/600/800mA Synchronous Buck Regulators With Integrated Inductor Rev 1.2 November, 2006.

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1 ENPIRION EP5352Q/EP5362Q/EP5382Q 5/6/8mA Synchronous Buck Regulators With Integrated Inductor Rev.2 November, 26 RoHS Compliant ENABLE Soft Start PWM Comp (+) Sawtooth Generator UVLO Thermal Limit Current Limit VREF Product Highlights (-) Error Amp (-) (+) P-Drive N-Drive DAC Switch Voltage Select VS VS VS2 Package Boundry Revolutionary integrated inductor Very small solution foot print Fully RoHS compliant; MSL 3 26 C reflow Only two low cost components required 5mm x 4mm x.mm QFN package Wide 2.4V to 5.5V input range 5, 6, 8 ma output current versions Less than µa standby current Very high switching frequency Fast transient response Very low ripple voltage; 5mV p-p 3 Pin VID Output Voltage select External divider option Dynamically adjustable output 2% accuracy over line, load, & temp Short circuit, UVLO, and thermal protection Stable with up to 6 uf output capacitance V SENSE V FB Product Overview The Ultra-Low-Profile EP53X2Q product family is targeted to applications where board area and profile are critical. EP53X2Q is a complete power conversion solution requiring only two low cost ceramic MLCC caps. Inductor, MOSFETS, PWM, and compensation are integrated into a tiny 5mm x 4mm x.mm QFN package. The EP53x2Q family is engineered to simplify design and to minimize layout constraints. High switching frequency and internal type III compensation provides superior transient response. With a. mm profile, the EP53x2 is perfect for space and height limited applications. A 3-pin VID output voltage select scheme provides seven pre-programmed output voltages along with an option for external resistor divider. Output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling. Typical Application Circuit 2.2uF Voltage Select ENABLE V in V S V S V S2 EP53x2Q V Sense V FB Figure. Typical application circuit. Applications µf Area constrained applications Mobile multimedia, smartphone & PDA Mobile and Cellular platforms VoIP and Video phones Personal Media Players Advanced Mobile Processors, DSP, IO, Memory, Video, Multimedia Engines

2 Absolute Maximum Ratings Maximum Electrical Ratings Min Max Voltages on:, -.3V 7.V Voltages on: V SENSE -.3V +.3V Voltages on: V S -V S2 -.3V +.3V Voltages on: ENABLE -.3V +.3V Voltages on: V FB -.3V 2.7V Maximum Thermal Ratings Ambient operating range (Industrial Rated) -4 C +85 C Max Operating Junction Temperature +25 C Storage Temperature Range -65 C +25 C Reflow Peak Body Temperature MSL3 ( Sec) +26 C Electrical Characteristics NOTE: typical values for =5.5V and T A = 25 C. C IN = 4.7µF, C OUT =µf unless otherwise noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Operating Input Voltage V Output Voltage V o VS VS VS User Sel Dynamic Voltage Slew Rate V slew 3 mv/µs Continuous Output Current I OUT EP5352Q 5 ma Continuous Output Current I OUT EP5362Q 6 ma Continuous Output Current I OUT EP5382Q 8 ma Shut-Down Current I SD Enable = Low.75 µa PFET Current Limit I LIM.4 A Feedback Pin Voltage V FB.6 V Feedback Pin Input Current I FB na VS-VS, Enable Voltage Pin = Low..4 V Threshold TH Pin = High.4 VS-VS2 Pin Input Current I VSX na Operating Frequency F OSC 4 5 MHz Ripple Voltage V Ripple C OUT =uf 85 X5R MLCC =3.6V; =.8V 5 mv Thermal Shutdown T SD 5 C Thermal Shutdown Hysteresis T SDH 5 C Voltage Accuracy Vin=2.4V to 5.5V; All internal VID conditions; Load µa to full load; Temp 4 C to +85 C V % Line Regulation 2.4V 5.5V.4.6 %/volt Load Regulation ma I LOAD 8mA %/ ma Soft-Start Operation Time to 9% T ss Vout = 3.3V µs 2

3 Pin Description ENABLE VS VS VS2 VS2 VS VS ENABLE V FB V SENSE V FB V SENSE 6 5 A EP53x2Q EP53x2Q VOUT Figure 2. Pin description, top view. Figure 3. Pin description, bottom view. VOUT (Pin,2): Input voltage pin. Supplies power to the IC. VIN can range from 2.4V to 5.5V. Input : (Pin 3): Input power ground. Connect this pin to the ground terminal of the input capacitor. Refer to Layout Recommendations for further details. Output : (Pin 4): Power ground. This pin is internally connected to bottom thermal/ground pad (A). The output filter capacitor should be connected to this pin. Refer to Layout recommendations for further detail. (Pin 5,6,7): Regulated output voltage. (Pin 8,9,,,2,3,4): These pins should not be electrically connected to each other or to any external signal, voltage, or ground. One or more of these pins may be connected internally. V SENSE (Pin 5): Sense pin for preset output voltages. When using preset voltages connect this to V LOAD or as close to V LOAD as possible to ensure the best regulation. When using external divider, connect this pin to. V FB (Pin 6): Feed back pin for external divider option. When using the external divider option (VS=VS=VS2= high) connect this pin to the center of the external divider. Set the divider such that V FB =.6V. VS,VS,VS2 (Pin 7,8,9): Output voltage select. VS=pin9, VS=pin8, VS2=pin7. Selects one of seven preset output voltages or choose external divider by connecting pins to logic high or low. Logic low is defined as V LOW.4V. Logic high is defined as V HIGH.4V. Any level between these two values is indeterminate. (refer to section on output voltage select for more detail). ENABLE (Pin 2): Output enable. Enable = logic high, disable = logic low. Logic low is defined as V LOW.4V. Logic high is defined as V HIGH.4V. Any level between these two values is indeterminate. A (Bottom thermal/ground pad): System ground for single point grounding. Also functions as thermal pad to remove heat from package. Connect to surface or PCB internal ground plane. 3

4 Functional Block Diagram UVLO Thermal Limit Current Limit Ramp Control ENABLE Soft Start P-Drive (-) PWM Comp (+) N-Drive Sawtooth Generator V SENSE Error Amp (-) (+) Switch V FB DAC VREF Voltage Select Package Boundry VS VS VS2 Figure 4. Functional block diagram. 4

5 Typical Performance Characteristics 95 Efficiency vs Output Current Efficiency vs Output Current Efficiency -% = 3.3V = 3.V = 2.7V = 2.5V =.8V Efficiency -% = 3.3V = 3.V = 2.7V = 2.5V =.8V 55 = 5.V Load Current (ma) 55 = 3.6V Load Current (ma) Efficiency vs Output Current Start up Waveform V/Div Efficiency -% = 3.V = 2.7V OUT V = 2.5V 6 OUT V =.8V 55 OUT V =.2V = 3.3V Load Current (ma) Transient Response Enable 2V/Div = 5.V 2µs/Div = 3.3V Transient Response 5mV/Div 5mV/Div I Load 5mA/Div I Load 5mA/Div = 5.V 2µs/Div = 3.3V I load = ma to 8mA = 3.3V 2µs/Div =.8V I load = ma to 8mA Output Ripple Output Ripple mv/div mv/div = 3.6V 2ns/Div = 3.3V Output Cap = µf 85 = 3.6V 2ns/Div = 3.3V Output Cap = 2 x µf 85 5

6 Detailed Description Functional Overview The EP53x2Q family is a complete DCDC converter solution requiring only two low cost MLCC capacitors. MOSFET switches, PWM controller, Gate-drive, compensation, and inductor are integrated into the tiny 5mm x 4mm x.mm package to provide the smallest footprint possible while maintaining high efficiency and high performance. The converter uses voltage mode control to provide the simplest implementation and high noise immunity. The device operates at a 5 MHz switching frequency. The high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. The 5 MHz switching frequency enables the use of very small components making possible this unprecedented level of integration. Enpirion s proprietary power MOSFET technology provides very low switching loss at frequencies of 5 MHz and higher, allowing for the use of very small internal components, and very wide control loop bandwidth. Unique magnetic design allows for integration of the inductor into the very low profile.mm package. Integration of the inductor virtually eliminates the design/layout issues normally associated with switch-mode DCDC converters. All of this enables much easier and faster integration into various applications to meet demanding EMI requirements. Output voltage is chosen from seven preset values via a three pin VID voltage select scheme. An external divider option enables the selection of any voltage in the 3.3V to.6v range. This reduces the number of components that must be qualified and reduces inventory problems. The VID pins can be toggled on the fly to implement glitch free dynamic voltage scaling. Protection features include under-voltage lock- (UVLO), over-current protection (OCP), out short circuit protection, and thermal overload protection. Integrated Inductor Enpirion has introduced the world s first product family featuring integrated inductors. The EP53x2Q family utilizes a low loss, planar construction inductor. The use of an internal inductor localizes the noises associated with the output loop currents. The inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. Further, the package layout is optimized to reduce the electrical path length for the AC ripple currents that are a major source of radiated emissions from DCDC converters. The integrated inductor significantly reduces parasitic effects that can harm loop stability, and makes layout very simple. Stable Over Wide Range Conditions of Operating The EP53x2Q family utilizes an internal type III compensation network and is designed to provide a high degree of stability over a wide range of operating conditions. One of the key features of this device is the ability to add supplementary capacitance to the output to further improve transient performance or reduce output voltage ripple. The EP53x2Q are stable with up to 6uF of total output capacitance. The very high switching frequency allows for a very wide control loop bandwidth. 6

7 Soft Start Internal soft start circuits limit in-rush current when the device starts up from a power down condition or when the ENABLE pin is asserted high. Digital control circuitry limits the ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor. The soft start ramp rate is nominally 3mV/µSec. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense P- MOSFET which is compared to a reference current. When this level is exceeded the P- FET is turned off and the N-FET is turned on, pulling low. This condition is maintained for a period of ms and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat in a hiccup mode. Under Voltage Lockout During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between states. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. In shutdown mode, the device quiescent current will be less than ua. The ENABLE pin must not be left floating. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 5C, the device will go through the normal startup process. Application Information Output Voltage Select To provide the highest degree of flexibility in choosing output voltage, the EP53x2Q family uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. VS VS VS2 Table. Voltage select settings External 7

8 Table shows the various VS-VS2 pin logic states and the associated output voltage levels. A logic indicates a connection to or to a high logic voltage level. A logic indicates a connection to ground or to a low logic voltage level. These pins can be either hardwired to or or alternatively can be driven by standard logic levels. Logic low is defined as V LOW.4V. Logic high is defined as V HIGH.4V. Any level between these two values is indeterminate. These pins must not be left floating. External Voltage Divider As described above, the external voltage divider option is chosen by connecting the VS, VS, and VS2 pins to VIN or logic high. The EP53x2Q uses a separate feedback pin, V FB, when using the external divider. VSENSE must be connected to as indicated in Figure uF ENABLE V in V S V S V S2 EP53x2 Figure 5. External Divider. V Sense V FB Ra Rb µf The output voltage is selected by the following formula: OUT Ra ( ) V =.6V + Rb R a must be chosen as 2KΩ to maintain loop gain. Then R b is given as: R b 5.2x = Ω V.6 OUT Dynamically Adjustable Output The EP53x2Q are designed to allow for dynamic switching between the predefined VID 8 voltage levels The inter-voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. The slew rate is identical to the softstart slew rate of 3mV/uS. Dynamic transitioning between internal VID settings and the external divider is not allowed. Input and Output Capacitors The input capacitance requirement is as follows: EP5352Q, EP5362Q = 2.2uF EP5382Q = 4.7uF Enpirion recommends that a low ESR MLCC capacitor be used. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-mode DC-DC converter input and output filter applications. The output capacitance requirement is a minimum of uf. The control loop is designed to be stable with up to 6uF of total output capacitance. Capacitance above the uf minimum should be added if the transient performance is not sufficient using the uf. Enpirion recommends a low ESR MLCC type capacitor be used. The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-DC converter input and output filter applications. Cout Manufacturer Part # Value WVDC Case Size Murata GRM29R6J6KE9D uf 6.3V 85 GRM39R6J6KED 26 Panasonic ECJ-2FBJ6K 6.3V 85 ECJ-3YBJ6K 26 Taiyo Yuden JMK22BJ6KD-T 6.3V 85 JMK36BJ6KF-T 26

9 Cin Manufacturer Part # Value WVDC Case Size Murata GRM2BR7A225KAL 2.2uF V 85 GRM3MR7A225KAL 26 GRM2BR7J225KAL 6.3V 85 Panasonic ECJ-2FBA225K V 85 ECJ-3YBA225K 26 ECJ-2YBJ225K 6.3V 85 Taiyo Yuden LMK7BJ225KA-T V 63 LMK22BJ225KG-T 85 Cin Manufacturer Part # Value WVDC Case Size Murata GRM29R6A475KE9D 4.7uF V 85 GRM39R6A475KAD 26 GRM29R6J475KED 6.3V 85 GRM3MR6J475KAL 26 Panasonic ECJ-2FBA475K V 85 ECJ-3YBA475K 26 ECJ-2FBJ475K 6.3V 85 ECJ-3YBJ475K 26 Taiyo Yuden LMK22BJ475KG-T V 85 LMK36BJ475KD-T 26 JMK22BJ475KD-T 6.3V 85 LAYOUT CONSIDERATIONS Recommendation : Input and output capacitors should be placed as close to the EP53x2Q package as possible to reduce EMI from input and output loop currents. This reduces the physical area of the Input and Output AC current loops. Recommendation 2: DO NOT connect pins 3 and 4 together. Pin 3 should be used for the Input capacitor local ground and pin 4 should be used for the output capacitor ground. The input and output capacitors should be spread slightly apart to prevent coupling between the input AC current loop and the output AC current loop (see Fig. 6 and Fig. 7).. Recommendation 3: Multiple, small, vias should be used to connect ground terminal of the Input capacitor and the output capacitor to the system ground plane. (see Fig. 6 and Fig. 7). Recommendation 4: The large thermal pad underneath the component must be connected to the system ground plane through as many thermal vias as possible. The diameter of the vias should be.3mm. This provides the quiet, or analog ground for the converter and also provides the path for heat dissipation from the converter. A later section of this note makes a recommendation on the PCB footprint. Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer. This ground plane should be continuous and uninterrupted below the converter and the input and output capacitors that carry large AC currents. Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or control lines underneath the converter package. Figure 6 shows an example schematic for the EP53x2Q using the internal voltage select. In this example, the device is set to a of.2v (VS2=, VS=, VS=). 9

10 SE VS2 VS VS ENABLE V SEN V A FB V 5 IN 6 V IN OUT V uF/2.2uF µf (see layout recommendation 3) Figure 6. Example application, Vout=.2V. Figure 7 shows an example schematic using an external voltage divider. VS=VS=VS2=. The resistor values are chosen to give an output voltage of 2.6V. VS2 VS VS A 9 8 ENABLE V FB V SENSE Rb=6K Ra=2K (see layout recommendation 3) 4.7uF µf Figure 7. Schematic showing the use of external divider option, Vout = 2.6V. Figure 8 shows two example board layouts. Note the placement of the input and output capacitors. They are placed close to the device to minimize the physical area of the AC current loops, and are slightly spread apart to prevent coupling between input and output current loops. Note the placement of the vias per recommendation 3. Package Outline Package Outline C OUT C IN C OUT C IN Vias to Ground Plane Vias to Ground Plane Figure 8. Example layouts.

11 Design Considerations for Lead-Frame Based Modules Exposed Metal on Bottom Of Package Enpirion has developed a break-through in package technology that utilizes the lead frame as part of the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, it does require some special considerations. As part of the package assembly process, lead frame construction requires that for mechanical support, some of the lead-frame metal be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package. Only the A/Thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. PCB solder mask should be used to prevent connection to the other pads. Figure 9 shows the shape and location of these metal pads as well as the mechanical dimension of the A/Thermal pad and the pins. The grayed-out area represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the PCB. NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC MO-22, Issue J, Date May 25). The separation between the large thermal pad and the nearest adjacent metal pad or pin is a minimum of.2mm, including tolerances. This is shown in Figure. Thermal Pad. Connect to Ground plane Figure 9. Exposed metal and mechanical dimensions of the package.

12 JEDEC minimum separation =.2 Figure. Exposed pad clearances; the Enpirion lead frame package complies with JEDEC requirements. 2

13 Figure. Recommended PCB Solder Mask Openings. 3

14 P53x2 XXXXX YYWW Figure 2. Package mechanical dimensions. 4

15 Tape & Reel Specification Figure 3. Tape and reel mechanical dimensions. Ordering Information Part Number Temp Range Package EP5352QI-T 5mA -4 C to +85 C QFN2 Tape & Reel (5) EP5352QI-E 5mA Evaluation Board EP5362QI-T 6mA -4 C to +85 C QFN2 Tape & Reel (5) EP5362QI-E 6mA Evaluation Board EP5382QI-T 8mA -4 C to +85 C QFN2 Tape & Reel (5) EP5382QI-E 8mA Evaluation Board 5

16 Additional Products Part Number EQ5352DI EQ5362DI EQ5382DI EN532QI EN5335QI EN5336QI EN5365QI EN5366QI Description 5mA DCDC regulator; tiny 3mm x 2mm x.9mm DFN package 6mA DCDC regulator; tiny 3mm x 2mm x.9mm DFN package 8mA DCDC regulator; tiny 3mm x 2mm x.9mm DFN package A DCDC with integrated inductor; 5mm x 4 x.mm QFN package 3A DCDC with integrated inductor; mm x 7.5mm x.85mm QFN package 3-Pin VID programming 3A DCDC with integrated inductor; mm x 7.5mm x.85mm QFN package External resistor divider programming 6A DCDC with integrated inductor; 2mm x mm x.85mm QFN package 3-Pin VID programming; Parallel Capable 6A DCDC with integrated inductor; 2mm x mm x.85mm QFN package External resistor divider programming; Parallel Capable Contact Information Enpirion, Inc. 685 US Route 22/26 Suite 35 Bridgewater, NJ 887 Phone: Fax: Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion. 6