AN2331. Power Management - MAX1583 White LED Driver Emulation with PSoC. Introduction. Principles of Operation

Transcription

1 Power Management - MAX58 White LED Driver Emulation with PSoC Author: Andrey Magarita Associated Project: Yes Associated Part Family: CY8C4xxxA, CY8C7xxx, CY8C9xxx GET FREE SAMPLES HERE Software Version: PSoC Designer 4. Associated Application Notes: AN04, AN0, AN6, AN7 Introduction This project demonstrates how to emulate the functionality of a Maxim MAX58 white LED driver with a PSoC device. It powers white LEDs in flash mode or continuous lighting mode from a battery power source. Additionally, it has an I C interface and features a demonstration using internal self-test mode. The proposed switching current source operates independently of the CPU using a unique combination of the PSoC device s analog and digital user modules. The CPU core can be employed to tune the LED current using a chosen communication interface, for example, I C. This is a new feature in comparison with the classic Maxim part. Principles of Operation The flash/camera white LED driver operates in several modes: In Shutdown mode the LED driver is off and the device consumes minimum current. In Precharge mode the LED is off but the storage capacitor accumulates energy for the flash. When this process is complete, the driver sets the Standby state by setting the Power OK signal (POK). In this state, constant voltage is maintained on the energy storage capacitor and the driver is ready to generate the flash pulse. In Strobe mode a large current pulse is applied to the LED to generate a flash. In Movie mode a small, constant current is applied to the LEDs to provide continuous illumination for continuous image capture. The outstanding feature of the flash driver is its ability to provide a large, short current pulse, which exceeds the normal continuous operation current by several times. A flash light source consists of several LEDs in series with forward voltage in flash mode of up to 4 volts. There is a need to increase the driver output voltage to support these voltage demands in flash mode. The pulse current through the diodes can reach 00 ma. When the LEDs are powered from a boost converter directly in flash mode, the converter input current can exceed several Amperes. This large consumption of current during pulse generation is not acceptable in many battery-powered applications. It is preferable to accumulate the necessary energy in the intermediate capacitive energy storage and transmit it into the load during flash. There are several ways to regulate the LED current during a flash. The simplest solution is to limit the current using a resistor. In this case, the LED brightness and color temperature will vary during the flash pulse due to the exponential decay of the pulse current. A constant current source can be used to power the LEDs and eliminate these drawbacks. This design uses the capacitor for intermediate energy storage and constant current source to regulate LED current during flash time. Energy storage capacitor charge pumping should be carried out as quickly as possible to enable the production of flashes in rapid sequence. At the same time, the current consumed from the battery must not exceed the predefined admissible value due to limited battery output resistance. Therefore, the driver should limit its own power consumption during the capacitor charge phase to some predefined value. This feature is implemented in the proposed application as well. The driver operates as a boost-switching regulator. Each operation cycle consists of two phases: the inductor energy accumulation phase and the energy transfer phase. The first phase is energy accumulation. Upon initialization, the inductor is connected to the power source and the inductor current ramps (nearly linearly) to the desired threshold value. January 5, 006 Document No Rev. **

2 Once completed, the driver switches to the energy transfer phase. In this phase the inductor is connected to the load and the driver operates as follows: The simplified driver schematic is shown in Figure and the operational timing diagram is shown in Figure. If the load voltage exceeds the predefined value, this phase continues until the load voltage drops below the predefined threshold value. If the load voltage does not reach the desired threshold value, the driver switches back to the energy accumulation phase after the timeout expires. The process then continues by alternating these two phases. Figure. Simplified Driver Schematic Uind I th DAC CPU set L D U cmp CMP U bat R L R ICS C U ind I Sw Sw Period = t on min + t off min Ucnt en En Counter Clock Compare = ton min CMP U sw POK Is D... D N Load CPU set I load UFB R U load Ucmp CMP U load U th Sw R Figure. Driver Timing Diagram January 5, 006 Document No Rev. **

3 Legend : U sw switches SW and SW control signal ; U ind I th comparator reference voltage, sets the inductor threshold current value during accumulation phase ; U load U th comparator reference voltage, sets the load threshold voltage value during energy transfer phase ; U ind I signal, proportional to the inductor current at energy accumulation phase; I ind inductor current ; U load load voltage signal; U cmp comparator output signal; U cmp comparator output signal; U cnt en counter enable control signal, high - counter is disabled, low - enabled ; t 0 inductor energy accumulation start ; t -t 0 inductor current is less than desired value, counter is disabled; t inductor current reaches desired value, counter counts t on min time, additionally ; t -t =t on min, inductor energy accumulation phase continues; t end of energy accumulation phase, start of energy transfer phase, t off min interval counting begins ; t -t energy transfer phase, load voltage increases, but is less threshold value, t off min is counted ; t load voltage reaches threshold value before t off min elapses,counter is stopped, inductor switch continues to be in off state; t 4-t load voltage is larger than desired value due to continuing energy transfer phase, counter is stopped; t 4 load voltage is less than desired value, counter is enabled ; t 0-t 4 -t off min interval counting ends; t 0 next cycle starts. U sw U ind I th U ind I U load I ind U load I th U FB U cmp U cmp U en cnt t 0 t t t t 4 t' 0 January 5, 006 Document No Rev. **

4 In Figure, the first comparator (CMP ) controls the load voltage value. It compares the load voltage to the reference voltage value. When the load voltage is less than the threshold reference value, a logic low is produced on the comparator output. The CMP output signal is only active during the energy transfer phase; it is blocked by using the Sw switch that is controlled by the same signal as the main regulator switch Sw. The second comparator (CMP ) controls the main switch current during the energy accumulation phase. When the current sense resistor R ics voltage is less than the reference voltage value U ind I th, the comparator output is a logic high. When the voltage on R ics exceeds the reference, the comparator logic output is low. The CMP output signal is active only during the energy accumulation phase; it is gated using the AND gate with the counter comparator CMP output signal. At the energy transfer phase, this comparator non-inverting input is gated by the Sw switch controlled by the inverted main regulator switch Sw control signal. Switch Sw is required to keep high inductor voltage from reaching the PSoC input during the energy transfer stage. The CMP reference voltage U ind l th is set by a DAC and can be varied in firmware within a wide range. The comparator CMP and CMP output signals are combined into one signal using the OR gate and used to enable/disable counter operation. Note that when the enable signal is set to inverted, low enables counter operation, high disables. If the counter is disabled when the compare module output signal is low, this state is preserved until the time when the counter is not re-enabled again by the CMP output signal because the load voltage dropped below the predefined threshold value. If the counter is disabled when the counter output comparator CMP signal is high, this state is preserved until the counter is re-enabled by the CMP output, signaling completion of the energy accumulation phase. This phase continues until the counter finishes counting to the preset value. The counter output signal is passed to the inductor current control switch Sw. The CPU-controlled linear current source I s is intended to set the load current I load. This value depends on the driver operation mode (zero value in Precharge/Shutdown mode, large current in Strobe mode, small value for continuous lighting in Movie mode). The POK signal is formed by using the NOR gate. The first gate input is connected with the CMP output, the second, with the counter comparator CMP output. This gate provides restoration of the Sw modulated comparator output. Evaluation Board Schematic To evaluate driver operation, the evaluation board is shown and the schematic given in Figure. Figure. Evaluation Board Schematic J5 J IC J VCC R8* 0k VCC VCC R9* 0k SDA SCK POK EN EN FB POK CC FBSW CS EN VCC U VCC 8 7 P0[7] P0[6] 6 P0[5] P0[4] 5 4 P0[] P0[] 4 P0[] P0[0] 5 6 P[7] P[6] 7 P[5] P[4] 8 P[] P[] 0 P[] P[0] 9 SMP XRES P[7] P[6] 7 P[5] P[4] 6 P[] P[] 5 EN P[] P[0] 4 Vss CY8C44A J Self Test C6 0.uF C7 pf SW R 470R VDD R 0k SW C 0.uF R6 0 L uh Q MOSFET N R7 00k Lx D C 0uF-470uF Vload D D D4 D5 R 5K R4 K FBSW FB R5 5K ISSP J6 POWER J7 VDD + C 47uF C4 0.uF D6 5V6 VCC + C5 0uF CC CS R8 K Q NPN R9 R BAT The Q on-resistance is used to sense inductor current during the energy accumulation phase. Driver performance depends strongly on the transistor s parameters because the transistor serves the role of inductor current switch and current sensor at the same time. Therefore, during transistor selection, the onresistance should be taken into account. The voltage drop during the on state for the maximum expected inductor current should be from 70 mv to 700 mv. The lower voltage limit is determined by the DAC s resolution, the DAC s minimum output voltage (not quite to the negative rail), and the noise level on the PSoC internal Vss ground. January 5, 006 Document No Rev. ** 4

5 The recommended minimum DAC output voltage is about 75 mv. The upper limit is set by the maximum allowed operating temperature for the given transistor package. This application requires a transistor with maximum drainsource voltage V dss 0V and gate capacitance C gss < 00pF as well as the ability to operate at gatesource voltage to.9v. For an inductor peak current of 50 ma and 500 ma, the IRLML80TR from International Rectifier is recommended. The minimum on-resistance (taken from typical characteristics) for these transistors at drain current I ds =0.5A R ds(on) =0.5R, at current I ds =0.5A R ds(on) =0.R. For these currents, the voltage drop in the on state is 6 mv and 5 mv. Due to the variation in transistor parameters, the voltage drop can differ from the expected value. If accurate inductor current limiting is required, the best solution is to use an external low-resistance current sense resistor together with a low-r ds(on) MOSFET. When an external sense resistor is used, the recommended transistors are the Si40DH from Vishay or the FDN7N from Fairchild. The scheme that includes a current sense resistor is shown in Figure 4. In this case, the R,R,C 7 components are no longer required, R and R should be shorted, and P[6] is left unconnected. Figure 4. External Current Sense Resistor Usage To R6 top0[6] Rs To L Q R The inductor current limiting I ds lim value is set by the voltage DAC and can be evaluated by using the following Equation: I dslim V R N DAC 55 = ref Equation ds( on)min V ref is the DAC reference voltage. V ref =.V for the selected bandgap settings. N dac is the DAC code (valid values are..54). R ds is the expected minimum current sense resistor value (internal MOSFET or external resistor). The L inductance value must be in the range of - 00 μh. For larger inductors, the demand for size and ohmic resistance increase. With smaller inductors, the operating frequency increases and efficiency degrades. Increasing operating frequencies also increases the demand for comparator response time, which requires higher power settings. Note that inductor saturation current should be at least 5% more than estimated in Equation. The energy storage capacitor value can be evaluated by using the following Equation: C = ( ) I I t U N U LED boost strobe out FwLED Equation N is the number of serially connected LEDs. U FwLED is the forward voltage drop on one LED (usually 4V for white LED) during the flash pulse. U out is the output converter voltage (4V for this design). t strobe is the strobe (flash) pulse duration. I LED is the defined strobe mode current. I boost is the maximum boost regulator output current for preset output voltage. I boost is selected from experimentally collected data, shown in Figure 7. These dependencies were obtained for IRLML80TR MOSFET and inductor with active resistance 0.R. If you replace the transistor and inductor with others, these diagrams will be different. In this case, the reference may be used for initial evaluation purposes. A Schottky diode is recommended for D. The diode continuous current should be no less than A and maximum reverse voltage no less than 0V. To provide constant LED current, a current source is used. It is based on Application Note AN0 Programmable Analog High Current Source. PSoC Style. The difference from the original design lies in the use of an additional instrumentation amplifier to amplify the signal from current sense resistor R 9. The instrumentation amplifier separates the signal from the current sense resistor R 9, shifts this signal to AGND level, and permits compensation for the voltage drop on the internal Vss die resistance. The current source regulates the Q base voltage to maintain a constant voltage drop on R 9. The LED current is calculated from the R 9 voltage drop using Ohm s law: I U R9 led = Equation R9 The R 9 voltage drop can be calculated using Equation 4: U = C C Equation 4 ASD0 ASC0 A F R9 Vref ASD0 ASC0 CB CA ASD0 ASD0 V ref is the reference voltage. V ref =.V. C A, C B are the values of Acap, BCap on PSoC block, ASD0. ASC0 ASC0 C A, C F are the values of ACap, FCap on PSoC block, ASC0. C Aasc0 is the feedback capacitor on ASC0. In this design, the following values were selected: ASC0 ASC0 ASD0 C F = 6, CA = CB =. The minimum non-zero ASD0 current sense resistor voltage is obtained when C A = and is equal to mv. The LED current sense resistor R 9 should be selected while taking into account the minimum and maximum necessary load current. January 5, 006 Document No Rev. ** 5

6 The current source transistor can be bipolar as is shown on the schematic, or an N-channel MOSFET. Both transistor types should provide a pulse current greater then 00 mа and have breakdown voltage of U ce (U ds )>=0V. For a bipolar transistor it is desirable to have current gain β>00 at collector current of 00 mа. The MOSFET transistor should operate at gate-source voltages of about.5v. The bipolar BC8740 or MOSFET BSS8 (from Fairchild) satisfies these requirements. When maximum efficiency is required, the MOSFET is preferred. To minimize cost, the bipolar can be used. The connector J is used for PSoC programming. J is used for I C communication. J 5 is used to read the control and driver status (POK signal). The POK signal goes low when the output voltage in Precharge mode reaches the preset value (4V in this application). The table below lists driver control signals for each operation mode setting. Note that the host controller is responsible for turning on the Strobe mode at the right time interval. If there are any issues with this from the host controller s point of view, an internal one-shot can easily be added to provide correct timing. The PSoC has free resources available to implement this feature. Table. Driver Mode and Pin Level To minimize noise, the design of the PCB layout should ensure that the ground path of the PSoC and switch regulator have no common tracks. A "star"-type ground connection is recommended with the center at the connection point of C and C. PSoC User Module Configuration The PSoC internal user module placement is shown in Figure 5. Driver Mode EN EN Shutdown 0 0 Precharge 0 Movie 0 Strobe Figure 5. PSoC Internal User Module Configuration January 5, 006 Document No Rev. ** 6

7 Manual configuration modification has been used in a number of places to achieve the desired module interconnections and to adjust user module features. This opens up possibilities that are not offered by the existing user module library. The comparators CMP and CMP are placed in blocks ACB00 and ACB0. These comparators are powered with maximum power to optimize switching speed. AGND is used as a CMP reference. The feedback signal U FB is sent via AnalogColumn_InputMUX_0 to the comparator non-inverting input. The reference voltage for CMP is formed by using the DAC_8_ and sent to the non-inverting comparator input via an analog bus. The inverting CMP s input is connected to Port0[6] via the AnalogColumn_InputMUX_ column multiplexer. The comparator inputs are reconnected in the user code by direct manipulation of registers ACB00CR and ACB0CR. The comparators are switched to asynchronous mode by disabling the comparator bus latches and modifying the corresponding bits in the CMP_CR, ACB00CR, and ACB0CR registers. The CMP output signal is sent to the AND gate. The column s incremental gate is used for this purpose and the second gate input is tied to the counter (placed in DCB0) primary output. Connection is accomplished by writing to DEC_CR0. The comparator outputs are ORed by using the row LUT with NOR function and sent to the PWM enable input. A digital buffer, placed in DBB0, is used to route these signals. P[6] and P[5] are set to Open Drain Low drive mode and used to gate the inputs of comparators CMP and CMP (Sw and Sw switches; see Figure ). The switches are controlled by signals with controlled phase relationships. GlobalOutEven_4 is used as a reference signal. This signal is routed internally via GlobalInEven_4, Row_0_Input_0, digital buffer DigBuf_ and Row_0_Output_. The manipulation with row/digital module synchronization settings allows the formation of the Sw (see Figure ) control signal with some time shift, the required completion of the transistor turning-on process. This allows us to avoid false triggers on the comparator, which will occur if a high inductor voltage is passed to the comparator input. If the current sense scheme given in Figure 4 is used, the Sw switch is no longer required and P[6] can be left unconnected. The POK signal is formed by the row LUT with NOR function. Driver Firmware The following features are implemented in the firmware: Loads Configuration Switches Mode Communicates over I C Bus Supports Self-Test Mode If the Shutdown driver mode is off, the analog modules are disabled and sleep mode is activated. The current consumption is minimal and determined by the PSoC s sleep current. Sleep mode is exited by triggering a GPIO interrupt. In Precharge mode the boost regulator is on, but the current source is off. The storage capacitor is charged and when this process finishes, the Standby state is set, indicating a ready to use driver state. In this state, the voltage regulator maintains a constant voltage on the capacitor to compensate for possible current leakage. Movie mode provides low-intensity, continuous light on the LED. In this mode, the boost converter is enabled and a low current level is set by the current source. The current in this mode is set by the variable, MovieCurrent. Strobe mode is intended to generate a flash. The current in this mode is set by the variable, StrobeCurrent. The self-test mode is optional and intended to demonstrate autonomous operation. The operating modes of this application are initiated in series: Precharge mode, Strobe mode, Movie mode. The LED is off, brightly flashing, and constantly lit during these three modes, respectively. I C Communication Protocol This project uses the simplest communication protocol, I C. This protocol allows users to modify three parameters. Each message consists of three bytes: Device Address Parameter Number Parameter Value The Device Address is set by the user in the PSoC I C User Module parameters before programming the controller firmware. A description of each numbered parameter is as follows: 00 LimitCurrent is the inductor current limiting value (N DAC ), which sets the DAC count. The inductor current is determined by Equation (). Allowed values are..54, default is 8. 0 is the MovieCurrent value. This value is ASD0 transferred to C. The current is calculated A according to Equation (4). Allowed values are.., default is. 0 is the StrobeCurrent. This value is handled in the same way as the MovieCurrent value. Allowed values are.., default is 8. Note that the I C interface is active in Movie mode and Strobe mode as well as Precharge mode when the POK signal is low. The I C interface does not operate in Shutdown mode. The new parameters are activated after changing modes. Parameters that are set using the I C interface are stored until the device is powered off. After power-on, the default values are automatically loaded. There is no internal EEPROM storage. It is possible to extend communication capabilities because there are many CPU resources and ample code/data space still available. For example, we can add January 5, 006 Document No Rev. ** 7

8 support for a series of flashes, flash ramp current, status reading, etc. Key Differences from Maxim Part The proposed implementation of the LED driver has the following differences relative to the first-source Maxim part:. The MAX58 uses an internal MOSFET switch and current source control transistor. PSoC implementation uses two external transistors.. The MAX58 uses an internal switching transistor current sensor while the proposed PSoC implementation uses an external sensor. The MOSFET on state resistance or an additional resistor can be used for these purposes. This solution requires several additional external resistors.. The PSoC implementation is not limited to fixed LED flash currents (50 ma, 500 ma, 000 ma). The LED strobe/movie current can be selected anywhere within the operating range. 4. The MAX58 sets the LED current by using external resistors. The PSoC implementation sets current in the firmware. This can be accomplished, for example, via I C interface. 5. The PSoC-based implementation has lower operating frequency that requires larger inductors. The MAX58 evaluation kit schematic is shown in Figure 6. Figure 6. MAX58 Evaluation Kit Schematic (From Maxim s Evaluation Kit Data Sheet) VIN VIN L 4.7μH POK EN GND VIN EN R 00kΩ JU JU C ΜF R 6.04kΩ % R.0kΩ % 0 IN LX GND 5 POK 8 OUT U MAX58XETB 7 EN 9 LED 4 STB MOV EN 6 D C 0μF C5 0. μf OUT LED D WHITELED MODULE VIN JU R5 00kΩ R4 00kΩ D5 SW C 0.0μF V CC RESET U MAX64XS SRT GND C4 0.0μF January 5, 006 Document No Rev. ** 8

9 Driver Specifications Table. Driver Specifications Parameter Symbol Conditions Minimum Typical Maximum Unit Supply Voltage Vcc V Quiescent Supply Current Icc ma Undervoltage Lockout V Current Sense Trip Current * A Minimum Frequency ** 50 khz Maximum Frequency ** Fmax 850 khz Shutdown Supply Current Iccshdn Vdd=5V 5 µa EN, EN Input High Voltage Vih Vcc=.7V V EN, EN Input Low Voltage Vil Vcc=.7V 0.75 V EN, EN Input Bias Current Ishdn na MOSFET Driver On-Resistance Vcc=.7V Ω MOSFET Driver Sink/Source Current 0 ma * Can be redefined by customer by modifying firmware parameters. ** This is tuned by external component values and can be changed by customer. January 5, 006 Document No Rev. ** 9

10 Performance Test Graphs The graphs below illustrate some driver characteristics, which were collected for the following measurement conditions and component values: L = µh, R l =0. Ohm, Q - IRLML80, T = 5 C C=0 μf,vdd=.v. Figure 7. Maximum Boost Converter Output Current vs. Input Voltage for Inductor Current Limiting: Iboost, ma LED LED 4LED Iboost, ma LED LED 4LED Vin, V Vin, V Figure 8. Precharge Current in Standby Mode vs. Supply Voltage ma 500ma 4.5 Ist, ma Vin, V January 5, 006 Document No Rev. ** 0

11 Scope Images The images below display scope images collected for various input voltages and different operation modes/states. Figure 9. Scope Images Collection SWITCHING WAVEFORMS DURING PRECHARGE MODE - Q gate control voltage, I in input current 500mA/div, V load output voltage 00 mv/div SWITCHING WAVEFORMS IN STANDBY MODE I in input current 00mA/div, - V load 00 mv/div STROBE-PULSE WAVEFORMS 500mA inductor current limit, C =00uF I in input current 00mA/div, I led 00mA/div, - Power Ok signal, 4- V load 0V/div STROBE-PULSE WAVEFORMS (50 ma inductor current limit, C =00uF) I in input current 00mA/div, I led 00mA/div, - Power Ok, 4- V load 0V/div PRECHARGE-CYCLE WAVEFORMS (500mA inductor current limit ) Iin input current 00mA/div, -Power Ok signal, 4- Vload 0V/div PRECHARGE-CYCLE WAVEFORMS (50mA inductor current limit ) Iin input current 00mA/div, - Power Ok, 4- Vload 0V/div January 5, 006 Document No Rev. **

12 Evaluation Board Photograph Figure 0. Evaluation Board Photograph January 5, 006 Document No Rev. **

13 About the Author Name: Title: Background: Contact: Andrey Magarita Sr. Application Engineer Andrey graduated from National University Lvivska Polytechnika (Lviv, Ukraine) in 989 and is presently working as Senior Application Engineer for Zuvs, a privately held company. He has more than 5 years experience with embedded systems design. You can contact him at makar@ltf.lviv.net. In March of 007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation number and revision code (00-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions. PSoC is a registered trademark of Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC Designer, and PSoC Express are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 98 Champion Court San Jose, CA Phone: Fax: Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. January 5, 006 Document No Rev. **