EV10AS180x-EB Evaluation Board... User Guide

Transcription

1 EV0AS80x-EB Evaluation Board User Guide

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3 Table of Contents Section Introduction - Scope- Description - Section Hardware Description - Board Structure- Analogue Inputs/Clock Input - 3 Digital Output Data-3 4 RSTN -3 5 SA, RSx, TMx, SDA, SDAEN, GA, OA, DECN, Diode-4 6 Ground Layers -4 7 Power Supplies -4 Section 3 Operating Characteristics 3-3 Introduction 3-3 Operating Procedure3-33 Electrical Characteristics3- Section 4 Application Information 4-4 Analogue Input4-4 Clock Input 4-43 RESETN input4-44 SA, GA, OA, SDA and SDAEN Commands4-45 RSx, TMx and DECN Commands Output Data Diode for Junction Temperature Monitoring Test Bench Description4-0 Section 5 Ordering Information 5- Section 6 Appendix 6-6 EV0AS80x-EB Electrical Schematics6-6 EV0AS80x-EB Board Layers 6-6 EV0AS80x-EB Evaluation Kit User Guide i

4 Table of Contents ii EV0AS80x-EB Evaluation Kit User Guide

5 Section Introduction Scope The EV0AS80x-EB Evaluation Kit is designed to facilitate the evaluation and characterization of the EV0AS80x 0-bit 5 GSps ADC in AC coupled mode The EV0AS80x-EB Evaluation Kit includes: The 0-bit 5 GSps ADC Evaluation board with EV0AS80x ADC soldered on the PCB A CD ROM with the datasheet and device User Guide The User Guide describes the use the EV0AS80x-EB Evaluation Kit as an evaluation and demonstration platform and provides guidelines for its proper use Description The EV0AS80x-EB Evaluation board is very straightforward as it implements ev EV0AS80x 0-bit 5 GSps ADC device, SMA connectors for the sampling clock, analogue inputs and reset input accesses and 54 mm pitch connectors compatible with high speed acquisition system probes Thanks to its user-friendly interface, the EV0AS80x-EB Kit enables to test all the functions of the EV0AS80x 0-bit 5 GSps ADC To achieve optimal performance, the EV0AS80x-EB Evaluation board was designed in a 6-metal-layer board using FR4 HTG epoxy dielectric material (00 µm, ISOLA IS40 featuring a resin content of 45%) The board implements the following devices: The 0-bit 5 Gsps ADC Evaluation board with the EV0AS80x ADC soldered SMA connectors for CLK, CLKN, VIN, VINN, RESETN signals 54 mm pitch connectors for the digital outputs, compatible with high speed acquisition system probes Banana jacks ( mm) for the power supply accesses, the Die junction Temperature monitoring functions Jumpers for SDAEN, RS0, RS, TM0, TM, DECN, SDA, SA, OA, GA Potentiometers for SA, OA, GA, SDA The board dimensions are 60 mm 0 mm The board comes fully assembled and tested, with the EV0AS80x installed EV0AS80x-EB Evaluation Kit User Guide -

6 Introduction Figure - EV0AS80x-EB Evaluation Board Simplified Schematic SA GA OA Diode RSTN Connector port A CLK CLKN PIN Connector port B VIN VINN Connector DR DRN Connector port C AGND VCC5 AGND VCC3 3 V 3 D G N D SDA V C C O D G N D SDAEN Connector port D RS0 RS TM0 TM DECN As shown in Figure - on page, different power supplies are required: V CC5 = 5V analogue positive power supply (referenced to AGND) V CC3 = 33V analogue positive power supply (referenced to AGND) V CCO = 5V digital output power supply (referenced to DGND) 33V board supply for control functions (referenced to DGND) - EV0AS80x-EB Evaluation Kit User Guide

7 Section Hardware Description Board Structure In order to achieve optimum full speed operation of the EV0AS80x 0-bit 5 Gsps ADC, a multi-layer board structure was retained for the evaluation board Six copper layers are used, dedicated to the signal traces, ground planes and power supply planes The board is made in FR4 HTG epoxy dielectric material (ISOLA IS40) Board characteristics: RO4003 for the top and bottom layers, FR4 HTG for the internal layers Dielectric thickness: 00 µm Dielectric constant: 338 Lands diameter: 750 µm GND Via/Land Diameter: 00 µm The following table gives a detailed description of the board's structure Table - Board Layer Thickness Profile Layer Layer Copper layer Characteristics Copper thickness = 40 mm (with NiAu finish) AC signals traces = 50Ω microstrip lines DC signals traces FR4 HTG / dielectric layer Layer thickness = 00 µm Layer Copper layer Copper thickness = 8 µm AGND, DGND (separate planes) FR4 HTG / dielectric layer Layer thickness = 349 µm Layer 3 Copper layer Copper thickness = 8 µm Power planes = V CC5, V CC3, V CCO FR4 HTG / dielectric layer Layer thickness = 350 µm Layer 4 Copper layer Copper thickness = 8 µm Power planes = 3V3 FR4 HTG / dielectric layer Layer thickness = 350 µm EV0AS80x-EB Evaluation Kit User Guide -

8 Hardware Description Table - Board Layer Thickness Profile (Continued) Layer Layer 5 Copper layer Copper thickness = 8 µm AGND, DGND (separate planes) FR4 HTG / dielectric layer Layer thickness = 00 µm Layer 6 Copper layer Characteristics Copper thickness = 40 µm (with NiAu finish) AC signals traces = 50Ω microstrip lines DC signals traces The board is 6 mm thick The Clock, analogue inputs, reset and ADC functions occupy the top metal layer The digital data output signals occupy the top and bottom layers The Ground planes occupy layer and 5 Layer 3 and 4 are dedicated to the power supplies Analogue Inputs/Clock Input The differential clock and analogue inputs are provided by SMA connectors (Reference: JOHNSON ) Both pairs are AC coupled using 0 nf capacitors Special care was taken for the routing of the analog and clock input signals for optimum performance in the high frequency domain: 50Ω lines matched to ±0 mm (in length) between VIN and VINN or CLK and CLKN 70 µm between two differential pairs 400 µm line width 40 µm thickness 870 µm diameter hole in the ground layer below the VIN and VINN or CLK and CLKN ball footprints In addition, the lines for VIN, VINN and CLK, CLKN are matched to one another within ±mm A clearance in the ground plane below the CLK, CLKN and VIN, VINN package lands is necessary Note: These values have been calculated with RO4003 dielectric material Figure - Board Layout for the Differential Analog and Clock Inputs with RO4003 e = 40 µm 400 µm 870 µm 400 µm RO4003 AGND 70 µm 00 µm Note: The analogue inputs and clock inputs are AC coupled with 0 nf very close to the SMA connectors - EV0AS80x-EB Evaluation Kit User Guide

9 Hardware Description Figure - Recommended Clearance Under CLK, CLKN, and VIN, VINN on the Ground Plane 70 µm 400 µm 3 Digital Output Data The high speed differential output signals (digital output, clock output), are routed in parallel with 50Ω impedance, 370 µm width and a pitch of 077 mm Max difference between any two signals = ±5mm Max difference between longest and shortest data per port = ±mm Max difference between two signals of the same differential pair (Xi, XiN) = ±05mm (where X = A, B, C or D, i = 0 9) Note: These values have been calculated with RO4003 dielectric material Figure -3 Recommended Routing on RO4003 for Digital Output Data Signals e = 40 µm 370 µm 400 µm 370 µm RO4003 DGND 770 µm 00 µm 4 RSTN The RSTN signal is a single-ended signal with 50Ω impedance Figure -4 Recommended Routing on RO4003 for RSTN Signal 430 µm e = 40 µm RO4003 DGND 00 µm EV0AS80x-EB Evaluation Kit User Guide -3

10 Hardware Description 5 SA, RSx, TMx, SDA, SDAEN, GA, OA, DECN, Diode These are "static" signals They are routed in single-ended 50Ω impedance Figure -5 Recommended Routing on RO4003 for Static Signal e = 40 µm 430 µm RO4003 DGND 00 µm 6 Ground Layers There are separated planes for the AGND and the DGND on the PCB These planes must be reunited via 0Ω resistors Only the input clock and analogue input are referenced to AGND, the other parts of the ADC are referenced to DGND Important note: AGND and V CCO are not superimposed in order to avoid coupling effects V CC3 and V CC5 are referenced to AGND while V CCO is referenced to DGND 7 Power Supplies Layers 3 and 4 are dedicated to power supply planes: V CC5 : ADC Analog part supply (V CC5 = 5V) V CC3 : ADC Analogue Core and Digital parts supply (V CC3 = 33V) V CCO : ADC Output buffers supply (V CCO = 5V) 33V: external reference for GA, OA, SA and SDA commands The supply traces are low impedance and are surrounded by two ground planes (layer and 5) Each incoming power supply is bypassed at the banana jack by a µf Tantalum capacitor in parallel with a 00 nf chip capacitor Each power supply is decoupled as close as possible to the EV0AS80x device by 0 nf in parallel with 00 pf surface mount chip capacitors Note: The decoupling capacitors are superimposed with the 00 pf capacitor mounted first -4 EV0AS80x-EB Evaluation Kit User Guide

11 Section 3 Operating Characteristics 3 Introduction This section describes a typical configuration for operating the EV0AS80x 0-bit 5 Gsps ADC, evaluation board The analogue input signals and the sampling clock signal should be accessed in a differential fashion Band pass filters should also be used to optimize the performance of the ADC both on the analog input and on the clock It is necessary to use a very low jitter source for the clock signal (recommended maximum jitter = 5 fs rms) Note: The analogue inputs and clock are AC coupled on the board 3 Operating Procedure Connect the power supplies and ground accesses through the dedicated banana jacks V CC5 = 5V, V CC3 = 33V, V CCO = 5V and board supply = 33V Connect the clock input signals The clock input level is typically 4 dbm and should not exceed 0 dbm (into 00 differential) The clock frequency should be set to 5 GHz (for operation in : or :4 DEMUX Ratio) 3 Connect the analogue input signals (the board has been designed to allow only AC coupled analogue inputs) Use a low-phase noise High Frequency generator as well as a band pass filter to optimize the analogue input performance The analogue input Full Scale is 500mV peak-to-peak around zero (analogue input providing the Input common mode) It is recommended to use the ADC with an input signal of dbfs max (to avoid saturation of the ADC) 4 Connect the high speed acquisition system probes to the output connectors The digital data are differentially terminated on-board (00Ω) however, they can be probed either in differential 5 Switch on the ADC power supplies (recommended power up sequence: simultaneous or in the following order: V CC3 = 33V, V CC5 = 5V, V CCO = 5V and board supply 33V) 6 Turn on the RF clock generator 7 Turn on the RF signal generator EV0AS80x-EB Evaluation Kit User Guide 3-

12 Operating Characteristics The EV0AS80x-EB evaluation board is now ready for operation Note: An external reset (RSTN) SMA connector or switch is available in case it is necessary to reset the ADC during operation (it is not mandatory to perform an external reset on the ADC for proper operation of the ADC as a power up reset already implemented) This reset is 5V CMOS compatible It is active low (inactive by default on the board) 33 Electrical Characteristics Values in the table below are given for information only, for more accurate values refer to datasheet Table 3- Recommended Conditions of Use Parameter Symbol Comments Typ Unit V CC5 5 V Power supplies V CC3 33 V V CC0 5 V Differential analog input voltage (Full Scale) Clock input power level (Ground common mode) V IN V INN 00Ω differential 500 mvpp P CLK P CLKN 00Ω differential input 4 dbm Unless otherwise stated, requirements apply over the full operating temperature range (for performance) and at all power supply conditions Table 3- Electrical Characteristics Parameter Symbol Min Typ Max Unit Test level RESOLUTION 0 bit,6 ESD CLASSIFICATION > 000V (HBM model) V NA POWER REQUIREMENTS Power Supply voltage - Analog - Analog Core and Digital - Output buffers VCC5 VCC3 VCCO V V V,6 Power Supply current in : DEMUX Ratio - Analog - Analog Core and Digital - Output buffers I_VCC5 I_VCC3 I_VCCO ma ma ma,6 Power Supply current in : DEMUX Ratio - Analog - Analog Core and Digital - Output buffers I_VCC5 I_VCC3 I_VCCO ma ma ma,6 Power Supply current in :4 DEMUX Ratio - Analog - Analog Core and Digital - Output buffers I_VCC5 I_VCC3 I_VCCO ma ma ma,6 Power dissipation - : Ratio with standard LVDS output swing - : Ratio with standard LVDS output swing - :4 Ratio with standard LVDS output swing PD PD PD W W W,6 3- EV0AS80x-EB Evaluation Kit User Guide

13 Operating Characteristics Table 3- Electrical Characteristics (Continued) Parameter Symbol Min Typ Max Unit Test level LVDS Data and Data Ready Outputs Logic compatibility LVDS differential Output Common Mode () VOCM V,6 Differential output ()() VODIFF mvp,6 Output level High (3) VOH 5 V,6 Output level Low (3) VOL 5 V,6 Output data format Binary,6 ANALOG INPUT Input type AC coupled Analog Input Common Mode (for DC coupled input) 3 V Full scale input voltage range (differential mode) VIN VINN mvp mvp,6 Full scale analog input power level PIN 5 dbm,6 Analog input capacitance (die only) CIN 03 pf 5 Input leakage current (VIN = VINN = 0V) IIN 50 µa 5 Analog Input resistance (Differential) RIN Ω,6 CLOCK INPUT (CLK, CLKN) Input type DC or AC coupled Clock Input Common Mode (for DC coupled clock) VICM V,6 Clock Input power level (low phase noise sinewave input) at 5 GHz PCLK dbm 4 00Ω differential Clock input swing (differential voltage) at 5 GHz VCLK VCLKN ±447 ±708 ±000 mvp 4 Clock input capacitance (die only) CCLK 03 pf 4 Clock Input resistance (Differential) RCLK Ω 4 RSTN (active low) Logic compatibility 5V CMOS compatible Input level High V IH 0 V,6 Input level Low V IL 04 V,6 DIGITAL INPUTS (RS0, RS, DECN, SDAEN, TM, TM0) Logic low - Resistor to ground - Voltage level - Input current R IL V IL I IL Ω V µa,6 Logic high - Resistor to ground - Voltage level - Input current R IH V IH I IH 0k 0 infinite 50 Ω V µa,6 OFFSET, GAIN & SAMPLING DELAY ADJUST SETTINGS (OA, GA, SDA) Min voltage for minimum Gain, Offset or SDA Analog_min *Vcc3/3 05 V,6 EV0AS80x-EB Evaluation Kit User Guide 3-3

14 Operating Characteristics Table 3- Electrical Characteristics (Continued) Parameter Symbol Min Typ Max Unit Test level Max voltage for maximum Gain, Offset or SDA Analog_max *Vcc3/ V,6 Input current for min setting I min 00 µa,6 Input current for nominal setting I nom 50 µa,6 Input current for max setting I max 00 µa,6 ANALOG SETTINGS (SA) SA voltage for default swing value Smax *Vcc3/3,6 SA voltage for minimum swing value S min *Vcc3/3 05,6 Input current (low, for default swing value I min 50 µa,6 Input current (high) for min swing value I max 50 µa,6 Notes: Assuming 00Ω termination ASIC load VODIFF can be lowered down to 00 mv with SA pin to reduce power consumption 3 V OH min and V OL max can never be 5V at the same time when VODIFFmin 3-4 EV0AS80x-EB Evaluation Kit User Guide

15 Section 4 Application Information 4 Analogue Input The analogue input (VIN, VINN) are entered in differential AC coupled mode as described in Figure 4- It is recommended to use a differential source to drive the analogue inputs of this ADC (external balun or differential amplifier) Please refer to Section Test Bench Description for more information In order to optimize the performance of the ADC, it is also recommended to use a band pass filter on the analogue input path Figure 4- Differential Analogue Inputs Implementation VIN VNN 0 nf VIN VINN EV0AS80x 0 nf 4 Clock Input It is recommended to use a differential source to drive the clock input The clock is AC coupled via 0 nf capacitors as described in Figure 4- Please refer to Section Test Bench Description for more information Figure 4- Clock Input Implementation CLK CLKN 0 nf CLK CLKN EV0AS80x 0 nf The jitter performance on the clock is crucial to obtain optimum performance from the ADC We thus recommend to use a very low phase noise clock and to filter the clock signal if a fixed frequency is used EV0AS80x-EB Evaluation Kit User Guide 4-

16 Application Information 43 RESETN input The RESETN signal can be applied by using a switch (SW5): By default, RESETN is floating, it is not active, the ADC is in normal mode; When the switch is activated, it connects RESETN to ground, which performs a reset on the ADC (reset of the clock circuitry, after reset, the first data will be seen on port A) It is also possible to apply a signal via the SMA connector, providing R4 is connected (0 ohm) and R3 is removed The reset signal is implemented as illustrated in Figure 4-3 Figure 4-3 RESETN Input Implementation RESETN EV0AS80x R4 0Ω NC RESETN R3 0Ω R 0Ω DGND 44 SA, GA, OA, SDA and SDAEN Commands 44 GA and OA Commands These signals are connected by default via their respective jumper to the command middle value (ie V CC3 /3 = V) When the jumper is removed, it is possible to tune the OA and GA commands between ( V CC3 /3 05V) to ( V CC3 /3 + 05V) 4- EV0AS80x-EB Evaluation Kit User Guide

17 Application Information Figure 4-4 GA and OA Commands Implementation 33V 33V 33V 33V R R4 R74 R76 P P3 R3 R5 R75 R77 DGND DGND DGND DGND GA OA EV0AS80x EV0AS80x With: R = R74 = 40Ω R4 = R76 = 649Ω P = P3 = K R3 = R75 = 05 kω R5 = R77 = 33 kω Figure 4-5 GA and OA Commands Jumper Settings GA and OA set to default middle value x V CC3 /3 GA and OA tunable between ( x V CC3 /3-05V) and ( x V CC3 /3 + 05) EV0AS80x-EB Evaluation Kit User Guide 4-3

18 Application Information 44 SA Command This signal is connected by default via its jumper to the command middle value (ie V CC3 /3 = V) When the jumper is removed, it is possible to tune the OA and GA commands between ( V CC3 /3 05V) to ( V CC3 /3 + 05V) Figure 4-6 SA Command Implementation 33V 33V R6 R8 P R7 R9 DGND DGND SA EV0AS80x With: R6 = kω R8 = 649Ω P = K R7 = 6 kω R9 = 33 kω Figure 4-7 SA Command Jumper Settings SA set to default middle value x V CC3 /3 SA tunable between ( x V CC3 /3) and x V CC3 /3-05V) 4-4 EV0AS80x-EB Evaluation Kit User Guide

19 Application Information 443 SDAEN and SDA Commands SDAEN signal allows to activate the SDA command when its jumper is OUT or connected as described in Figure 4-9 on page 5 When the SDA function is activated via SDAEN, then it is possible to tune the sampling delay of the ADC by tuning the SDA command between ( V CC3 /3 05V) and ( V CC3 /3 + 05V) by ±40 ps around the nominal Aperture delay of the ADC Figure 4-8 SDAEN and SDA Commands Implementation 33V 33V 33V R8 NC R78 R80 P4 R8 DGND DGND DGND SDAEN SDA EV0AS80x EV0AS80x With: R8 = 0 kω (NC: can be connected to provide a true High level to SDAEN) R78 = 40Ω R80 = 649Ω P4 = K R79 = 05 kω R8 = 33 kω Figure 4-9 SDAEN Command Jumper Settings SDAEN activated: JUMPER ON SDAEN inactivated: JUMPER OUT EV0AS80x-EB Evaluation Kit User Guide 4-5

20 Application Information Figure 4-0 SDA Command Jumper Settings SDA set to default middle value x V CC3 /3 SDA tunable between ( x V CC3 /3-05) and ( x V CC3 /3 + 05) 45 RSx, TMx and DECN Commands The RSx, TMx and DECN functions are implemented on board with a jumper which can be ON or OUT (default setting is when the Jumpers are OUT, refer to Figure 4- on page 7) A 0 kω resistor can be connected in case a pull up is necessary to force a high level on these signals This resistor is not connected Figure 4- RSx, TMx and DECN Commands Implementation 33V RSx TMx 0 kω NC DECN The default setting for RSx, TMx and DECN is when their respective jumper is OUT (refer to Figure 4-) This gives a default setting of the ADC as described below (refer also to Table 4-): RS = RS0 = Logic High = Jumper OUT -> : DMUX mode TM = TM0 = Logic High = Jumper OUT -> Test mode inactive DECN = Logic High = Jumper OUT -> Decimation Mode inactive DGND 4-6 EV0AS80x-EB Evaluation Kit User Guide

21 Application Information Table 4- RSx, TMx and DECN Commands Jumper Position When the jumper are on (refer to Figure 4-), the different settings are described in Table 4- Function DECN RS<:0> TM<:0> Logic Level Jumper position Description 0 ON Decimation by 8 OUT Normal conversion (no decimation) RS : ON RS0 : OUT RS : OUT RS0 : OUT RS : OUT RS0 : ON RS : ON RS0 : ON TM : ON TM 0 : OUT TM : OUT TM 0 : OUT TM : OUT TM 0 : ON TM : ON TM0 : ON : DEMUX Ratio (Port A) : DEMUX Ratio (Ports A and B) :4 DEMUX Ratio (Ports A, B C and D) Not used Static Test (all 0 s at the output for VOL test) Normal conversion mode (default mode) Static Test (all s at the output for VOH test) Dynamic test (checker board pattern = all bits toggling from 0 to or to 0 every cycle with or patterns) Figure 4- RSx, TMx, DECN Command Jumper Settings Jumpers OUT Jumpers ON EV0AS80x-EB Evaluation Kit User Guide 4-7

22 Application Information 46 Output Data The digital outputs are compatible with LVDS standard They are on-board 00Ω differentially terminated as described in Figure 4-3 Figure 4-3 Differential Digital Outputs Implementation Connector 00Ω ADC Double row 54 mm pitch connectors are used for the digital output data The upper row is connected to the signal while the lower row is connected to Ground, as illustrated in Figure 4-5 on page 3 and Figure 4-6 on page 4 The connectors are vertical connectors Figure 4-4 Differential Digital Outputs 54 mm Pitch Connector (X = A, B) X0 X0N X XN X8 X8N X9N X9N GND GND GND GND GND GND GND GND Figure 4-5 Differential Digital Outputs 54 mm Pitch Connector (Port A) Figure 4-6 Differential Digital Outputs 54 mm Pitch Connector (Port B) B0 B0N B BN B BN B3 B3N B4 B4N B5 B5N B6 B6N B7 B7N B8 B8N B9 B9N A0 A0N A AN A AN A3 A3N A4 A4N A5 A5N A6 A6N A7 A7N A8 A8N A9 A9N 4-8 EV0AS80x-EB Evaluation Kit User Guide

23 Application Information Figure 4-7 Differential Digital Outputs 54 mm Pitch Connector (X = C, D) X9N X9 X8N X8 XN X X0N X0 GND GND GND GND GND GND GND GND Figure 4-8 Differential Digital Outputs 54 mm Pitch Connector (Port C) Figure 4-9 Differential Digital Outputs 54 mm Pitch Connector (Port D) D9N D9 D8N D8 D7N D7 D6N D6 D5N D5 D4N D4 D3N D3 DN D DN D D0N D0 C9N C9 C8N C8 C7N C7 C6N C6 C5N C5 C4N C4 C3N 3C CN C CN C C0N C0 Figure 4-0 Differential Digital Outputs 54 mm Pitch Connector (DR, DRN Signal) DR DRN The data are output in Binary format and in double data rate (the output clock frequency is half the data rate and thus half the input clock frequency in : DMUX mode, or ¼ the input clock frequency in : DMUX mode and /8 the input clock frequency in DMUX :4 mode) EV0AS80x-EB Evaluation Kit User Guide 4-9

24 Application Information 47 Diode for Junction Temperature Monitoring Two mm banana jacks are provided for the die junction temperature monitoring of the ADC One banana jack is labeled DIODEA and should be applied a current of up to ma (via a multimeter used in current source mode) and the second one is connected to DIODEC Figure 4- Die Temperature Monitoring Test Setup DIODEA Protection Diodes To DIODEA V ma Banana jacks To DIODEC DIODEC Note: The protection diodes are NC 48 Test Bench Description Figure 4- Test Bench Description Band pass filter Input Signal Generator Thermal system Temperature range -80 to +63 VINN Evaluation Board balun VIN ADC 0 -bit Digital Acquisition System Band pass filter Clock Signal Generator balun Supply Computer Equipment (for example) Input Signal Generator: Agilent E446B Clock Signal Generator: Agilent E446B Power Supply: Agilent 669A Logic Analyser: HP6500C Balun: MACOM-H9 (MHz => GHz) Band pass filter: LORCH (500MHz => GHz) & LORCH (GHz => GHz) 4-0 EV0AS80x-EB Evaluation Kit User Guide

25 Section 5 Ordering Information 5 Ordering Information Table 5- Ordering Information Part Number Package Temperature Range Screening Level Comments EV0AS80AGS-EB CI-CGA55 Ambient Prototype Evaluation board EV0AS80x-EB Evaluation Kit User Guide 5-07A HIREL /

26 Ordering Information 5- EV0AS80x-EB Evaluation Kit User Guide 07A HIREL /

27 Section 6 Appendix 6 EV0AS80x-EB Electrical Schematics Figure 6- Power Supplies Bypassing VCCO VCCA 3 VCCA 5 3V3 VCC0 J J C uf 6V K C 00nF 50V K PT4 VCC3 J4 J3 C3 uf 6V K C4 00nF 50V K PT3 VCC5 J6 J5 C5 uf 6V K C6 00nF 50V K PT Vcarte J8 J7 C7 uf 6V K C8 00nF 50V K PT AGND AGND Figure 6- Power Supplies Decoupling VCCO C3 00pF J 50V C4 C5 0nF 00pF 5V K J 50V C6 C7 0nF 00pF 5V K J 50V C8 C9 0nF 00pF 5V K J 50V C0 C 0nF 00pF 5V K J 50V C C3 0nF 00pF 5V K J 50V C4 C5 0nF 00pF 5V K J 50V C6 C7 0nF 00pF 5V K J 50V C8 0nF 5V K VCCA 3 C6 00pF J 50V C6 C63 0nF 00pF 5V K J 50V C64 C65 0nF 00pF 5V K J 50V C66 C67 0nF 00pF 5V K J 50V C68 0nF 5V K AGND VCCA 5 C77 00pF J 50V C78 C79 0nF 00pF 5V K J 50V C80 C8 0nF 00pF 5V K J 50V C8 C83 0nF 00pF 5V K J 50V C84 0nF 5V K AGND EV0AS80x-EB Evaluation Kit User Guide 6-

28 Appendix Figure 6-3 Electrical Schematics 3V3 3V3 3V3 3V3 3V3 3V3 DiodeA 3V3 3V3 3V3 3V3 3V3 3V3 3V3 OA GA SA 3V3 3V3 SD A 3 P4 K 3 P K PT R8 33K 00W F PT8 C 00nF K50V SW CR BAV99 70V NE R W F 3 R 0K 00W NE SW 6 J6 3 J PT5 R7 0K 00W NE J R5 0K 00W NE R4 00W NE J 3 CR3 BAV99 70V NE PT0 SW SD AEN J 0 SW 4 R79 05K 00W F R6 0K 00W NE T R N4 P4 P4 N4 T4 R4 T3 R3 T4 P3 N3 SD A SD AEN OA GA SA DE CN TM 0 TM RS 0 RS RS TN DIOD EA DIOD EC J TM RS 0 RS TN DiodeC /3 CONTROL EV0AS80x MN -A SW5 SW 8 CR4 BAV99 R W SW 8 J3 3 R W F 3 R73 0K 00W NE PT7 DE CN SW 9 PT PT4 SW 0 SW SW 3 J3-A SM A-bord-de-cart e 3 J3-B SM A-bord-de-cart e J5 J4 70V NE J V V V3 V4 V5 V R 0 00W R3 00W PT5 J J 0 SW 5 34 SW ITCH-STTS KHUB B RS PT9 R7 0K 00W NE CR BAV99 70V NE J 3 PT6 SW 6 SW 7 TM 0 R W SW 7 J7 3 PT3 R8 0K 00W NE SW 9 J4 3 J R75 05K 00W F R W F R77 33K 00W F F R 40 00W F R3 05K 00W F R W F C 00nF K50V 3 P3 K C9 00nF K50V R5 33K 00W F 3 P K R6 K 00W F R7 6K 00W F C0 00nF K 50V R9 33K 00W F F RSTN DIODE A NC NC DIODE C NC NC PT6 PT7 SW 0 6- EV0AS80x-EB Evaluation Kit User Guide

29 Appendix Figure 6-4 Electrical Schematics (Analogue and Clock Input) J-B SM A-bord-de-carte V V V3 V4 V5 V AGND AGND J-A SM A-bord-de-carte 3 AGND J-A SM A-bord-de-carte VIN 3 C93 0nF 5V K C94 0nF 5V K VIN VINN /3 EV0AS80x MN -B DA TA A A0 A0N A AN A AN A3 A3N A4 A4N A5 A5N A6 A6N A7 A7N A8 A8N A9 A9N P P N N M M L3 M3 L L K K K3 J3 J J H H H3 G3 A0 A0N A AN A AN A3 A3N A4 A4N A5 A5N A6 A6N A7 A7N A8 A8N A9 A9N CLK AGND J-B SM A-bord-de-carte AGND AGND J9-B SM A-bord-de-carte AGND AGND J9-A SM A-bord-de-carte 3 AGND J0-A SM A-bord-de-carte 3 CLK CLKN T9 T0 T6 R6 VIN VINN CLK CLKN DA TA B DATA READY DA TA C DA TA D B0 B0N B BN B BN B3 B3N B4 B4N B5 B5N B6 B6N B7 B7N B8 B8N B9 B9N DR DRN C0 C0N C CN C CN C3 C3N C4 C4N C5 C5N C6 C6N C7 C7N C8 C8N C9 C9N D0 D0N D DN D DN D3 D3N D4 D4N D5 D5N D6 D6N D7 D7N D8 D8N D9 D9N F F E3 F3 E E D D A4 B4 A5 B5 C6 C5 A6 B6 A7 B7 C7 C8 A9 B9 F6 F5 E4 F4 E6 E5 D6 D5 A3 B3 A B C C A B A0 B0 C0 C9 P6 P5 N6 N5 M 6 M 5 L4 M 4 L6 L5 K6 K5 K4 J4 J6 J5 H6 H5 H4 G 4 B0 B0N B BN B BN B3 B3N B4 B4N B5 B5N B6 B6N B7 B7N B8 B8N B9 B9N C0 C0N C CN C CN C3 C3N C4 C4N C5 C5N C6 C6N C7 C7N C8 C8N C9 C9N D0 D0N D DN D DN D3 D3N D4 D4N D5 D5N D6 D6N D7 D7N D8 D8N D9 D9N DR DRN R83 00 F 00W AGND J0-B SM A-bord-de-carte V V V3 V4 V5 V V V V3 V4 V5 V V V V3 V4 V5 V C95 0nF 5V K C96 0nF 5V K TSM-04-0-L-DV-A J J 3 J J 5 J J 7 J J AGND AGND EV0AS80x-EB Evaluation Kit User Guide 6-3

30 Appendix Figure 6-5 Electrical Schematics (Output Connectors Ports A and B) 3V3 3V3 3V3 3V3 R6 F W R8 F W NC Aligneme ntpin TSM-6-0-L-DV J8 53 J8 J8 R40 F W R4 F W NC Aligneme ntpin TSM-6-0-L-DV J9 53 J9 J9 00 Oh ms sha lbeput outside togetv and V4 3 J8 J8 5 J8 J Oh ms sha lbe put outside to getv and V4 3 J9 J9 5 J9 J Oh ms sha lbeput outside togetv and V4 7 J8 J8 9 J8 J Oh ms sha lbe put outside toget V and V4 7 J9 J9 9 J9 J9 8 0 R7 F 49 00W R9 F 49 00W A0 A0N A AN R8 00 F 00W R9 00 F 00W J8 J8 3 J8 J8 5 J8 J8 7 J8 J R4 F 49 00W R43 F 49 00W B0 B0N B BN R30 00 F 00W R3 00 F 00W J9 J9 3 J9 J9 5 J9 J9 7 J9 J A AN R0 00 F 00W 9 J8 J8 J8 J8 0 B BN R3 00 F 00W 9 J9 J9 J9 J9 0 A3 A3N R 00 F 00W 3 J8 J8 5 J8 J8 4 6 B3 B3N R33 00 F 00W 3 J9 J9 5 J9 J9 4 6 A4 A4N R0 00 F 00W 7 J8 J8 9 J8 J B4 B4N R34 00 F 00W 7 J9 J9 9 J9 J A5 A5N R 00 F 00W 3 J8 J8 33 J8 J B5 B5N R35 00 F 00W 3 J9 J9 33 J9 J A6 A6N R 00 F 00W 35 J8 J8 37 J8 J B6 B6N R36 00 F 00W 35 J9 J9 37 J9 J A7 A7N R3 00 F 00W 39 J8 J8 4 J8 J B7 B7N R37 00 F 00W 39 J9 J9 4 J9 J A8 A8N R4 00 F 00W 43 J8 J8 45 J8 J B8 B8N R38 00 F 00W 43 J9 J9 45 J9 J A9 A9N R5 00 F 00W 47 J8 J8 49 J8 J B9 B9N R39 00 F 00W 47 J9 J9 49 J9 J J8 J8 5 5 J9 J9 5 NC AlignementPin 54 J8 NC Aligneme ntpin 54 J9 PORT A PORT B 6-4 EV0AS80x-EB Evaluation Kit User Guide

31 Appendix Figure 6-6 Electrical Schematics (Output Connectors Ports C and D) TSM-6-0-L-DV TSM-6-0-L-DV NC Aligneme ntpin 53 J0 NC Aligneme ntpin 53 J J0 J0 J J C9N C9 R58 00 F 00W 3 J0 J0 5 J0 J0 4 6 D9N D9 R70 00 F 00W 3 J J 5 J J 4 6 C8N C8 R59 00 F 00W 7 J0 J0 9 J0 J0 8 0 D8N D8 R7 00 F 00W 7 J J 9 J J 8 0 C7N C7 R44 00 F 00W J0 J0 3 J0 J0 4 D7N D7 R5 00 F 00W J J 3 J J 4 C6N C6 R45 00 F 00W 5 J0 J0 7 J0 J0 6 8 D6N D6 R53 00 F 00W 5 J J 7 J J 6 8 C5N C5 R46 00 F 00W 9 J0 J0 J0 J0 0 D5N D5 R60 00 F 00W 9 J J J J 0 C4N C4 R47 00 F 00W 3 J0 J0 5 J0 J0 4 6 D4N D4 R6 00 F 00W 3 J J 4 5 J J 6 C3N C3 R48 00 F 00W 7 J0 J0 9 J0 J D3N D3 R6 00 F 00W 7 J J 9 J J V3 3V3 CN C CN C R49 00 F 00W R50 00 F 00W 3 J0 J0 33 J0 J0 35 J0 J0 37 J0 J V3 3V3 DN D DN D R63 00 F 00W R64 00 F 00W 3 J J 33 J J 35 J J 37 J J R54 F W R56 F W C0N C0 R5 00 F 00W 39 J0 J0 4 J0 J R66 F W R68 F W D0N D0 R65 00 F 00W 39 J J 4 J J Oh ms sha lbeput outside togetv and V4 43 J0 J0 45 J0 J Ohm s sha lbe put outside to getv and V4 43 J J 45 J J Oh ms sha lbeput outside togetv and V4 47 J0 J0 49 J0 J Ohm s sha lbe put outside to getv and V4 47 J J 49 J J J0 J0 5 5 J J 5 NC Aligneme ntpin 54 J0 NC Aligneme ntpin 54 J R55 F 49 00W R57 F 49 00W PORT C R67 F 49 00W R69 F 49 00W PORT D EV0AS80x-EB Evaluation Kit User Guide 6-5

32 Appendix 6 EV0AS80x-EB Board Layers Figure 6-7 Top Layer EV0AS8X-EVALUATION-BOARD 90066B B SA GA OA A0 DIOD EA DIOD EC A A GN D RS TN A3 A4 B0 A5 B B A6 A7 B3 A8 B4 A9 B5 CLK B6 B7 B8 CLKN B9 DR VIN C9 C8 VINN C7 D9 C6 D8 C5 AG ND D7 D6 C4 C3 VCC5 D5 D4 C C D3 C0 AG ND SD A D VCC3 D 3V3 DG ND VCCO DG ND SDAE N RS 0 RS TM 0 TM DECN D0 EV0AS8X-EVALUATION BOARD LAYER COMPONENT SIDE 6-6 EV0AS80x-EB Evaluation Kit User Guide

33 Appendix Figure 6-8 Bottom Layer 6 B LAYER 6 SOLDER SIDE EV0AS80x-EB Evaluation Kit User Guide 6-7

34 T R P N M L K J H G F E D C B A Appendix Figure 6-9 Equipped Board (Top) Dotted components are not wired FX FX7 FX4 R9 R8 C0 J7 R5 PT3 R4 C9 J6 R77 PT R76 C J3 PT8 R7 R6 PT6 PT7 R9 R8 P P P3 R8 R6 R7 R R3 R74 R75 R9 R4 J3 R4 R R3 SW 5 R PT5 SW 3 R0 R R0 J8 R40 R43 R4 R30 R3 SW R R R3 R3 R33 R34 J9 FX R4 R35 J9 C95 R5 R36 R37 R38 J0 C96 R39 MN R83 J J C93 R58 R59 J C94 R44 R45 R70 FX8 R7 R46 R47 C5 C6 R5 R53 R48 J0 PT R60 R49 R50 R6 C3 C4 PT3 SW 4 PT9 J4 P4 R79 R78 R6 R63 R64 R65 J R5 R56 R57 R54 R55 R8 R80 C R68 PT PT4 R69 R66 PT0 PT4 PT PT6 PT5 PT7 R67 C8 C7 C C R8 R6 R5 R7 R7 R73 SW FX3 SW 0 SW SW 0 SW 6 SW 4 SW 8 FX5 FX6 6-8 EV0AS80x-EB Evaluation Kit User Guide

35 R9 R90 Appendix Figure 6-0 Equipped Board (Bottom) Dotted components are not wired R93 R97 R 7 R 07 R88 R0 R94 R9 R05 R5 R 6 R R98 R0 R 03 R89 R99 R04 R85 R95 R 00 R87 R06 J6 R86 R96 R84 J4 RED J5 J3 J5 BLACK J4 CR4 CR3 CR CR C7 C5 C8 C6 C6 C5 C67 C68 C6 C6 C84 C83 C7 C8 C77 C78 C0 C9 C4 C3 C66 C79 C80 C3 C C4 C C65 C63 C64 C8 C8 Put all 00 pf capacitor below 0 nf capacitor RED BLACK RED BLACK J J J7 J8 BLACK RED BLACK RED EV0AS80x-EB Evaluation Kit User Guide 6-9

36 Appendix 6-0 EV0AS80x-EB Evaluation Kit User Guide

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