Product Specifications. General Information. Order Information: VL493T5663D-E6M/D5M/CCM-S1 REV: 1.0. Pin Description PART NO.:

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1 General Information 2GB 256Mx72 DDR2 SDRAM ECC REGISTERED SORDIMM 200PIN Description The VL493T5663D is a 256Mx72 DDR2 SDRAM high density SORDIMM. This memory module consists of eighteen CMOS 128Mx8 bit with 8 banks DDR2 synchronous DRAMs in BGA packages, two 25bit registered buffer in BGA package, a zero delay PLL clock in BGA package, and a 2K EEPROM in an 8pin MLF package. This module is a 200pin smalloutline dual inline memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR2 SDRAM. Features 200pin, registered smalloutline dual inline memory module (SORDIMM) JEDEC pin out Supports ECC error detection and correction Fast data transfer rates: PC25300, PC24200, PC23200 VDD = VDDQ = 1.8V JEDEC standard 1.8V (SSTL_18 compatible) VDDSPD = 1.7V to 3.6V Differential data strobe (DQS, DQS# ) option Differential clock inputs (CK, CK#) Fourbit prefetch architecture DLL aligns DQ and DQS transition with CK Nominal and dynamic ondie termination (ODT) Programmable CAS# latency: 5 (DDR2667), 4 (DDR2533), 3 (DDR2400) Write latency = Read latency 1 tck Eight internal component banks for concurrent operation Programmable burst; length (4, 8) Adjustable dataoutput drive strength Auto & self refresh, (8K/64ms refresh) Serial presence detect (SPD) with EEPROM Gold edge contacts Leadfree, RoHS compliant PCB: Height 29.85mm (1.175 ), double sided component Operating temperature (TOPER): 40 o C to +85 o C (module screening using commercial DRAM) Pin Description Pin Name Function A0~A13 Address Inputs A10/AP Address Input/ Autoprecharge BA0~BA2 Bank Address Inputs ~3 Data Input/Output DQS0~DQS8 Data Strobes DQS0#~DQS8# Data Strobes Complement ODT0, ODT1 Ondie Termination Control CK, CK# Clock Input CKE0, CKE1 Clock Enables CS0#, CS1# Chip Selects RAS# Row Address Strobes CAS# Column Address Strobes WE# Write Enable CB0~CB7 Check Bits DM0~DM8 Data Masks VDD Voltage Supply 1.8V +/ 0.1V Order Information: VL493T5663DE6 M X S1 S1: Screening temperature DRAM DIE (Option) VSS Ground SA0~SA1 SPD Address SDA SPD Data Input/Output SCL SPD Clock Input VDDSPD SPD Voltage Supply 1.7V to 3.6V DRAM component: K4T1G084QEHCE6 (Leadfree/ RoHS) DRAM MANUFACTURER M MICRON MODULE SPEED E6: CL5 D5: CL4 CC: CL3 VL: Leadfree/RoHS VREF NC SSTL_18 Reference Voltage No Connect Tel Tomas, Rancho Santa Margarita, CA USA 1

2 Pin Configuration 200PIN DDR2 SORDIMM FRONT 200PIN DDR2 SORDIMM BACK Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF VDD 151 VSS 2 VSS 52 VSS 102 A6 152 VSS A5 153 DQS5# 4 DQ A4 154 DM5 5 VSS 55 VSS 105 A3 155 DQS VDD 156 VSS A2 157 VSS 8 VSS 58 VSS 108 A1 158 DQ46 9 DQS0# VDD 159 DQ42 10 DM0 60 DM3 110 A0 160 DQ47 11 DQS0 61 VSS 111 A10/AP 161 DQ43 12 VSS 62 VSS 112 BA1 162 VSS 13 VSS 63 DQS3# 113 BA0 163 VSS VDD DQS3 115 RAS# 165 DQ WE# VSS 117 VDD 167 DQ49 18 VSS 68 VSS 118 CS0# 168 VSS 19 VSS CAS# 169 VSS CB4 120 ODT0 170 DM6 21 DQ CS1# 171 DQS6# CB5 122 A VSS 23 DQ9 73 VSS 123 VDD 173 DQS6 24 VSS 74 VSS 124 VDD VSS 75 CB0 125 ODT1 175 VSS 26 DM1 76 DM8 126 CK DQS1# 77 CB1 127 NC VSS 78 VSS 128 CK# 178 VSS 29 DQS1 79 VSS CB6 130 VSS VSS 81 DQS8# 131 VSS 181 VSS CB DQS VSS 84 VSS VSS VSS 135 DQS4# CB2 136 VSS 186 DM7 37 VSS 87 CKE0 137 DQS4 187 VSS CB3 138 DM CKE1 139 VSS 189 DQS7# 40 VSS 90 VSS 140 VSS 190 VSS NC DQS7 42 RESET# 92 BA VSS 93 VDD DM2 94 NC SDA 45 DQS2# 95 A VSS 195 VSS 46 VSS 96 A VSS 196 SCL 47 DQS2 97 A9 147 DQ VDD 148 DQ SA1 49 VSS 99 A7 149 DQ VDDSPD A8 150 DQ SA0 NC: No connect Tel Tomas, Rancho Santa Margarita, CA USA 2

3 Function Block Diagram RCS1# RCS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DQ4 DQ4 D0 DQ4 D DQ4 D4 DQ4 D13 DQS1 DQS1# DM1 DQS5 DQS5# DM5 DQ8 DQ DQ4 D1 DQ4 D10 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ4 D5 DQ4 D14 DQS2 DQS2# DM2 DQS6 DQS6# DM DQ4 D2 DQ4 D11 DQ48 DQ DQ4 D6 DQ4 D15 DQS3 DQS3# DM3 DQS7 DQS7# DM DQ4 D3 DQ4 D DQ4 D7 DQ4 D16 DQS8 DQS8# DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQ4 D8 DQ4 D17 CK0 CK0# RESET# P L L OE# PCK0PCK6, PCK8PCK9 > CK: SDRAMs D0D17 PCK0#PCK6#, PCK8#PCK9# > CK#: SDRAMs D0D17 PCK7 > CK: Registers PCK7# > CK#: Registers CS1# CS0# A0A13 BA0BA2 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 1:2 R E G I S T E R RCS1# > CS1#: SDRAMs D9D17 RCS0# > CS0#: SDRAMs D0D8 RA0RA13 >A0A13:SDRAMs D0D17 RBA0RBA2 > BA0BA2: SDRAMs D0D17 RRAS# > RAS#: SDRAMs D0D17 RCAS# > CAS#: SDRAMs D0D17 RWE# > WE#: SDRAMs D0D17 RCKE0 > CKE0: SDRAMs D0D8 RCKE1 > CKE1: SDRAMs D9D17 RODT0 > ODT0: SDRAMs D0D8 RODT1 > ODT1: SDRAMs D9D17 SCL Vss Serial PD WP A0 A1 A2 SA0 SA1 Vss SDA VDDSPD VDD/ VDDQ VREF Serial PD D0D17 D0D17 VSS D0D17 RESET# RST# PCK7 PCK7# Notes: 1. Unless otherwise noted, resistor values are 22 ohms +/5% Tel Tomas, Rancho Santa Margarita, CA USA 3

4 Absolute Maximum Ratings Symbol Parameter MIN MAX Unit VDD Voltage on VDD pin relative to VSS V VDDQ Voltage on VDDQ pin relative to VSS V VDDL Voltage on VDDL pin relative to VSS VIN, VOUT Voltage on any pin relative to VSS V TSTG Storage temperature IL IOZ Input leakage current; Any input 0V<VIN<VDD; VREF input 0V<VIN<0.95V; Other pins not under test = 0V Output leakage current; 0V<VOUT<VDDQ; DQs and ODT are disabled Address, BA, RAS#, CAS#, WE# 0 C ua CS#, CKE, ODT ua CK, CK# ua DM ua DQ, DQS, DQS# ua IVREF VREF supply leakage current; VREF = Valid VREF level ua DC Operating Conditions Symbol Parameter Min Typical Max Unit Notes VDD Supply voltage V 1 VDDQ I/O supply voltage V 4 VDDL VDDL supply voltage V 4 VREF I/O reference voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2 VTT I/O termination voltage VREF0.04 VREF VREF+0.04 V 3 Note: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD. 2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peaktopeak noise on VREF may not exceed +/1percent of the DC value. Peaktopeak AC noise on VREF may not exceed +/2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VDDQ tracks with VDD; VDDL tracks with VDD. Tel Tomas, Rancho Santa Margarita, CA USA 4

5 Operating Temperature Condition Symbol Parameter Rating Units Notes TOPER Operating temperature 40 to C 1,2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD At 40 to 85 o C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when 85 o C < TOPER <= 95 o C. Input DC Logic Level All voltages referenced to VSS Symbol Parameter Min Max Unit VIH(DC) Input High (Logic 1) Voltage VREF VDDQ V VIL(DC) Input Low (Logic 0) Voltage VREF V Input AC Logic Level All voltages referenced to VSS Symbol Parameter Min Max Unit VIH(AC) Input High (Logic 1) Voltage DDR2400 & DDR2533 VREF V VIH(AC) Input High (Logic 1) Voltage DDR2667 VREF V VIL(AC) Input Low (Logic 0) Voltage DDR2400 & DDR2533 VREF V VIL(AC) Input Low (Logic 0) Voltage DDR2667 VREF V Input/Output Capacitance TA=25 0 C, f=100mhz Parameter Symbol Min Max Unit Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#) CIN pf Input capacitance (CKE0, CKE1), (ODT0, ODT), (CS0#, CS1#) CIN pf Input capacitance (CK0, CK0#) CIN3 6 7 pf Input/Output capacitance (DQ, DQS, DQS#, DM, CB) CIO 9 12 pf Tel Tomas, Rancho Santa Margarita, CA USA 5

6 IDD Specification Condition Operating one bank activeprecharge current; t CK = t CK(IDD) ; t RC = t RC(IDD) ; t RAS = t RAS MIN(IDD) ; CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank activereadprecharge current; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0; t CK = t CK(IDD) ; t RC = t RC(IDD) ; t RAS = t RAS MIN(IDD); t RCD = t RCD(IDD) ; CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge powerdown current; All banks idle; t CK = t CK(IDD) ; CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; t CK = t CK(IDD) ; CKE is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; t CK = t CK(IDD) ; CKE is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Symbol DDR2667 (E6) DDR2533 (D5) DDR2400 (CC) Unit IDD0* ma IDD1* ma IDD2P** ma IDD2Q** ma IDD2N** ma Active powerdown current; Fast PDN Exit MRS(12) = ma All banks open; t CK = t CK(IDD) ; CKE is LOW; Other IDD3P** control and address bus inputs are STABLE; Data bus inputs are FLOATING. Slow PDN Exit MRS(12) = ma Active standby current; All banks open; t CK = t CK(IDD) ; t RP = t RP(IDD) ; t RAS = t RAS MAX(IDD) ; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst write current; All banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0; t CK = t CK(IDD) ; t RAS = t RAS MAX(IDD) ; t RP = t RP(IDD) ; CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0; t CK = t CK(IDD) ; t RAS = t RAS MAX(IDD) ; t RP = t RP(IDD) ; CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Burst refresh current; t CK = t CK(IDD) ; Refresh command at every t RFC(IDD) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Self refresh current; CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD3N** ma IDD4W* ma IDD4R* ma IDD5** ma Normal IDD6** ma Operating bank interleave read current; All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = t RCD(IDD) 1*t CK(IDD) ; t CK = t CK(IDD) ; t RC = t RC(IDD) ; t RRD = t RRD(IDD) ; t RCD = 1*t CK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING. IDD7* ma Notes: IDD specification is based on Micron Hdie components. *: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition. Tel Tomas, Rancho Santa Margarita, CA USA 6

7 AC TIMING PARAMETERS & SPECIFICATIONS Parameter Symbol DDR2667 (E6) DDR2533 (D5) DDR2400 (CC) Unit Min Max Max Min Max Min Clock Timing CL5 t CK (5) ps Clock Cycle Time CL4 t CK (4) ps CL3 t CK (3) ps CK highlevel width t CH(avg) t CK CK lowlevel width t CL(avg) t CK Half clock period t HP MIN (tch, tcl) MIN (tch, tcl) MIN (tch, tcl) ps Clock jitter t JIT ps Data Timing DQ output access time from CK/CK# t AC ps Dataout high impedance window from CK/CK# t HZ t AC(MAX) t AC(MAX) t AC(MAX) ps Dataout low impedance window from CK/CK# t LZ t AC(MiN) t AC(MAX) t AC(MiN) t AC(MAX) t AC(MiN) t AC(MAX) ps DQ and DM input setup time relative to DQS t DS ps DQ and DM input hold time relative to DQS t DH ps DQ and DM input pulse width ( for each input) t DIPW t CK Data hold skew factor t QHS ps DQDQS hold, DQS to first DQ to go nonvalid, per access t QH t HP t QHS t HP t QHS t HP t QHS ps Data valid output window (DVW) t DVW t QH t DQSQ t QH t DQSQ t QH t DQSQ ns Data Strobe Timing DQS input high pulse width t DQSH t CK DQS input low pulse width t DQSL t CK DQS output access time from CK/CK# t DQSCK ps DQS failing edge to CK risingsetup time t DSS t CK DQS failing edge from CK risinghold time t DSH t CK DQSDQ skew, DQS to last DQ valid, per group, per access t DQSQ ps DQS read preamble t RPRE t CK DQS read preamble t RPST t CK DQS read preamble setup time t WPRES ps DQS read preamble t WPRE t CK DQS read preamble t WPST t CK Write command to first DQS latching transition t DQSS WL0.25 WL+0.25 WL0.25 WL+0.25 WL0.25 WL+0.25 t CK Tel Tomas, Rancho Santa Margarita, CA USA 7

8 AC TIMING PARAMETERS & SPECIFICATIONS Parameter Symbol DDR2667 (E6) DDR2533 (D5) DDR2400 (CC) Unit Min Max Min Max Min Max Command and Address Timing Address and control input pulse width for each input t IPW t CK Address and control input setup time t IS ps Address and control input hold time t IH ps CAS# to CAS# command delay t CCD t CK ACTIVE to ACTIVE (same bank) command t RC ns ACTIVE bank a to ACTIVE bank b command t RRD ns ACTIVE to READ or WRITE delay t RCD ns Four Bank Activate period t FAW ns ACTIVE to PRECHARGE command t RAS 45 70, , ,000 ns Internal READ to precharge Command delay t RTP ns Write recovery time t WR ns Auto precharge write recovery + precharge time t DAL t WR +t RP t WR +t RP t WR +t RP t CK Internal WRITE to READ Command delay t WTR ns PRECHARGE command period t RP ns PRECHARGE ALL command period t RPA t RP +t CK t RP +t CK t RP +t CK ns LOAD MODE command cycle time t MRD t CK CKE low to CK, CK# uncertainty Self Refresh Refresh to Active or Refresh to Refresh command interval t DELAY t IS +t CK +t IH t IS +t CK +t IH t IS +t CK +t IH ns t RFC ns Average periodic Refresh interval t REFI us Exit Self Refresh to nonread command t XSNR t RFC(MIN) +10 t RFC(MIN) +10 t RFC(MIN) +10 ns Exit Self Refresh to READ t XSRD t CK Exit Self Refresh timing reference t ISXR t IS t IS t IS ps ODT ODT turnon delay t AOND t CK ODT turnon t AON t AC(MIN) 700 Tel Tomas, Rancho Santa Margarita, CA USA 8 t AC(MIN) t AC(MIN) ODT turnoff delay t AOFD t CK ODT turnoff t AOF t AC(MIN) ODT turnon(powerdown mode) ODT turnoff (powerdown mode) t AONPD t AOFPD x t CK x t CK + t AC(MIN) x t CK x t CK + t AC(MIN) x t CK x t CK + ODT to powerdown entry latency t ANPD t CK ODT powerdown exit latency t AXPD t CK Power Down Exit active powerdown to READ command, MR[bit12=0] t XARD t CK Exit active powerdown to READ command, MR[bit12=1] t XARDS 7AL 6AL 6AL t CK Exit precharge powerdown to any nonread command t XP t CK CKE minimum high/low time t CKE t CK ps ps ps ps

9 Package Dimensions FRONT VIEW MAX 4.0 +/ 0.10 (2X) (2X) TYP TYP 2.00 TYP PIN R 1.0 +/ TYP 0.45 TYP PIN / TYP BACK VIEW 2.55 TYP 3.50 TYP PIN TYP 4.20 TYP TYP TYP PIN 2 Note: 1. All dimensions are in millimeters with tolerance +/ 0.15mm unless otherwise specified. 2. The dimensional diagram is for reference only Tel Tomas, Rancho Santa Margarita, CA USA 9

10 Revision History:VN Date Rev. Page Changes 10/15/ All Spec release Tel Tomas, Rancho Santa Margarita, CA USA 10

Product Specifications. General Information. Order Information: VL393T5663F-E7M/E6M/D5M REV: 1.2. Pin Description PART NO.:

Product Specifications. General Information. Order Information: VL393T5663F-E7M/E6M/D5M REV: 1.2. Pin Description PART NO.: General Information 2GB 256Mx72 DDR2 SDRAM ULP ECC REGISTERED DIMM 240PIN Description The VL393T5663F is a 256Mx72 DDR2 SDRAM high density DIMM. This memory module is dual rank, consists of eighteen CMOS