Jin-Hyuk Kim, Je-Huk Ryu, Jun-Dong Cho. Sungkyunkwan Univ.

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1 A High Speed and Low Power VLSI Multiplier Using a Redundant Binary Booth Encoding Jin-Hyuk Kim, Je-Huk Ryu, Jun-Dong Cho School of Electrical and Computer Engineering Sungkyunkwan Univ. jhkim,compro@nature.skku.ac.kr, jdcho@yurim.skku.ac.kr Abstract This paper proposes a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of a redundant binary addition. The redundant binary representation is eective in speed, for it does not require carry propagation. The drawback is hardware increase due to a redundant bit. In this paper, we introduce a novel redundant binary Booth encoding scheme to eliminate the hardware overhead. Experimental results show that our multiplier exhibits the practical interest in high-speed and lower power designs. Keywords Switching-activity, VLSI, High-performance, Low-power-design, Arithmetic. I. Introduction MULTIPLIER plays an important role in various digital systems such as computers, process controllers and signal processors. Previously, various multiplication algorithms have been proposed and practically used, e.g. [10][11][12]. Recently, power dissipation in VLSI multiplication became an important factor to be minimized [3][13], because multiplication is the most power-hungry source in DSP applications. In order to achieve high-speed multiplication, various multiplication algorithms using parallel processors, such as the Wallace tree [4], have been practically used. However, its VLSI chip implementations become complicated, and the area for wires is large [2]. Therefore, a new multiplier is needed to avoid the waste of area and power consumption. In this paper, we improve the multiplication algorithm based on redundant binary representation by [1], utilizing a Booth encoding scheme. This paper is organized as follows. Section 2 introduces and extended carry propagation free adder structure to be used for our redundant binary Booth multiplier. In Section 3, a new Booth encoding scheme used for redundant binary addition is presented. Section 4 presents our multiplication algorithm. Finally, Sections 5 and 6 draw experimental results and conclusion. II. An Extended Carry Propagation Free Adder Structure The multiplier proposed in this paper uses redundant binary representation to utilize carry propagation-free adder[7] for summation of partial products. In carry propagation-free adder, addition can be done in constant time regardless of bit length because of eliminating the carry propagation and adding by means of binary tree. Because the parallel addition of two n-digit redundant binary numbers is executed in a constant time independent of n, TABLE I 2-valued representation of redundant binary code an n-bit multiplication is performed in time proportional to [1]. Consequently, high speed operation is possible, which is impossible in two's complement arithmetic. However, it is dicult to implement in real circuit using redundant binary numbers since area of the circuit can be as some times as that of normal adder circuits. There are two reasons: 1) it must use a triple digit 1; 0; 1 (here, 1 denotes -1) that requires two bits to represent a binary value; 2) each addition requires necessarily 2 steps. In the rst step, it creates intermediate carry and intermediate sum. In the second step, it generates nal sum. Motivated by the facts, in this section, we devise a lowarea and high speed adder for our new multiplier proposed in the following sections. Because each digit is represented by three digits 1; 0; 1, a new 2-valued encoding scheme using so-called S? V code for the new redundant binary code is needed as shown in Table I. For example, is encoded [1,0] and 1 is encoded [0,1]. Consider the rst step which creates intermediate carry and intermediate sum. The block which generates intermediate carry and intermediate sum is composed of three parts, remain adder, body adder and pass adder. Fig. 1 shows the structure of creating intermediate carry and intermediate sum. Remain adder is used for "0" most signi- cat bits in augend. Fig. 2 shows the circuit diagram of the remain adder. Pass adder is used for "0" least signicant bits in addend. Pass adder has the same structure as remain adder. Body adder is used for the middle part of bits which is not "0". Fig. 3 shows the circuit diagram of body adder.

2 Fig. 1. The structure of carry propagation free adder (in the rst step) Fig. 3. The circuit diagram body adder Fig. 2. The circuit diagram of remain adder Consider the second step which generates a nal sum. Because the encoded S-V code represents redundant binary as in Table I, circuit block which generates the nal sum is composed of only OR-gate. All additions at each level in the redundant binary addition tree are performed in parallel that leads to minimize waste of area, increase speed and reduce power consumption of the multiplier we proposed. III. Redundant Binary Booth Encoding Scheme The basic theory for Booth encoding and redundant binary representation was described in [5][6][8]. There are several problems arisen when redundant binary composed of 1; 0; 1 is applied to the Booth encoding algorithm. First, because redundant binary is composed of 1; 0; 1, the number recoded digits are nine such as f 0, +1, +2, +3, +4, -1, -2, -3, -4 g. Such many recoded digits introduce controller overhead Second, the number of partial products are increasing for the recoded digits f-3, +3, -4, +4g. Third, since we need 2 bits to represent the triplevalued redundant binary, area overhead is increased. Motivated by the above facts, in this paper, we propose a new encoding scheme for resolving those problems. Redundant binary encoding represents an integer in various ways and operates without carry propagation [9]. Using these properties, we can apply the redundant binary representation to the Modied Booth algorithm [10] eectively. In this section, we shall explain a new encoding method for multiplying a n-bit multiplicand( = [x 0 x 1 x n?1 ]) and a multiplier( [y 0 y 1 y n?1 ]). A. Our Basic Encoding Method (BEM) The MSB (Most Signicant Bit) of two's complement integer represents sign of the number, but that of redundant binary is not the case. In other words, the dierence between redundant binary ( 1; 0; 1 ) and two's complement ( 0, 1 ) is MSB. To represent binary integer Y, equation 1 is used for two's complement representation, and equation 2 is used for redundant binary representation. n?1 n=2?1 (Y 2i?1 + Y 2i? 2Y 2i+1 ) 2 2i with Y?1 = 0 and Y i 2 f0; 1g (1) Y i 2 i with Y i 2 1; 0; 1 (2) Here, we denote MSB as x n?1 or y n?1 in a n-bit integer. Thus, we need a new encoded binary integer with MSB being zero to apply for Booth algorithm to redundant binary arithmetic. To remove 4 recoded digits f+4, -4, +3, -3g which cause performance overheads, we choose a dierent encoding scheme by considering positive and negative number dierently: 1) if Y is positive number Y n?1 = 0 2) if Y is negative number Y i 2 i ; where Y i 2 f0; 1g (3)

3 TABLE II 4-bit coding using BEM TABLE III 4-bit coding using EEM Y n?1 = 0 Y i 2 i ; where Y i 2 0; 1 (4) Table II shows an example of 4-bit coding using the BEM. Now let us compare the extent of two's complement representation and the proposed redundant binary representation. The extent of two's complement binary is?2 n?1 Y 2 n?1? 1. Whereas, the extent of proposed redundant binary representation is?? 2 n?1? 1 Y 2 n?1?1 which is same as sign magnitude representation. That is, the proposed redundant binary representation is still eective in its extent range. B. Our Extended Encoding Method (EEM) The BEM is still not eective in multiplier designs because of using a triple digit 1; 0; 1 which requires two bits to represent a binary value. Thus, we need a better encoding method. We present an encoding scheme that uses only two digits f0; 1g to enhance area, speed and power dissipation in partial product generation. In BEM, we could get rid of MSB since it is all "0" for every number. We denote "Virtual MSB" as that signies the positive or negative sign of the number. The new encoding method EEM is as follows. 1) if Y is positive number fs n?1 = 0g Y i 2 i ; where Y i 2 f0; 1g (5) 2) if Y is negative number fs n?1 = 1g Fig. 4. An overall multiplication algorithm? Y i 2 i ; where Y i 2 f0; 1g (6) Table III shows a 4-bit coding using the EEM which leads to much eective partial product generation in terms of area, speed and power dissipation in using modied Booth algorithm. Also, we coould remove area overhead by eliminting 1. IV. A Multiplication Based on EEM In this section, we describe the overall multiplication algorithm based on the EEM and Modied Booth encoding algorithm (See Fig. 4).

4 TABLE IV Recoded digit Fig. 5. An example of converting 8 bits two's complementary number into a new code using EEM Step 1 First, we convert input operands(two's complement) into EEM. Consider two's complement binary Y, [y n?1 y 0 ] 2. Here, [y n?1 y 0 ] SD2 denotes redundant binary code using EEM. 1) if Y is positive number (s n?1 = 0) s n?1 = y n?1 [y n?1 y 0 ] SD2 = [y n?1 y 0 ] 2 ; where y i 2 f0; 1g (7) TABLE V Partial product generation 2) if Y is negative number (s n?1 = 1) s n?1 = y n?1 [y y 0 ] SD2 = [y y 0 ] 2 2 ; where y i 2 f0; 1g (8) Fig. 5 shows an example of converting a 8-bit number. Step 2 In this step, we nd recoded digit value for multiplication with multiplier Y. We can nd recoded digit value R i by equations (9) and (10). 1) if Y is positive number (s n?1 = 0) n o 0; 1; 2; ; n 2 ; where Y n?1 = 0; Y?1 = 0 and Y i = f0; 1g (9) R i = Y 2i?1 + Y 2i? 2Y 2i+1 i 2 2) if Y is negative number (s n?1 = 1)? R i = Y 2i?1 + Y 2i? 2Y 2i+1 n o =? (Y 2i?1 + Y 2i? 2Y 2i+1 ) i 2 0; 1; 2; ; n 2 ; where Y n?1 = 0; Y?1 = 0 and Y i = f0; 1g (10) The bits in multiplier Y are partitioned into groups of overlapping 3-bits as in the case of Booth encoder with two's complement, and each groups generates a certain partial product. Here, MSB(Y n?1 ) must be zero. Table IV shows the generated recode digit value. Step 3 By the generated recoded digits in step 2, a set of partial products are generated in this step. Table V shows the partial product generation process by the recoded digit. In Table V, is the multiplicand, and the negative sign of recoded digit signies the opposition of multiplier(y ). In EEM, the opposition operation of multiplier(y ) is done by negating the virtual MSB(s n?1 ) only. That is, s n?1 is changed as 0! 1 or 1! 0. Step 4 In the next step, we add the set of partial products generated in step 3 for producing the nal multiplication result. The proposed multiplier in this paper uses redundant binary arithmetic so as to utilize the carry propagation-free adder. We already presented the carry propagation-free adder in Section 2. Step 5 In this step, we convert a n-digit redundant binary integer into a n-bit two's complement binary. Con-

5 TABLE VI Experimental Result Fig. 6. Converting redundant binary integer into two's complement binary integer using + and? operations Fig. 7. An example of multiplication algorithm? sider a redundant binary integer, [x n?1 x 0 ] SD2 xi 2 1; 0; 1. The conversion process is done by subtracting? from +, where + and? are n-bit unsigned binary integers formed from the positive digits, and the negative digits in, respectively. Fig. 6 shows an example of the conversion process. Finally, Fig. 7 shows an example of multiplication algorithm proposed in this paper. V. Experimental Results To verify the eectiveness of the proposed algorithm, we simulated and compared the following three multipliers using Synopsys TM (1) Modied Booth multiplier with Wallace tree (BW), (2) our multiplier using redundant binary arithmetic (PRB), (3) multiplier in Synopsys TM library (DW02 mult). Table VI shows the experimental results. Experimental constraints are set as follows: Target library is LSI10K; Input Strength is 0.08; Capacitive Load is 1; Operating Conditions is WCCOM(class), and Wire Load is 0505(class). Fig. 9 shows the area result of each multiplier. Using PRB, the area is reduced by 18% compared with the BW, and increased about 31% compared with the DW02 mult on the average. Fig. 10 shows the delay result of each multiplier. Using PRB, the delay is reduced by 59% compared with the DW02 mult, and reduced about 46% compared with the BW on the average, respectively. Fig. 11 shows the power dissipation result of each mul- tiplier. To measure total power dissipation, we tested fty inputs during 500ns. Table VI shows the average power consumption that consists of static and dynamic switching power dissipation. DesignPower TM (Synopsys TM ) is a power analysis tool that analyzes switching power, internal cell power, and leakage power. Power analysis is based on the activity of the nets in our design. When analyzing a gate-level design, DesignPower requires a gate-level netlist and some form of switching activity for the netlist. The switching activity that DesignPower uses most commonly originates from RTL simulation of the design. The power dissipated when the circuit is active. A circuit is active anytime the voltage on a net changes due to some stimulus applied to the circuit. Because voltage on a net can change without necessarily resulting in a logic transition, dynamic power can be dissipated even when a net doesn't change its logic state. The dynamic power of a circuit is composed of Switching power and Internal power as follows. Switching power P c is given by the following equation (11). P C = V 2 dd 2 8 nets(i) (C LOADi T R i ) (11) Here, C Loadi is the total capacitive load of net i, including parasitic capacitance, gate capacitance, and drain capacitance of all the pins connected to net i. DesignPower obtains C Loadi from the wire load model for the net and from the technology library information for the gates connected to the net. T R i is toggle rate of net i, transitions per second. And V dd is supply voltage. Internal power calculation is shown in Fig. 8.

6 Fig. 8. Internal power calculation Fig. 10. Delay Fig. 9. Area P Int = E Z T R Z E Z = f C LOADi ; W eightavg P (TRANS) T R i T rans i i=a;b W eightavg (TRANS) = P T R i i=a;b Fig. 11. Power Dissipation P Int : Total internal power of the cell E Z : Internal energy for output Z as a function of input transitions and output load (dened in the technology library) T R i : Toggle rate of input pin I, transitions per second T rans i : Transition time of input I W eightavg (TRANS) : Weighted average transition time for output Z The total power dissipation using 32-bit inputs is reduced about 18% compared with the BW and reduced about 59% compared with the DW02 mult. Even though the test results of [1][7] was not available for us, it is obvious that our multiplier is faster in speed and lower in power consumption than [1][7], because they does not use Booth encoding. VI. Conclusions In this paper, we proposed a high speed and low power Booth multiplier using redundant binary arithmetic. Our new encoding method was much eective on terms of area, speed and power dissipation than Booth and Wallace tree using two's complement. Dynamic switching power dissipation and delay were reduced signicantly by employing carry propagation-free adder. We expect more gains on large multipliers for 32-bit and above. Therefore, the multiplier proposed in this paper can be eectively used for Digital Signal Processing applications. References [1] N. Takagi, A high-speed multiplier with a regular cellular array structure using redundant binary representation, Yajima Lab., Dep. Inform. Sci., Kyoto Univ., Kyoto, Japan, Res. Rep. R82-14(in Japanese), Ju ne [2] J.E. Vuillemin, A very fast multiplication algorithm for VLSI implementation, Integration, VLSI J., vol. 1, no. 1, pp , Apr [3] Brian S. Cherkauer, Eby G. Friedman, A Hybrid Radix-4/Radix- 8 Low Power Signed Multiplier Architecture, IEEE Transactions on Circuits and Systems, Vol. 44, No. 8, August [4] A. Bellaouar, M. I. Elmasry, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academic Pub., [5] Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Design of Testable Multipliers for Fixed-Width Data Paths, IEEE Transactions on Computers, Vol. 46, No. 7, July [6] R. I. Hartley, K. K. Parhi, Digit-Serial Computation, Kluwer Academic Pub.,1995.

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