Design of Parallel MAC Based On Radix-4 & Radix-8 Modified Booth Algorithm

Transcription

1 International Journal of Research in Computer and Communication technology, IJRCCT, ISSN , Vol 1, Issue 7, December Design of Parallel MAC Based On Radix-4 & Radix-8 Modified Booth Algorithm 1 S.ANITHA, 2 M.VIDYA, 3 D. MAHESH VARMA 1 PG Student, Kakinada institute of engineering & technology, East Godavari, Andhra Pradesh, India 2 Assistant Professor, Kakinada institute of engineering & technology, East Godavari, Andhra Pradesh, India 3 Assistant Professor, Kakinada institute of engineering & technology, East Godavari, Andhra Pradesh, India Abstract This paper focused on a combined process of multiplication and accumulation based on radix-4 & radix-8 booth encodings. In this Paper, we investigate the method of implementing the Parallel MAC with the smallest possible delay. Parallel MAC is frequently used in digital signal processing and video/graphics applications. A new architecture of multiplier - and accumulator (MAC) for highspeed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The MAC provides high speed multiplication and multiplication with accumulative addition. Enhancing the speed of operation of the parallel MAC is a major design issue. modified Booth s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 m, and 90 nm standard CMOS library. Keywords Radix-4 and Radix-8 based Booth multiplier; carry save adder (CSA) tree; computer arithmetic; digital signal processing (DSP); multiplier and- accumulator (MAC); Adders. 1. INTRODUCTION In this paper, we study the various parallel MAC architectures and then implement a design of parallel MAC based on some booth encodings such as radix-4 & radix-8 booth encoder and some final adders such as CLA, Kogge stone adder and then compare their performance characteristics. A Digital multiplier is the fundamental component in general purpose microprocessor and in DSP [1], [2]. Compared with many other arithmetic operations multiplication is time consuming and power hungry. Thus enhancing the performance and reducing the power dissipation are the most important design challenges for all applications in which multiplier unit dominate the system performance and power dissipation. The one most effective way to increase the speed of a multiplier is to reduce the number of the partial products. Although the number of partial products can be reduced with a higher radix booth encoder, but the number of hard multiples that are expensive to generate also increases simultaneously. To increase the speed and performance, many parallel MAC architectures have been proposed. Parallelism in obtaining partial products is the most common technique used in the above implemented architecture. There are two common approaches that make use of parallelism to enhance the multiplication performance. The first one is reducing the number of partial product rows and second one is the carry-save-tree technique to reduce multiple partial product rows as two "carry-save" redundant forms. An architecture was proposed in [4] to provide the tact to merge the final adder block to the accumulator register in the MAC operator to provide the possibility of using two separate N/2-bit adders instead of one N-bit adder to accumulate the N bit MAC chiefeditor@ijrcct.org Page 446

2 results. The most advanced types of MAC has been proposed by Elguibaly [8] in which accumulation has been combined with the carry save adder (CSA) tree that compresses partial products and thus reduces the critical path. Later on a new architecture for a high-speed MAC is proposed by Seo and Kim [9]. The difference between the two is that the latest one carries out the accumulation by feeding back the final CSA output rather than the final adder results. The rest of the paper is organized as follows. In section second, an introduction to the general MAC is given along with basic MAC algorithms. In section third, entire process of parallel MAC based on radix-4 and radix-8booth encodings [7] is explained. Section four shows implementation result and the characteristics of parallel MAC based on both of the booth encodings. Finally, the conclusion will be given in section five in which we provide summary of our proposed approach and discuss scope of future extensions. II. GENERAL MAC STRUCTURE In this section, we discuss basic MAC operation. Basically, multiplier operation can be divided into three operational steps. The first one is booth encoding to generate the partial products. The second one is adder array or partial product compression and the last one is final addition in which final multiplication result is produced If the multiplication process is extended to accumulate the multiplied result, then MAC consists of four steps. General hardware architecture for MAC is shown in Figure 1. It executes the multiplication operation by multiplying input multiplier X and input multiplicand Y. After that current multiplication result is added to the previous multiplication result Z as accumulation step. A multiplier can be divided into three operational steps. The first is radix-2 Booth encoding in which a partial product is generated from the multiplicand X and the multiplier Y. The second is adder array or partial product compression to add all partial products. The last is the final addition in which the process to accumulate the multiplied results is included. The general hardware architecture of this MAC is shown in Fig.. It executes the multiplication operation by multiplying the input multiplier X and the multiplicand Y. This is added to the previous multiplication result Z as the accumulation step. The N-bit 2 s complement binary number can be expressed as..(1) If (1) is expressed in base-4 type redundant sign digit form in order to apply the radix-2 Booth s algorithm...(2) (3) If (2) is used, multiplication can be expressed as (4) If these equations are used, the afore-mentioned multiplication accumulation results can be expressed as.(5) Each of the two terms on the right-hand side of (5) is calculated independently and the final result is produced by adding the two results. The MAC architecture implemented by (5) is called the standard design [6].If -bit data are multiplied, the number of the generated partial products is proportional to N. In order to add them serially, the execution time is also proportional to N. The architecture of a multiplier, which is the fastest, uses radix-2 Booth encoding that generates partial products. If radix-2 Booth encoding is used, the number of partial products, is reduced to half, resulting in the decrease in Addition of Partial Products step. In addition, the signed multiplication based on 2 s complement numbers is also possible. Due to these reasons, most current used multipliers adopt the Booth encoding. A. Multiplier and Accumulator Unit MAC is composed of an adder, multiplier and an accumulator. Usually adders implemented are Carry- Select or Carry-Save adders, as speed is of utmost importance in DSP (Chandrakasan, Sheng, & Brodersen, 1992 and Weste & Harris, 3rd Ed). One implementation of the multiplier could be as a parallel array multiplier. The inputs for the MAC are to be fetched from memory location and fed to chiefeditor@ijrcct.org Page 447

3 the multiplier block of the MAC, which will perform multiplication and give the result to adder which will accumulate the result and then will store the result into a memory location. This entire process is to be achieved in a single clock cycle (Weste & Harris, 3rd Ed). The architecture of the MAC unit which had been designed in this work consists of one 16 bit register, one 16-bit Modified Booth Multiplier, 32-bit accumulator. To multiply the values of A and B, Modified Booth multiplier is used instead of conventional multiplier because Modified Booth multiplier can increase the MAC unit design speed and reduce multiplication complexity. SPST Adder is used for the addition of partial products and a register is used for accumulation.. The operation of the designed MAC unit is as in Equation 2.1. The product of Ai X Bi is always fed back into the 32-bit accumulator and then added again with the next product Ai x Bi. This MAC unit is capable of multiplying and adding with previous product consecutively up to as many as times. Fig 1: Simple Multiplier and Accumulator Architecture III.DESIGN OF MAC In the majority of digital signal processing (DSP) applications the critical operations usually involve many multiplications and/or accumulations. For real-time signal processing, a high speed and high throughput Multiplier- Accumulator (MAC) is always a ke y to achieve a high performance digital signal processing system. In the last few years, the main consideration of MAC design is to enhance its speed. This is because; speed and throughput rate is always the concern of digital signal processing system. But for the epoch of personal communication, low power design also becomes another main design consideration. This is because; battery energy available for these portable products limits the power consumption of the system. Therefore, the main motivation of this work is to investigate various Pipelined multiplier/accumulator architectures and circuit design techniques which are suitable for implementing high throughput signal processing algorithms and at the same time achieve low power consumption. A conventional MAC unit consists of (fast multiplier) multiplier and an accumulator that contains the sum of the previous consecutive products. The function of the MAC unit is given by the following equation=σai (2.1)The main goal of a DSP processor design is to enhance the speed of the MAC unit, and at the same time limit the power consumption. In a pipelined MAC circuit, the delay of pipeline stage is the delay of a 1-bit full adder. Estimating this delay will assist in identifying the overall delay of the pipelined MAC. In this work, 1-bit full adder is designed. Area, power and delay are calculated for the full adder, based on which the pipelined MAC unit is designed for low power. A. High-Speed Booth Encoded Parallel Multiplier Design: Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. In the past multiplication was generally implemented via a sequence of addition, subtraction, and shift operations. Multiplication can be considered as a series of repeated additions. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. In most computers, the operand usually contains the same number of bits. When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one collects and adds them. chiefeditor@ijrcct.org Page 448

4 Fig 2. Hardware architecture of the proposed MAC. The basic multiplication principle is two fold i.e. evaluation of partial products and accumulation of the shifted partial products. It is performed by the successive additions of the columns of the shifted partial product matrix. The multiplier is successfully shifted and gates the appropriate bit of the multiplicand. The delayed, gated instance of the multiplicand must all be in the same column of the shifted partial product matrix. They are then added to form the product bit for the particular form. Multiplication is therefore a multi operand operation. To extend the multiplication to both signed and unsigned. will not be degraded. A 2-bit CLA is used to add the lower bits in the CSA. In addition, to increase the output rate when pipelining is applied, the sums and carry s from the CSA are accumulated instead of the outputs from the final adder in the manner that the sum and carry from the CSA in the previous cycle are inputted to CSA. Due to this feedback of both sum and carry, the number of inputs to CSA increases, compared to the standard design and. In order to efficiently solve the increase in the amount of data, CSA architecture is modified to treat the sign bit. Equation Derivation: The aforementioned concept is applied to to express the proposed MAC arithmetic. Then, the multiplication would be transferred to a hardware architecture that complies with the proposed concept, in which the feedback value for accumulation will be modified and expanded for the new MAC. First, if the multiplication in (4) is decomposed and rearranged, it becomes If this is divided into the first partial product, sum of the middle partial products, and the final partial product, it can be expressed as. The reason for separating the partial product addition as is that three types of data are fed back for accumulation, which are the sum, the carry, and the preadded results of the sum and carry from lower bits. Fig 3. Basic arithmetic steps of multiplication and accumulation. 3.2 Derivation of MAC Arithmetic: Basic Concept: If an operation to multiply two bit numbers and accumulates into a 2-bit number is considered, the critical path is determined by the 2-bit accumulation operation. If a pipeline scheme is applied for each step in the standard design of Fig 1, the delay of the last accumulator must be reduced in order to improve the performance of the MAC. The overall performance of the proposed MAC is improved by eliminating the accumulator itself by combining it with the CSA function. If the accumulator has been eliminated, the critical path is then determined by the final adder in the multiplier. The basic method to improve the performance of the final adder is to decrease the number of input bits. In order to reduce this number of input bits, the multiple partial products are compressed into a sum and a carry by CSA. The number of bits of sums and carries to be transferred to the final adder is reduced by adding the lower bits of sums and carries in advance within the range in which the overall performance Now, the proposed concept is applied to in (5). If is first divided into upper and lower bits and rearranged, (8) will be derived. The first term of the right-hand side in (8) corresponds to the upper bits. It is the value that is fed back as the sum and the carry. The second term corresponds to the lower bits and is the value that is fed back as the addition result for the sum and carry The second term can be separated further into the carry term and sum term as Thus, chiefeditor@ijrcct.org Page 449

5 number of partial products by half, by using the technique of radix-4 Booth recoding. The basic idea is that, instead of shifting and adding for every column of the multiplier term and multiplying by 1 or 0, we only take every second column, and multiply by ±1, ±2, or 0, to obtain the same results. The advantage of this method is the halving of the number of partial products. To Booth recode the multiplier term, we consider the bits in blocks of three, such that each block overlaps the previous block by one bit. Grouping starts from the LSB, and the first block only uses two bits of the multiplier. Figure 3 shows the grouping of bits from the multiplier term for use in modified booth encoding. Fig.6 Grouping of bits from the multiplier term Fig 4. Proposed arithmetic operation of multiplication and accumulation. Each block is decoded to generate the correct partial product. The encoding of the multiplier Y, using the modified booth algorithm, generates the following five signed digits, -2, -1, 0, +1, +2. Each encoded digit in the multiplier performs a certain operation on the multiplicand, X, as illustrated in Table 1 Table 1. Coding Table Fig 5. Hardware architecture of general MAC. 3.3 Modified Booth Encoder: In order to achieve high-speed multiplication, multiplication algorithms using parallel counters, such as the modified Booth algorithm has been proposed, and some multipliers based on the algorithms have been implemented for practical use. This type of multiplier operates much faster than an array multiplier for longer operands because its computation time is proportional to the logarithm of the word length of operands. Booth multiplication is a technique that allows for smaller, faster multiplication circuits, by recoding the numbers that are multiplied. It is possible to reduce the For the partial product generation, we adopt Radix-4 Modified Booth algorithm to reduce the number of partial products for roughly one half. For multiplication of 2 s complement numbers, the two-bit encoding using this algorithm scans a triplet of bits. When the multiplier B is divided into groups of two bits, the algorithm is applied to this group of divided bits. Figure 4, shows a computing example of Booth multiplying two numbers 2AC9 and 006A. The shadow denotes that the numbers in this part of Booth multiplication are all zero so that this part of the computations can be neglected. Saving those computations can significantly reduce the power consumption caused by the transient signals. chiefeditor@ijrcct.org Page 450

6 Fig.9 Booth partial products Generation Fig.7 Illustration of multiplication using modified Booth encoding The PP generator generates five candidates of the partial products, i.e., {-2A,-A, 0, A, 2A}. These are then selected according to the Booth encoding results of the operand B. When the operand besides the Booth encoded one has a small absolute value, there are opportunities to reduce the spurious power dissipated in the compression tree. The multiplication second step reduces the partial products from the preceding step into two numbers while preserving the weighted sum. The sough after product P is the sum of those two numbers. The two numbers will be added during the third step The "Wallace trees" synthesis follows the Dadda's algorithm, which assures of the minimum counter number. If on top of that we impose to reduce as late as (or as soon as) possible then the solution is unique. The two binary number to be added during the third step may also be seen a one number in CSA notation (2 bits per digit). 3.4 Partial product generator: Fig.8 Booth partial product selector logic Fig.10 Booth single partial product selector logic The multiplication first step generates from A and X a set of bits whose weights sum is the product P. For unsigned multiplication, P most significant bit weight is positive, while in 2's complement it is negative. The partial product is generated by doing AND between a and b which are a 4 bit vectors as shown in fig. If we take, four bit multiplier and 4-bit multiplicand we get sixteen partial products in which the first partial product is stored in q. Similarly, the second, third and fourth partial products are stored in 4-bit vector n, x, y. Table2. Truth table for MBE Scheme chiefeditor@ijrcct.org Page 451

7 IV. PROPOSED ARCHITECTURE The architecture of the hybrid-type CSA that complies with the operation of the proposed MAC is shown in Fig. 5, which performs 8-bit operation. In Fig Si is to simplify the sign expansion and Ni is to compensate 1 s complement number into 2 s complement number. S[i] and C[i] correspond to the ith bit of the feedback sum and carry. Z[i] is the ith bit of the sum of the lower bits for each partial product that were added in advance and Z [i] is the previous result. In addition, Pj[i] corresponds to the ith bit of the jth partial product. Since the multiplier is for 8 bits, totally four partial products are generated from the Booth encoder. This CSA requires at least four rows of FAs for the four partial products. Thus, totally five FA rows are necessary since one more level of rows are needed for accumulation. For an -bit MAC operation, the level of CSA is (n/2+1). The white square in Fig represents an FA and the gray square is a half adder (HA). The rectangular symbol with five inputs is a 2-bit CLA with a carry input. and the others is the type of values that is fed back for accumulation. Ours has the smallest number of inputs to the final adder. V. EXPERIMENTAL RESULT: Simulation Results of MAC: Synthesis Result: The developed MAC design is simulated and verified their functionality. Once the functional verification is done, the RTL model is taken to the synthesis process using the Xilinx ISE tool. In synthesis process, the RTL model will be converted to the gate level netlist mapped to a specific technology library. This MAC design can be synthesized on the family of Spartan 3E. Here in this Spartan 3E family, many different devices were available in the Xilinx ISE tool. In order to synthesis this design the device named as XC3S500E has been chosen and the package as FG320 with the device speed such as -4. The design of MAC is synthesized and its results were analyzed as follows. Device utilization summary: Fig. 11 Architecture of the proposed CSA tree. The critical path in this CSA is determined by the 2-bit CLA. It is also possible to use FAs to implement the CSA without CLA. However, if the lower bits of the previously generated partial product are not processed in advance by the CLAs, the number of bits for the final adder will increase. When the entire multiplier or MAC is considered, it degrades the performance. In Table I, the characteristics of the proposed CSA architecture have been summarized and briefly compared with other architectures. For the number system, the proposed CSA uses 1 scomplement, but ours uses a modified CSA array without sign extension. The biggest difference between ours chiefeditor@ijrcct.org Page 452

8 This device utilization includes the following. Logic Utilization Logic Distribution Total Gate count for the Design The device utilization summery is shown above in which its gives the details of number of devices used from the available devices and also represented in %. Hence as the result of the synthesis process, the device utilization in the used device and package is shown above. Summary: The developed MAC design is modelled and is simulated using the Modelsim tool. The simulation results are discussed by considering different cases. The RTL model is synthesized using the Xilinx tool in Spartan 3E and their synthesis results were discussed with the help of generated reports Timing Summary: Speed Grade: -4 Minimum period: ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 6.892ns Maximum output required time after clock: 4.394ns Maximum combinational path delay: No path found In timing summery, details regarding time period and frequency is shown are approximate while synthesize. After place and routing is over, we get the exact timing summery. Hence the maximum operating frequency of this synthesized design is given as MHz and the minimum period as ns. Here, OFFSET IN is the minimum input arrival time before clock and OFFSET OUT is maximum output required time after clock. Fig.13 Internal RTL schematic The bit parallel MAC based on both the booth encodings (i.e. Radix-4 booth encoding and Radix-8 booth encoding) and some final adders (such as CLA adder and Radix-5 Kogge stone adder) is designed in Verilog and the functionalities of the algorithms are verified by XILINX ISE 8.2i using Virtex 2p with XC2VP7 family with FF896 package & -7 RTL Schematic The RTL (Register Transfer Logic) can be viewed as black box after synthesize of design is made. It shows the inputs and outputs of the system. By double-clicking on the diagram we can see gates, flip-flops and MUX. Fig. 14. Simulation result of Pipelined 16-bit MAC based on radix-4 modified booth encoder Figure.12 Schematic with Basic Inputs and Output Simulation result for the 16-bit parallel MAC based on radix-4 booth encoder and using Radix-5 Koggestone as a final adder is shown in Figure 6 respectively and performance characteristics in terms of speed andarea are chiefeditor@ijrcct.org Page 453

9 shown in table I. It could be seen from table that the parallel MAC based on Radix-5 Kogge stone adderis having more area as compared to others but having less delay. Higher would be the no. of slices, higher wouldbe area. Thus, MAC based on Radix-5 Kogge stone adder shows higher performance than others but at the cost of area. VI. CONCLUSION A multiplier-accumulator (MAC) is presented in this work. A Radix 4Modified Booth multiplier circuit is used for MAC architecture. Compared to other circuits, the Booth multiplier has the highest operational speed and less hardware count. The basic building blocks for the MAC unit are identified and each of the blocks is analyzed for its performance. Power and delay is calculated for the blocks. 1-bit MAC unit is designed with enable to reduce the total power consumption based on block enable technique. Using this block, the N-bit MAC unit is constructed and the total power consumption is calculated for the MAC unit. The power reduction techniques adopted in this work. The MAC unit designed in this work can be used in filter realizations for High speed DSP applications. Table 3 summarizes the results obtained. REFERENCES [1] Young-Ho Seo and Dong-Wook Kim, A New VLSI Architevture of parallel Multiplier-Accumulator based on Radix-2 Modified Booth Algorithm. IEEE Trans.vol.18.No.2 FEB [2] Information Technology-Coding of Moving Picture and AssociatedAutio, MPEG-2 Draft International Standard, ISO/IEC , 2, 3,1994. [3] JPEG 2000 Part I Fina1119l Draft, ISO/IEC JTC1/SC29 WG1. [4] O. L. MacSorley, High speed arithmetic in binary computers, Proc.IRE, vol. 49, pp , Jan [5] S. Waser and M. J. Flynn, Introduction to Arithmetic for Digital SystemsDesigners. New York: Holt, Rinehart and Winston, [6] A. R. Omondi, Computer Arithmetic Systems. Englewood Cliffs, NJ:Prentice-Hall, [7] A. D. Booth, A signed binary multiplication technique, Quart. J Math., vol. IV, pp , [8] C. S. Wallace, A suggestion for a fast multiplier, IEEE Trans. ElectronComput., vol. EC-13, no. 1, pp , Feb [9] A. R. Cooper, Parallel architecture modified Booth multiplier, Proc.Inst. Electr. Eng. G, vol. 135, pp , [10] N. R. Shanbag and P. Juneja, Parallel implementation of a 4 4- bitmultiplier using modified Booth s algorithm, IEEE J. Solid-State Circuits,vol. 23, no. 4, pp , Aug [11] G. Goto, T. Sato, M. Nakajima, and T. Sukemura, A regularstructured tree multiplier, IEEE J. Solid-State Circuits, vol. 27, no. 9,pp , Sep [12] J. Fadavi-Ardekani, M N Booth encoded multiplier generator usingoptimizedwallace trees, IEEE Trans. Very Large Scale Integr. (VLSI)Syst., vol. 1, no. 2, pp , Jun [13] N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K.Sasaki, and Y. Nakagome, A 4.4 ns CMOS multiplier usingpass-transistor multiplexer, IEEE J. Solid-State Circuits, vol. 30, no.3, pp , Mar [14] A. Tawfik, F. Elguibaly, and P. Agathoklis, New realization andimplementation of fixed-point IIR digital filters, J. Circuits, Syst.,Comput., vol. 7, no. 3, pp , Table 3. Comparison results of 16-bit parallel MAC [15] A. Tawfik, F. Elguibaly, M. N. Fahmi, E. Abdel-Raheem, and P.Agathoklis, High-speed area-efficient inner-product processor, Can.J. Electr. Comput. Eng., vol. 19, pp , [16] F. Elguibaly and A. Rayhan, Overflow handling in inner-product processors, in Proc. IEEE Pacific Rim Conf. Commun., Comput., SignalProcess., Aug. 1997, pp [17] F. Elguibaly, A fast parallel multiplier accumulator using the modifiedbooth algorithm, IEEE Trans. Circuits Syst., vol. 27, no. 9, pp , Sep chiefeditor@ijrcct.org Page 454