AUTOSWITCHING POWER MULTIPLEXER

Transcription

1 AUTOSWITCHING POWER MULTIPLEXER TPS FEATURES Two-Input, One-Output Power Multiplexer With Low r DS(on) Switches: 8 mω Typ () 0 mω Typ (TPS) Reverse and Cross-Conduction Blocking Wide Operating Voltage Range:.8 V to. V Low Standby Current: 0. µa Typical Low Operating Current: µa Typical Adjustable Current Limit Controlled Output Voltage Transition Times, Limits Inrush Current and Minimizes Output Voltage Hold-Up Capacitance CMOS and TTL Compatible Control Inputs Manual and Auto-Switching Operating Modes Thermal Shutdown Available in a TSSOP-8 Package APPLICATIONS PCs PDAs Digital Cameras Modems Cell phones Digital Radios MP3 Players STAT D0 D ILIM 3 PW PACKAGE (TOP VIEW) IN OUT IN GND DESCRIPTION The TPSx family of power multiplexers enables seamless transition between two power supplies, such as a battery and a wall adapter, each operating at.8-. V and delivering up to A. The TPSx family includes extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power multiplexer applications. TYPICAL APPLICATION IN:.8 -. V Switch Status PW 0. µf R 3 STAT D0 D ILIM IN OUT IN GND C L R L R ILIM IN:.8 -. V 0. µf Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 00 00, Texas Instruments Incorporated

2 TPS These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS FEATURE TPS0 TPS TPS TPS3 TPS Current limit adjustment range A A A A A A Switching modes Manual Yes Yes No No Yes Yes Automatic Yes Yes Yes Yes Yes Yes Switch status output No No Yes Yes Yes Yes Package TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 TSSOP-8 PACKAGE DISSIPATION RATINGS ORDERING INFORMATION T A PACKAGE ORDERING NUMBER () MARKINGS -0 C to 8 C TSSOP-8 (PW) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted () TPSPW PW () The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPSPWR) to indicate tape and reel. PACKAGE DERATING FACTOR T A C T A = 70 C T A = 8 C ABOVE T A = C POWER RATING POWER RATING POWER RATING TSSOP-8 (PW) 3.87 mw/ C mw.76 mw.73 mw TPS, V I Input voltage range IN, IN, D0, D, ILIM () -0.3 V to 6 V V O Output voltage range () OUT, STAT -0.3 V to 6 V I O Output sink current STAT ma I O Continuous output current TPS Continuous total power dissipation 0.9 A. A See Dissipation Rating Table T J Operating virtual junction temperature range -0 C to C T stg Storage temperature range -6 C to 0 C Lead temperature soldering,6 mm (/6 inch) from case for 0 seconds 60 C () Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. () All voltages are with respect to GND.

3 RECOMMENDED OPERATING CONDITIONS TPS MIN MAX UNIT V I(IN).8 V.. V I Input voltage at IN V V I(IN) <.8 V.8. V I(IN).8 V.. V I Input voltage at IN V V I(IN) <.8 V.8. V I Input voltage at D0, D 0. V TPS I O(OUT) Current limit adjustment range A T J Operating virtual junction temperature -0 C ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN MAX UNIT Human body model kv CDM 00 V ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, V I(IN) = V I(IN) =. V, R (ILIM) = 00 Ω (unless otherwise noted) POWER SWITCH r DS(on) () TPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX V I(IN) = V I(IN) =.0 V T J = C, I L = 00 ma V I(IN) = V I(IN) = 3.3 V mω Drain-source on-state V I(IN) = V I(IN) =.8 V resistance (INx-OUT) V I(IN) = V I(IN) =.0 V 0 0 T J = C, I L = 00 ma V I(IN) = V I(IN) = 3.3 V 0 0 mω V I(IN) = V I(IN) =.8 V 0 0 () The TPSx can switch a voltage as low as. V as long as there is a minimum of.8 V at one of the input power pins. In this specific case, the lower supply voltge has no effect on the IN and IN switch on-resistances. 3

4 TPS ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) LOGIC INPUTS (D0 AND D) PARAMETER TEST CONDITIONS UNIT MIN TYP MAX V IH High-level input voltage V V IL Low-level input voltage 0.7 V D0 or D = High, sink current Input current at D0 or D µa D0 or D = Low, source current 0.. SUPPLY AND LEAKAGE CURRENTS D = High, D0 = Low (IN active), V I(IN) =. V, V I(IN) = 3.3 V, I O(OUT) = 0 A 90 D = High, D0 = Low (IN active), V I(IN) = 3.3 V, V I(IN) =. V, I O(OUT) = 0 A Supply current from IN (operating) µa D0 = D = Low (IN active), V I(IN) =. V, 7 V I(IN) = 3.3 V, I O(OUT) = 0 A D0 = D = Low (IN active), V I(IN) = 3.3 V, V I(IN) =. V, I O(OUT) = 0 A D = High, D0 = Low (IN active), V I(IN) =. V, V I(IN) = 3.3 V, I O(OUT) = 0 A D = High, D0 = Low (IN active), V I(IN) = 3.3 V, 7 V I(IN) =. V, I O(OUT) = 0 A Supply current from IN (operating) µa D0 = D = Low (IN active), V I(IN) =. V, V I(IN) = 3.3 V, I O(OUT) = 0 A D0 = D = Low (IN active), V I(IN) = 3.3 V, V I(IN) =. V, I O(OUT) = 0 A 90 D0 = D = High (inactive), V I(IN) =. V, 0. V I(IN) = 3.3 V, I O(OUT) = 0 A Quiescent current from IN (STANDBY) µa D0 = D = High (inactive), V I(IN) = 3.3 V, V I(IN) =. V, I O(OUT) = 0 A D0 = D = High (inactive), V I(IN) =. V, V I(IN) = 3.3 V, I O(OUT) = 0 A Quiescent current from IN (STANDBY) µa D0 = D = High (inactive), V I(IN) = 3.3 V, 0. V I(IN) =. V, I O(OUT) = 0 A Forward leakage current from IN D0 = D = High (inactive), V I(IN) =. V, IN open, (measured from OUT to GND) V O(OUT) = 0 V (shorted), T J = C Forward leakage current from IN D0 = D= High (inactive), V I(IN) =. V, IN open, (measured from OUT to GND) V O(OUT) = 0 V (shorted), T J = C Reverse leakage current to INx D0 = D = High (inactive), V I(INx) = 0 V, (measured from INx to GND) V O(OUT) =. V, T J = C CURRENT LIMIT CIRCUIT 0. µa 0. µa 0.3 µa R (ILIM) = 00 Ω TPS Current limit R (ILIM) = 700 Ω accuracy R (ILIM) = 00 Ω R (ILIM) = 700 Ω Time for short-circuit output current to settle within t d Current limit settling time () ms 0% of its steady state value. Input current at ILIM V I(ILIM) = 0 V, I O(OUT) = 0 A - 0 µa () Not tested in production. A

5 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) UNDERVOLTAGE LOCKOUT IN and IN UVLO TPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX Falling edge.. Rising edge.30.3 IN and IN UVLO hysteresis () mv Internal V DD UVLO (the higher of IN and IN) Falling edge.3 Rising edge.8.8 Internal V DD UVLO hysteresis () mv UVLO deglitch for IN, IN () Falling edge 0 µs REVERSE CONDUCTION BLOCKING D0 = D = high, V I(INx) = 3.3 V. Connect OUT to a V O(I_block) Minimum output-to-input voltage V supply through a series -kω resistor. Let difference to block switching D0 = low. Slowly decrease the supply voltage until mv OUT connects to IN. THERMAL SHUTDOWN Thermal shutdown threshold () TPSx is in current limit. 3 Recovery from thermal shutdown () TPSx is in current limit. C Hysteresis () 0 IN-IN COMPARATORS Hysteresis of IN-IN comparator V Deglitch of IN-IN comparator, (both ) () µs STAT OUTPUT Leakage current V O(STAT) =. V 0.0 µa Saturation voltage I I(STAT) = ma, IN switch is on V Deglitch time (falling edge only) 0 µs () Not tested in production. V V

6 TPS SWITCHING CHARACTERISTICS over recommended operating junction temperature range, V I(IN) = V I(IN) =. V, R (ILIM) = 00 Ω (unless otherwise noted) POWER SWITCH TPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX T J = C, C L = µf, Output rise time from an t r V I(IN) = V I(IN) = V I L = 00 ma, ms enable () See Figure (a) T J = C, C L = µf, Output fall time from a t f V I(IN) = V I(IN) = V I L = 00 ma, ms disable () See Figure (a) IN to IN transition, T J = C, V I(IN) = 3.3 V, C L = 0 µf, V I(IN) = V I L = 00 ma [Measure transition time as t t Transition time () µs IN to IN transition, 0-90% rise time or V from 3. V to.8 V I(IN) = V, V on V O(OUT) ], I(IN) = 3.3 V See Figure (b) T J = C, V I(IN) = V I(IN) = V, Turnon propagation delay C L = 0 µf, t PLH Measured from enable 0. ms from enable () I L = 00 ma, to 0% of V O(OUT) SeeFigure (a) T J = C, V I(IN) = V I(IN) = V, Turnoff propagation delay C L = 0 µf, t PHL Measured from disable 3 ms from a disable () I L = 00 ma, to 90% of V O(OUT) See Figure (a) t PLH Logic to Logic 0 transition on D, T J = C, V I(IN) =. V, Switch-over rising C L = 0 µf, V I(IN) = V, propagation delay () I L = 00 ma, V I(D0) = 0 V, See Figure (c) Measured from D to ms t PHL 0% of V O(OUT) Logic 0 to Logic transition on D, T J = C, V I(IN) =. V, Switch-over falling C L = 0 µf, V I(IN) = V, propagation delay () I L = 00 ma, V I(D0) = 0 V, Measured See Figure (c) from D to 90% of ms V O(OUT) () Not tested in production. TRUTH TABLE D D0 V I(IN) > V I(IN) STAT OUT () 0 0 X Hi-Z IN 0 No 0 IN 0 Yes Hi-Z IN 0 X 0 IN X 0 Hi-Z () The under-voltage lockout circuit causes the output OUT to go Hi-Z if the selected power supply does not exceed the IN/IN UVLO, or if neither of the supplies exceeds the internal V DD UVLO. 6

7 TERMINAL NAME NO. I/O DESCRIPTION Terminal Functions TPS D0 I TTL and CMOS compatible input pins. Each pin has a -µa pullup resistor. The truth table shown above illustrates D 3 I the functionality of D0 and D. GND I Ground IN 8 I Primary power switch input. The IN switch can be enabled only if the IN supply is above the UVLO threshold and at least one supply exceeds the internal V DD UVLO. IN 6 I Secondary power switch input. The IN switch can be enabled only if the IN supply is above the UVLO threshold and at least one supply exceeds the internal V DD UVLO. ILIM I A resistor R (ILIM) from ILIM to GND sets the current limit I L to 0/R (ILIM) and 00/R (ILIM) for the TPS and, respectively. OUT 7 O Power switch output STAT O STAT is an open-drain output that is Hi-Z if the IN switch is ON. STAT pulls low if the IN switch is ON or if OUT is Hi-Z (i.e., EN is equal to logic 0). FUNCTIONAL BLOCK DIAGRAM µa µa V f = 0 V V f = 0 V Internal V DD IN 8 Q I O(OUT) 7 OUT IN 6 Q Charge Pump k* I O(OUT) V DD ULVO _ TPS: k = 0.% : k = 0.% ILIM IN ULVO + 0. V IN ULVO Cross-Conduction Detector + _ 0.6 V + + _ EN EN D0 D GND 3 Q is ON UVLO (V DD ) UVLO (IN) UVLO (IN) D0 D Control Logic Q is ON 00 mv V O(OUT) > V + I(INx) + _ Thermal Sense + _ EN IN IN STAT Q is ON 7

8 TPS PARAMETER MEASUREMENT INFORMATION V O(OUT) 0 V 0% 90% 90% 0% t r t f DO-D Switch Off t PLH Switch Enabled t PHL Switch Off (a) V O(OUT) 3.3 V 3. V.8 V V t t DO-D Switch # Enabled Switch # Enabled (b) V O(OUT). V.8 V V.6 V DO-D Switch # Enabled t PLH Switch # Enabled (c) t PHL Switch # Enabled Figure. Propagation Delays and Transition Timing Waveforms 8

9 TPS OUTPUT SWITCHOVER RESPONSE TYPICAL CHARACTERISTICS V I(DO) V/Div V I(D) V/Div V f = 8 Hz 78% Duty Cycle NC 00 Ω 3 PW STAT IN D0 OUT D IN ILIM GND µf 0. µf 0 Ω 3.3 V V O(OUT) V/Div 0. µf t - Time - ms/div Output Switchover Response Test Circuit Figure. OUTPUT TURNON RESPONSE V I(DO) V/Div V I(D) V/Div V f = 8 Hz 78% Duty Cycle NC 00 Ω 3 PW STAT IN D0 OUT D IN ILIM GND µf 0. µf 0 Ω 3.3 V V O(OUT) V/Div 0. µf Output Turnon Response Test Circuit t Time ms/div Figure 3. 9

10 TPS TYPICAL CHARACTERISTICS (continued) OUTPUT SWITCHOVER VOLTAGE DROOP 0 µf V I(DO) V/Div V I(D) V/Div C L = µf V f = 80 Hz 90% Duty Cycle NC 00 Ω 3 PW STAT IN D0 OUT D IN ILIM GND C L 0. µf 0 Ω V O(OUT) V/Div C L = 0 µf t - Time - 0 µs/div Figure. 0. µf Output Switchover Voltage Droop Test Circuit 0

11 TYPICAL CHARACTERISTICS (continued) OUTPUT SWITCHOVER VOLTAGE DROOP vs LOAD CAPACITANCE V I = V. TPS - Output Voltage Droop - V V O(OUT) R L = 0 Ω R L = 0 Ω C L - Load Capacitance - µf V I f = 8 Hz 0% Duty Cycle NC 3 00 Ω PW D0 IN D OUT VSNS IN ILIM GND µf 0. µf 0. µf µf 0 µf 7 µf 00 µf 0 Ω 0 Ω Output Switchover Voltage Droop Test Circuit Figure.

12 TPS TYPICAL CHARACTERISTICS (continued) 300 INRUSH CURRENT vs LOAD CAPACITANCE 0 Inrush Current - ma V I = V V I = 3.3 V I I C L - Load Capacitance - µf f = 8 Hz 90% Duty Cycle V I NC NC 3 00 Ω PW STAT IN D0 OUT D IN ILIM GND µf 0 Ω To Oscilloscope 0. µf 0. µf µf 0 µf 7 µf 00 µf Output Capacitor Inrush Current Test Circuit Figure 6.

13 TYPICAL CHARACTERISTICS (continued) TPS 80 SWITCH ON-RESISTANCE vs JUNCTION TEMPERATURE 0 SWITCH ON-RESISTANCE vs SUPPLY VOLTAGE Switch On-Resistance m Ω r DS(on) TPS r DS(on) Switch On-Resistance m Ω TPS T J Junction Temperature C V I(INx) Supply Voltage V Figure 7. Figure 8. IN SUPPLY CURRENT vs SUPPLY VOLTAGE IN SUPPLY CURRENT vs SUPPLY VOLTAGE I I(IN) IN Supply Current µ A Device Disabled V I(IN) = 0 V I O(OUT) = 0 A IN Supply Current µ A I(IN) I IN Switch is ON V I(IN) = 0 V, I O(OUT) = 0 A V I(IN) IN Supply Voltage V V I(IN) Supply Voltage V Figure 9. Figure 0. 3

14 TPS TYPICAL CHARACTERISTICS (continued) Supply Current µ A I(INx) I SUPPLY CURRENT vs JUNCTION TEMPERATURE Device Disabled V I(IN) =. V V I(IN) = 3.3 V I O(OUT) = 0 A I I(IN) = 3.3 V I I(IN) =. V T J Junction Temperature C Supply Current µ A I(INx) I SUPPLY CURRENT vs JUNCTION TEMPERATURE IN Switch is ON V I(IN) =. V, V I(IN) = 3.3 V I O(OUT) = 0 A I I(IN) I I(IN) T J Junction Temperature C Figure. Figure.

15 TPS APPLICATION INFORMATION The circuit in Figure 3 allows one or two battery packs to power a system. Two battery packs allow a longer run time. The TPS/ cycles between the battery packs until both packs are drained. IN:.8 -. V PW 0. µf R Switch Status NC 3 STAT D0 D ILIM IN OUT IN GND C L R L R ILIM IN:.8 -. V C 0. µf Figure 3. Running a System From Two Battery Packs In Figure, the multiplexer selects between two power supplies based upon the D logic signal. OUT connects to IN if D is logic, otherwise OUT connects to IN. The logic thresholds for the D terminal are compatible with both TTL and CMOS logic. IN:.8 -. V PW 0. µf R Switch Status 3 STAT D0 D ILIM IN OUT IN GND C L R L R ILIM IN:.8 -. V 0. µf Figure. Manually Switching Power Sources

16 TPS DETAILED DESCRIPTION AUTO-SWITCHING MODE D0 equal to logic and D equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the higher of IN and IN. MANUAL SWITCHING MODE D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN if D is equal to logic, otherwise OUT connects to IN. N-CHANNEL MOSFETs Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic selects the IN switch, IN switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so output-to-input current cannot flow when the FET is off. An integrated comparator prevents turnon of a FET switch if the output voltage is greater than the input voltage. CROSS-CONDUCTION BLOCKING The switching circuitry ensures that both power switches never conduct at the same time. A comparator monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of the other FET is below the turnon threshold voltage. REVERSE-CONDUCTION BLOCKING When the TPSx switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPSx does not connect a supply to the output until the output voltage has fallen to within 00 mv of the supply voltage. Once a supply has been connected to the output, it remains connected regardless of output voltage. CHARGE PUMP The higher of supplies IN and IN powers the internal charge pump. The charge pump provides power to the current limit amplifier and allows the output FET gate voltage to be higher than the IN and IN supply voltages. A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET. CURRENT LIMITING A resistor R (ILIM) from ILIM to GND sets the current limit to 0/ R (ILIM) and 00/R (ILIM) for the TPS and, respectively. Setting resistor R (ILIM) equal to zero is not recommended as that disables current limiting. OUTPUT VOLTAGE SLEW-RATE CONTROL The TPS/ slews the output voltage at a slow rate when OUT switches to IN or IN from the Hi-Z state (see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can adversely effect the voltage bus and cause a system to hang up or reset. It can also cause reliability issues like pit the connector power contacts, when hot plugging a load like a PCI card. The TPS/ slews the output voltage at a much faster rate when OUT switches between IN and IN. The fast rate minimizes the output voltage droop and reduces the output voltage hold-up capacitance requirement. 6

17 PACKAGE OPTION ADDENDUM -Apr-03 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TPSPW ACTIVE TSSOP PW 8 0 Green (RoHS & no Sb/Br) TPSPWG ACTIVE TSSOP PW 8 0 Green (RoHS & no Sb/Br) PW ACTIVE TSSOP PW 8 0 Green (RoHS & no Sb/Br) PWG ACTIVE TSSOP PW 8 0 Green (RoHS & no Sb/Br) PWR ACTIVE TSSOP PW Green (RoHS & no Sb/Br) PWRG ACTIVE TSSOP PW Green (RoHS & no Sb/Br) () Lead/Ball Finish MSL Peak Temp (3) Op Temp ( C) Top-Side Markings () CU NIPDAU Level--60C-UNLIM -0 to 8 CU NIPDAU Level--60C-UNLIM -0 to 8 CU NIPDAU Level--60C-UNLIM -0 to 8 CU NIPDAU Level--60C-UNLIM -0 to 8 CU NIPDAU Level--60C-UNLIM -0 to 8 CU NIPDAU Level--60C-UNLIM -0 to 8 Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Addendum-Page

18 PACKAGE OPTION ADDENDUM -Apr-03 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

19 PACKAGE MATERIALS INFORMATION -Jun-03 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant PWR TSSOP PW Q Pack Materials-Page

20 PACKAGE MATERIALS INFORMATION -Jun-03 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PWR TSSOP PW Pack Materials-Page

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