Figure 1: Over Voltage, Under Voltage, Over Current and Inrush Current Protection

Transcription

1 a) Over Voltage, Under Voltage, Over Current and Inrush Current Protection Figure 1: Over Voltage, Under Voltage, Over Current and Inrush Current Protection

2 The protection is implemented using a controller. This device does the inrush current limit, overcurrent and over-voltage protection. The Current Limiting and Cut-off Block monitor the input voltage continuously. The FET is kept on as long as the input voltage and current are within limits. If the input voltage or input current goes beyond the operating limits, the FET is immediately turns off. Nominal System Voltage: 28 V Maximum Operating System Voltage: 32 V Overvoltage Threshold: 54V Under voltage Threshold: 12V Steady-state Load Current: 25A max. Load Capacitance: 500 μf maximum Maximum Ambient Temperature: 71 C Maximum Static Junction Temperature 150 C Maximum Transient Junction Temperature: 175 C a) R SENSE (R20) The sense resistor is chosen based on the load current required to start the TIMER The maximum power dissipated by the sense resistor at 30 A is So that sense resistor R20 has been selected for dissipating 3 W. b) Mosfet (Q4 & Q5 ) The first step to choose a suitable MOSFET is to select the V DS and I D criteria. For a 28-V system, V DS should be at least 70 V±5V (2.5 times) to handle transients that could destroy the MOSFET. The I D of the MOSFET should be much larger than the required maximum (see the SOA graph in Figure 7). In high-current applications, one of the most important specifications will be the MOSFET s R DSON. Low values of this parameter will ensure that minimum power is lost in the MOSFET when it is fully enhanced in normal operation and that minimal heat is generated at full load. for single MOSFET Since we are using two Mosfet so I limit become half, So for each MOSFET We are able to find a suitable FET with an RDSON of 1 mω at 25 C and 1.8mΩ at 125 C. These devices are in a package such as a with a large copper base and very low RθJC. That s why FDB031N08 is suitable for our design.

3 The power dissipation of the MOSFET at full dc load needs to be considered because overheating must be avoided. As the temperature of the MOSFET increases, its power rating is reduced, or derated. In addition, running MOSFETs at high temperatures decreases their life span. Recall that the hot-swap controller initiates the TIMER at a minimum sense voltage of 50 mv. For this calculation, we need to know the maximum possible dc current that can flow without tripping the TIMER. Assume the worst-case V REGMIN of 50 mv. Then, Two parallel Mosfet has been used for equal load sharing and to reduce temperature Rise. This will effectively reduce the R DSON and thus the power dissipation in the MOSFETs. With two MOSFETs, a maximum temperature rise of C per MOSFET will be incurred, assuming current is divided evenly between the devices (some tolerance should be allowed). The following shows the power in each MOSFET: The MOSFET's maximum R DSON is 1.8 C, each Mosfet will have power loss P mosfet = ( ) = W The MOSFET s thermal resistance at ambient temperature is specified in the data sheet. The footprint size and additional copper will have an effect on this value. Max has been considered is 60 C/W. As the MOSFET is required to dissipate W, a worst-case temperature rise of C above ambient can be expected: = C Figure 2: SOA graph of Mosfet c) Choose the Power Limit PLIM and the PROG Resistors, R26 and R28 A lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the TPS2493 is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage across the sense resistor (VSNS) to a very-low value. Minimum V SNS of TPS2493 is 5mV. To avoid significant degradation of the power limiting, TI does not recommend a VSNS of less than 5 mv. Based on this requirement, the minimum allowed power limit can be computed as follows:

4 Because the VPROG pin, which programs the power limit of the device, has a minimum voltage of 0.4 V, the set P LIM must also result in the voltage at V PROG being greater than 0.4 V. Based on this requirement the minimum allowed power limit can be computed as follows: P LIM, MIN2 = V PROG I LIM_MAX 10 = =100 W MOSFET dissipates large amounts of power during power-up or output short circuit. Power limit, P LIM should be set to prevent the MOSFET die temperature from exceeding a short term maximum temperature, T J (max2). Short term T J (max2) may be set as high as 150 C (specified on FET datasheet) while still leaving ample margin for the typical manufacturer's rating of 175 C. The R26 and R28 resistors set V PROG, programming the FET power dissipation. R θja is 62.5 C/W, R θjc is 0.4 C/W, and R θca is 62.1 C/W (approx. 60 C/W max.) for the device we chose above. P LIM can be estimated for single Mosfet as follows: ( ( ) ) ( ) Where R θca is the Mosfet plus PCB case-to-ambient thermal resistance, R θjc is Mosfet junction-to-case thermal resistance, R DSON is Mosfet channel resistance at the maximum operating temperature, and the factor of 0.7 accounts for the tolerance of the constant power engine. In this case we know that power limit is less than I LIMIT x V IN and that power limit will control operation during a short circuit. It is often advantageous to use a transient value of R θjc to get a usable solution that is a VPROG within the recommended range. If a current/power limited startup is used, transient R θjc should be based on the TIMER period (see below). FET manufacturers typically provide transient thermal resistance in graphic format on their datasheet. Additional information can be found in FDB031N08. Because the power limit has to satisfy both the V SNS and V PROG, the greater P LIM, MIN value is used as the basis for sizing the resistive divider. In this design example it is 110 W. The maximum ratio of the resistive divider can be computed as follows: The following equations calculate VPROG and R4 using an assumed R28 =10 kω. ( ) ( ) The output I vs. VOUT curve for this configuration is shown in Figure 3.

5 Figure 3:TPS2493 Power and Current Limit Curve d) Choose the TIMER Capacitor, CT and Turn-On Time The fault timer runs when the hot swap is in power limit or current limit, which is the case during start-up. Thus the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current limit (ILIM x VDS < PLIM) the maximum start time can be computed with following equation: For most designs (including this example) ILIM x VDS > PLIM so the hot swap will start in power limit and transition into current limit. In that case the start time can be computed as follows: [ ] [ ] The actual startup time is slightly longer, as the power limit is a function of VDS and decreases as the output voltage increases. To ensure that the timer never times out during start-up, TI recommends setting the fault time (t flt ) to be more than 1.75 x t start or 4.375ms 5ms. This accounts for the variation in power limit, timer current, and timer capacitance. Thus CTIMER can be computed as follows:

6 The CTIMER is chosen as 33 nf. Once the CTIMER is chosen the actual programmed fault time can be computed as follows: e) Check MOSFET SOA Once the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all test conditions. During a Hot-Short the circuit breaker trips and the TPS2493 restarts into power limit until the timer runs out. In the worst case the MOSFET s V DS will equal V IN,MAX, I DS will equal P LIM / V IN,MAX and the stress event will last for t flt. For this design example the MOSFET has 33 V, 4 A across it for 4.88ms. Based on the SOA of the FDB031N08, it can handle 33 V, 3.5 A for 10 ms and it can handle 33 V, 14A for 1ms. The SOA for 3.26ms can be extrapolated by approximating SOA vs time as a power function as shown in following equations: ( ) ( ) ( ) ( ) =5.39A Note that the SOA of a MOSFET is specified at a case temperature of 25 C, while the case temperature can be much hotter during a hot-short. The SOA should be de-rated based on T C,MAX using following equations: ( ) ( ) Based on this calculation the MOSFET can handle 3.4A, 33 V for 4.88ms at elevated case temperature, but is required to handle 4A during a hot-short. This means the MOSFET will be at risk of getting damaged during a hot-short. f) Set UVLO and OVLO Thresholds By programming the UVLO and OVLO thresholds, the TPS2493 enables the seriespass device (Q4 & Q5) when the input supply voltage (VIN) is within the desired operational range. If VIN is below the UVLO threshold or above the OVLO threshold, Q4 & Q5 are switched off, denying power to the load. Per our system design requirements above, both over-voltage shutdown and undervoltage shutdown are desired. Equations for calculating the thresholds are: Assume R3 is 3.3 kω and use the following procedure to determine R1 and R2.

7 So, R3=3.33K R2=18.33K-3.33K=15K R1=131.2K-15K=116.2K ( ) ( ) (( ) ) ( ) Since we are using two different resistive networks for UV an OV threshold that s why For UV, R1+R2=122K+18.2K and R3=3.3K (R1 equivalent to R29+R30, R2 equivalent to R32+R23 and R3 equivalent to R24) For OV, R1+R2=121K+10K and R3=3.3K (R1 equivalent to R25, R2 equivalent to R22 and R3 equivalent to R19) g) Choose R15 & R14, and CIN R15 & R14 are intended to suppress high-frequency oscillations; a resistor of 4.7Ω will serve for most applications. CIN is a bypass capacitor to help with control of transient voltages, unit emissions, and local supply noise while in the disabled state. Where acceptable, TI recommends a value in the range of μf to 0.1 μf. SO in parallel combination C3 (2.2uF), C4 (2.2uF), C12 (0.1uF), and C103 (10uF) has been used. h) Input and Output Protection Proper operation of the TPS2493 hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in. The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current. This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET shuts off. The TVS should be chosen to have minimal leakage current at VIN,MAX and to clamp the voltage during hot-short events. For many high power applications, SMCJ100CA is a good choice.

8 i) Inrush Designs Gate Capacitor (dv/dt) Control The TPS2493 is being used with applications that require constant turn-on currents. The current is controlled by a single capacitor from the GATE terminal to ground with a series resistor. Q4 & Q5 appears to operate as a source follower (following the gate voltage) in this implementation. Again assuming that the output capacitor charges without additional loading, choose a time to charge, t ON, based on the load capacitor, C O input voltage V I, and desired charge current I CHARGE. When power limiting is used (VPROG < VREF) choose I CHARGE to be less than PLIM /V VCC to prevent the fault timer from starting. The fault timer starts only if power or current limit is invoked. ( Here dv/dt=0.5v/ms)