Optimum PCB and Stencil Layout for Wireless USB QFN Package AN5060. Application Note Abstract

Transcription

1 Optimum PCB and Stencil Layout for Wireless USB QFN Package Application Note Abstract AN5060 Author: Nelson Zhang Associated Project: No Associated Part Family: CYWUSB6934, CYWUSB6935 Software Version: None Associated Application Notes: None AN5060 provides guidelines and recommendations for printed circuit board (PCB) design using the WirelessUSB LS/LR 2.4-GHz DSSS Radio SoC IC QFN package. Introduction When designing a system board using the WirelessUSB LS/LR QFN chip for wireless product applications, there are several important factors to consider. It is advised to pay critical attention to PCB design and assembly aspects when using QFN package in a system design. This application note contains guidelines and recommendations that can help alleviate issues due to sub-optimal board layout around the WirelessUSB LS/LR QFN packaged IC. General Description of QFN Package The Cypress Semiconductor WirelessUSB LS/LR QFN package offers low-inductance I/O pads on a 0.5-mm pitch. The need for low-cost surface-mount plastic packages that operate to high frequency above 1 GHz with low package thermal resistance has led to the development of Quad Flatpack No-Lead (QFN) packages. In addition, an exposed conductive paddle effectively decreases the thermal resistance, which in turn provides excellent heat dissipation from the die. In most cases the exposed paddle also acts as electrical ground. This provides improved electrical performance by minimizing ground lead inductance. This decreased ground inductance improves high frequency RF performance. To take full advantage of the RF characteristics that are inherent to QFN package one must design the PCB pad, the stencil and assembly to provide adequate surface area for self alignment, sufficient solder for a proper fillet, and optimum grounding while maintaining isolation on RF, digital control pins. To successfully integrate these QFN packages into a system design operating at very high frequencies, proper PCB layout, handling and assembly guidelines must be followed. Surface Mount Considerations for QFN Package The following general guidelines are given to aid the customer designing a PCB that uses the QFN package. These suggestions should be evaluated and optimized for each individual process and design. Proper soldering of the exposed paddle (EPAD) to a suitable thermally conductive surface, such as a ground plane, is critical in obtaining the improved performance of the exposed paddle package and proper operation of WirelessUSB LS/LR IC. February 9, 2011 Document No Rev. *A 1

2 Figure 1. Wireless LS/LR 48-Pin QFN Package Outline. MIN DIMENSION in mm MAX REFERENCE JEDEC MO 220 PKG WEIGHT 0.13 grms Top View LF48A LY48A PART # STANDARD PKG LEAD FREE PKG 48LD QFN 7X7 mm Package Outline Figure 2. WirelessUSB LS/LR 48 Pin QFN Package Outline Including EPA E-PAD SIZE PADDLE SIZE (X, Y MAX.) 5.1 X X 5.3 The WirelessUSB LS/LR radio IC employs a 48-pin exposed paddle QFN package shown in Figure 1 and Figure 2. In order to achieve peak performance, special considerations are needed to properly design the system board and to mount the package. For enhanced thermal, electrical, RF, and board level performance, the exposed pad on the package needs to be soldered to the board using a corresponding thermal pad on the board. The PCB footprint design needs to be considered from dimensional tolerances due to package, PCB, and assembly. The QFN package has a Exposed Pad (EPAD) of size 209 mils 209 mils (width length) on the bottom of the IC to improve RF grounding and RF performance of the small package. Cypress recommends adding a 100-mil hole underneath the ground pad of the IC package to allow a solid soldering joint ground connection. This allows excess solder February 9, 2011 Document No Rev. *A 2

3 to bleed through the hole, permits visual inspection of the ground connection, and simplifies rework on the bench, if necessary. A number of factors may have a significant effect on mounting QFN package on the board and the quality of solder joints. Some of these factors include: amount of solder paste coverage in thermal pad region, stencil design for peripheral and thermal pad region, type of vias, board thickness, lead finish on the package, surface finish on the board, type of solder paste, and reflow profile. It should be emphasized that this is just a guideline to help the user in developing the proper system board design and surface mount process. Actual studies as well as development effort may be needed to optimize the process as per user s surface mount practices and requirements. As shown in Figure 1, the lands on the package bottom side are rectangular in shape with rounded edge on the inside. Since the package does not have any solder balls, the electrical connection between the package and the system board is made by printing the solder paste on the system board and reflowing it after component placement. In order to form reliable solder joints, special attention is needed in designing the system board pad pattern and solder paste printing. Perimeter PADs Design Typically the PCB pad pattern for an existing package is designed based on guidelines developed within a company or by following industry standards such as IPC-SM-782. For the purpose of this document, IPC s methodology is used here for designing PCB pad pattern. However, because of exposed die paddle and the package lands on the bottom side of the package, certain constraints are added to IPC s methodology. The pad pattern developed here includes considerations for lead and package tolerances. Figure 3 shows the bottom and side views of full lead option, indicating the dimensions needed to design the pad pattern for PCB. Since most packages are square with dimension D equal to dimension E and the leads are along the E direction for dual packages, the side view dimensions (D, S, D2, and L) are used to determine the land length on the PCB. Figure 3. QFN Component Dimensions Needed for PCB Land Pattern Design D D2 D b SE E2 E e SD QFN 48 PIN Component Dimensions needed for PCB Land Pattern Design L D2 S L February 9, 2011 Document No Rev. *A 3

4 PCB Land Pattern The PCB pad pattern and dimensions to be determined are shown in Figure 4. In the figure, the dimensions ZDmax and GDmin (and ZEmax and GEmin) are the outside to outside and inside to inside pad dimensions, respectively. The dimension X and Y indicate the width and the length of the pad, respectively. Figure 4. PCB Land Pattern Dimensions to be Determined ZDmax D2' 100 mil Diameter hole PIN 1 E-PAD FOOTPRINT Table 1. QFN Package Dimensions QFN Package Size I/O Leads/Side Lead Pitch 7X mm C PL GEmin ZEmax C LL AEmax TYPICAL PAD FOOTPRINT QFN Package Dimensions with Tolerance D(min) D(max) E(min) E(max) b(min) b(max) L(min) L(max) All Dimensions in mm Y ADmax GDmin QFN 48 PIN PCB Land Pattern Two additional clearances, C LL and C PL, are also defined to avoid solder bridging. While C LL defines the minimum distance between land to land for the corner joints on adjacent sides, C PL defines the minimum distance between the inner tip of the peripheral lands and the outer edge of the thermal pad. In order to design a proper pad pattern, tolerance analysis is required on package and PCB dimensions. The tolerance analysis requires the consideration of: (a) component tolerances, (b) the PCB tolerances, and (c) the accuracy of the equipment used for placing the component. In addition, minimum values of toe, heel, and side fillets are considered for the formation of reliable solder joints. For component tolerances, the profile tolerances usually given in the package outline drawing are converted into Maximum Material Condition (MMC) and Least Material Condition (LMC) based tolerances. The minimum and maximum values thus obtained are listed in Table 1 for QFN packages. In order to determine the pad pattern dimensions, three sets of tolerances are involved; one set for the overall component tolerances, and the other two sets for the leads on each end. Since it is unrealistic to assume that all three tolerances will be at their worse case, a more realistic RMS (root-mean-square) system is used here as described in IPC- SM-782. X Table 2. Board Land Pattern Dimensions Board Land Pattern Dimensions X max Y ref A max G min Z max D2 th max All Dimensions in mm The dimension S, shown in Figure 3, is not normally shown in package outline drawings. Since this dimension is required to determine the pad length, it is calculated as follows: SDmin = Dmin 2Lmax SD max = SD min + SD tol (rms) Where, SD tol ( rms) = (( D max D min ) 2 + 2( L max L min ) 2 ) The board tolerance defines the difference between the MMC and LMC of each pad pattern dimension and is assumed as 0.05 mm here. The placement tolerance is also assumed as 0.05 mm, given that most placement machines have placement accuracy between 20 and 70 microns. The minimum values for solder joint fillets, defined in Figure 5, used to calculate the land pattern dimensions are: Minimum Toe Fillet = J T min = 0.1mm Minimum Heel Fillet = J H min = 0.05mm Minimum Side Fillet = J S min = 0.0mm The values are selected recognizing that both sides and one end of the leads are embedded in the mold compound and solder fillets cannot be formed on these sides. The fourth side, however, has either full of half the thickness of the lead exposed on the side of the package, depending on the full lead or lead pull back options. Since the pad pattern dimension is most likely to be larger than the nominal lead February 9, 2011 Document No Rev. *A 4

5 dimension, solder joints may assume some angular shape or fillets as shown in Figure 5 for full lead option. It should be realized that the formation of the toe fillet is not guaranteed as the sides of the leads are not plated. It is generally observed, however, that the toe fillets are formed depending on the type of solder paste used and length of exposure of package to environment. The toe fillet, if formed, will improve the solder joint reliability and allocation must be made for its formation. Although the toe fillet is not expected to form for the lead pullback option, the same pad pattern as the one for full lead option can be used for this design. Figure 5. Definition of Toe, Heel, and Side Fillets J S min J H min Pad Pattern Design Calculations With these assumptions and tolerances, the land pattern dimensions are determined by using the following relations: ZD max = D min + 2J T + T T X max = b min + 2J S + T S J T min GD min = SD max 2J T T H Where T T, T H, and T S are the RMS values of toe, heel, and side tolerances accounting for component, board, and placement tolerances. The calculations for these values are defined in more detail in IPC-SM-782 document. The above calculation for GD min does not account for the leads on all four sides of the package. In order to include this and to avoid any solder bridging between the two perpendicular leads on each corner, a minimum clearance, C LL, is needed. This clearance, shown in Figure 3, is assumed as 0.1 mm and the final value of GD min is determined by using the following constraint: GD min AD max + 2 C LL Where AD max = (Lead Pitch) x (# of leads on one side 1) + Pad Width Finally, the pad length is determined as: Y = ZD max ( GD min ) The pads may also be rounded on the inner edge. Using the above methodology, the perimeter pad pattern dimensions for various QFN packages with Full lead option are listed in Table 2. It should be noted that the calculated Xmax dimension (pad width) from the above equations is reduced for 0.4- and 0.5-mm pitch devices to avoid any solder bridging issues. Also, because of rectangular dimension of the package in most case, the suffix D and E from dimension notations in Figure 3 (e.g., ZD and ZE) are dropped in the table and it is implied that Zmax =ZDmax = ZEmax. Printed Circuit Board Design Considerations One of the key efforts in mounting the QFN package on a substrate PCB is the design of land pad. Electrical connection between the component and the PCB can be made by screen printing solder paste on the PCB and re-flowing after placement. It is essential to design the pad pattern to the component exposed lead frame pattern for ensuring reliable solder joints. Land Pattern Styles There are two basic types of PCB land pad configurations for mounting the QFN package: Non Solder mask defined (NSMD) style and the solder mask defined (SMD) style, as shown in Figure 6. The NSMD contact pads have the solder mask pulled away from the solderable metallization, while the SMD pads have the solder mask over the edge of the metallization. The NSMD pads configuration where the solder will flow around both the top and the sides of the metallization are recommended over SMD pads due to tighter tolerance on copper etching than solder masking. With the SMD pads the solder mask restricts the flow of the solder paste on the top of the metallization which prevents the solder flow from flowing along the side of the metal pad. NSMD, by definition, also provides a larger copper pad area and allows the solder to anchor to the edges of the copper pads, thus providing improved solder joint reliability. February 9, 2011 Document No Rev. *A 5

6 Figure 6. NSMD and SMD Pad Configurations \ Solder Mask Overlay Lead Frame Wire Bond QFN Die Cross-Section of single-device QFN Package Solder Mask Opening NSMD SMD PCB Design The PCB lead finger pad is designed such that a minimum of 0.1 mm longer than the package land length and the pad is extended 0.05 mm towards the center line of the package. The width must be a minimum 0.05 mm (0.025 mm per side, as shown in Figure 7. However, the pad width is reduced to the dimension of the component pad for lead pitches of 0.5 mm to 0.28 mm wide to avoid solder bridging. Figure 7. PCB Lead Finger Geometry PCB Pad 0.05 mm 0.1 mm PCB Pad Solderable Pad Min mm Per side for Lead Pitches Greater than 0.65 mm Exposed Pad (EPAD) PCB Design The construction of the exposed pad enables enhanced thermal and electrical characteristics. In order to take full advantage of this feature the pad must be physically connected to the PCB substrate with solder. The dimensions of the ground EPAD must be equal or greater than the exposed pad on the QFN package. Adequate clearance is necessary to prevent solder bridging. Experiments have concluded that a minimum clearance of 0.15 mm (0.2 mm recommended) is satisfactory for most designs. PCB Solder Mask and Land Pattern Design The QFN package has a dense land pattern and exposed metal base (EPAD); there are two main PCB perimeter pad design factors namely the pad (terminal) and the spacing between pads. The package pad width and the spacing between package pads are shown in Table 3 from the case outline drawings. Table 3. Case Outline PAD Width Limits Case Outlne Dim ensions for QFN Package Pad width Case Outline Pad W idth Limits 0.5 mm Pitch QFN Pad Spacing Minimum 0.18 mm 0.31 mm Nominal 0.23 mm 0.25 mm Maxim um 0.28 m m 0.19 m m When dimensionally possible, the solder mask should be located al least ±0.076 mm (0.003 in) away from the edge of the solderable pad. This spacing is used to compensate for the registration tolerance of the solder mask, as well as to insure that the solder is not inhibited by the mask as it reflows along the side of the metal pad. IPC-SM-782 is one of the industry standard guidelines for developing PCB pad patterns. This application note along with IPC-SM-782 serves as a guide to design the optimum PCB land pattern for mounting the QFN package. The dimensions of the PCB s solderable pads should match the substrate pad pattern shown in the Figure 8. The side view dimensions (D, S, D2 and L) are used to determine the lead length on the PCB. The land pattern and solder mask pattern for the QFN package are shown with their proper alignment in Figure 8. February 9, 2011 Document No Rev. *A 6

7 Figure 8. PCB Land Pattern and Solder Mask for QFN Package 233/5.9 Mask Opening 252/6.4 38/0.96 Mask Opening Solder Mask 288/7.31 Square 0.006" Mask/Metal overlap 0.010" MIN MASK WIDTH PIN 1 201/5.1 Square Mask Opening 209/5.3 SQUARE GROUND PAD E-Pad Hole Pad Size QFN 48 PIN Solder Mask and Land Pattern 20/ /5.78 Dimension in mil/mm Ground E-PAD TYPICAL PAD FOOTPRINT 11/ /0.84 QFN Board Mounting Process The QFN board mounting process is optimized by first defining and controlling the following processes: 1. Creating and maintaining a solderable metallization on the PCB contacts 2. Choosing the proper solder paste 3. Screening/stenciling the solder paste onto the PCB 4. Solder Mask 5. Placing the package onto the PCB 6. Re-flowing the solder paste 7. Final solder joint inspection Recommendations for each of these processes are mentioned in the following sections. PCB Surface Finishes and Solderable Metallization There are a variety of surface finishes commonly available. The key factor in selecting an acceptable surface finish is to ensure that the land pads have a uniform coating. Irregular surface plating, uneven solder paste thickness, and crowning of the solder plating can reduce overall surface mount yields. Bare copper with an organic solderability preservative (OSP) coating, electroless nickel/immersion gold, or electroplated nickel/gold finishes have been shown to provide an acceptable land pad surface. One type of surface finish to avoid is referred to as a dry-film process. This is because the copper undercut effect caused during the dry film removal prevents optimal sidewall wetting during the re-flow process. The advantages of plating over OSPs are: Shelf life Permanent coverage of copper vias and other features not exposed to a solder process and Contamination resistance A controlled assembly process for QFN soldering relies on a flat uniform attachment site. Achieving this allows for greater control of solder paste print uniformity. There are three commonly plated solderable metallizations which are used for PCB surface mount devices. In all the cases, it is imperative that the plating is uniform, conforming, and free of impurities to insure a consistent solderable system. The first metallization consists of an Organic Solderability Preservative coating (OSP) over the copper plated pad. The organic coating assists in reducing oxidation in order to preserve the copper metallization for soldering. The second recommended solderable metallization consists of plated electroless 200 µinches nickel over the copper pad, followed by immersion gold of 3-8 µinches. The thickness of the electroless nickel layer is determined by the allowable internal material stresses and the temperature excursions the board will be subjected to throughout its lifetime. Even though the gold metallization is typically a selflimiting process, the thickness should be at least 3 8 µinches thick, and not consist of more than 5% of the overall solder volume. Having excessive gold in the solder joint can create gold embitterment which may affect the reliability of the joint. The third recommended solderable metallization consists of plated electroless 200 µinches nickel over the copper pad, followed by 30 µinches 50 µinches hard gold. Solder Paste Screen Printing Process An important factor in producing high-yield PCB assemblies is the quality of the paste print. A low residue, "no-clean" Type 3 solder paste with SN63/Pb37 (63% tin and 37% lead) is commonly used in mounting QFN ICs; however, water soluble flux materials are widely used as well. The paste is the vehicle that provides the flux and solder alloy necessary for a reliable and repeatable PCB assembly process. Therefore it is recommended to use special SMD specific solder paste and follow the suggested thermal profile and reflow instructions. Solder Paste Application Methods Solder paste can be applied using screen printing, stencil printing or dispensing, with screen/stencil printing being the most common high-volume solder application method. Using these methods, the solder paste is applied on the top surface of the screen or stencil with the print squeegee at one end of the stencil. During the printing process, the squeegee presses down on the stencil to the extent that the bottom of the stencil touches the surface of the board. The solder paste is then printed on the land through the opening in the stencil February 9, 2011 Document No Rev. *A 7

8 when the squeegee traverses the entire length of the image area on the metal mask. Although the print processes for stencil and screen printing are similar, the differences lie in the construction of the mask. A screen utilizes an emulsion laminated over a wire mesh. The wire mesh provides mechanical support while the emulsion defines the solder print pattern. Therefore an opening in a screen will contain wire mesh around which the solder paste must flow to reach the PCB surface. A stencil is fabricated from a thin sheet of metal in which the solder print patterns are defined by etched or lasered openings in the metal sheet. Therefore an opening in the stencil will provide an unobstructed path for the solder paste flow. Stencils however have the disadvantage of being dependent on over-etching, which can occur during its fabrication. The choice of stencil or screen depends on the application. Solder paste can also be dispensed by pressure/time systems, auger valves, or positive displacement valves. Using these methods, solder paste is dispensed in a serial manner, thus the process rate is much slower than that of stencil or screen-printing. Dispensing is often used in small volume engineering, high product mix or rework applications due to its process flexibility. Additionally, dispensing may have special applications for products that require different print thicknesses on a single board. Solder paste that is too thick will result in excessive solder in the joints. This may cause solder balls and/or solder bridging between components or pads. Solder paste that is too thin may result in insufficient solder fillets and/or voids in the solder. This may degrade the mechanical, thermal and electrical properties of the solder. To the first order, the thickness of the paste print is determined by the thickness of the metal mask of the stencil (or the emulsion thickness and mesh diameter of a screen). Varying the print process parameters and the percent metal content of the solder paste can modify this baseline thickness. Stencil Design for Perimeter Pads and Epad The optimum and reliable solder joints on the perimeter pads should have about 50 to 75 microns (2 to 3 mils) standoff height and good side fillet on the outside. A joint with good standoff height but no or low fillet will have reduced life but may meet application requirement. The first step in achieving good standoff is the solder paste stencil design for perimeter pads. The stencil aperture opening should be so designed that maximum paste release is achieved. This is typically accomplished by considering the following two ratios: Area Ratio = Area of Aperture Opening/Aperture Wall Area and Aspect Ratio = Aperture width/ Stencil Thickness For rectangular aperture openings, as required for this package, these ratios are given as Area Ratio = LW/2T(L+W) and Aspect Ratio = W/T Where L and W are the aperture length and width, and T is stencil thickness. For optimum paste release the area and aspect ratios should be greater than 0.66 and 1.5 respectively. It is recommended that the stencil aperture should be 1:1 to PCB pad sizes as both area and aspect ratio targets are easily achieved by this aperture. The opening can be reduced for lead pullback option because of reduction of solderable area on the package. The stencil should be laser cut and electro polished. The polishing helps in smoothing the stencil walls, which results in better paste release. It is also recommended that the stencil aperture tolerances should be tightly controlled, especially for 0.4- and 0.5-mm pitch devices, as these tolerances can effectively reduce the aperture size. It is essential to form reliable solder joints. The contrast between the large exposed metal base and the dense land pattern of the QFN package can present a challenge in producing an even solder line thickness. To achieve this, careful consideration must be applied to the PCB land pattern geometry and stencil design. Stencil screening the solder onto the PCB board is commonly used in the industry. The recommended stencil thickness used is mm to mm (0.003 in to in) and the sidewalls of the stencil openings should be tapered approximately 5 degrees to facilitate the release of the paste when the stencil is removed from the PCB. For a typical edge PCB terminal pad, the stencil opening should be the same size as the pad size on the package. However, in cases where the exposed pad (EPAD) is soldered to the PCB, the stencil opening must be divided into array of smaller openings. Dividing the larger exposed pads into smaller screen openings reduces the risk of solder voiding and allows the solder joints for the smaller terminal pads to be at the same height as the larger ones. It is recommended that a window pane stencil opening pattern for the PCB exposed pad as shown in Figure 9. February 9, 2011 Document No Rev. *A 8

9 Figure 9. Window Pane Pattern for EPAD Stencil Opening 5.3 mm Hand soldering of the QFN package is not recommended due to the fine pitch of the package leads and the inability to properly attach the exposed metal base to the PCB. Furthermore, the use of conductive epoxy is not recommended since these epoxies will bleed, causing shorts between lands. Solder paste must be used to attach QFN package to the PCB. For proper solder thickness and alignment, the solder paste must be applied to the PCB using a stencil printer. The volume of solder paste dispensed via screen-printing will be dependent on the stencil opening and stencil thickness. A recommended stencil pattern is shown in Figure 10. Stencil alignment to the PCB should be to within ±1 mil to prevent formulation of solder balls between the lands during the re-flow process. Figure 10. Solder Paste Stencil-Design 10 Original Stencil Exposed Pad opening 0.25 mm Window Pane Frame Width 5.3 mm 0.25 mm E-PAD FOOTPRINT Window Pane Stencil Openings 20 TYP 95 SQUARE 4 PLCS R 4 TYP 192 PLCS 17 Dimension in mil TYP 9 QFN 48 PIN Solder Paste Stencil SQUARE 17 Solder Mask The PCB land pattern geometry is critical due to the dense land pattern and exposed metal base of the QFN package. The application of solder mask is required, and must be applied to the PCB between the land pads and the ground pad. As described at the beginning of this section, non solder mask defined (NSMD) design is recommended over solder mask defined style (SMD) to produce good solder joint reliability. The solder mask can be designed around each individual lead finger for lead pitches 0,65 mm and above. The solder mask opening should be 120 to 150 µm. Solder mask openings must be between 60 µm to 75 µm larger than the lead finger pad size. For a lead pitch of 0.5 mm, it is recommended to design the solder mask around all pads on each side. In order to maximize the solder mask between adjacent sides, it is necessary to round the inner corner on each row. This ensures sufficient solder mask in the corner of the PCB footprint design. See Figure 8. This allows for solder mask registration tolerances, which are typically between 50 to 65 microns, depending upon the board fabricators capabilities. Typically each pad on the PCB should have its own solder mask opening with a web of solder mask between two adjacent pads. Since the web has to be at least 75 microns in width for solder mask to stick to the PCB surface, each pad can have its own solder mask opening for lead pitch of 0.5 mm or higher, based on the pad width dimensions given in Table 3. For the cases where thermal land (EPAD) dimension is close to the theoretical maximum discussed above, it is recommended that the thermal pad area should be solder mask defined in order to avoid any solder bridging between the thermal pad and the perimeter pads. The mask opening should be 100 microns smaller than the thermal land size on all four sides. This will guarantee a 25 microns solder mask overlap even for the worse case misregistration. Component Placement onto the PCB Pick and place equipment with the standard tolerance of 0.05 mm or better is recommended. Careful device placement and minimal pressure will prevent solder paste smearing. In order to prevent solder paste smearing, the base of the QFN package should be brought to a height of 3 4 mils above the surface of the PCB. This will result in the QFN package being pressed 1 2 mils into the solder paste. Re-flow Solder Process Once the package is placed on the PC board along with the solder paste, a standard surface mount re-flow process can be used to mount the part. Reflow soldering of surface mount assemblies provides mechanical, thermal and electrical connections between the component leads or terminations, and the customer surface mount land pads. Solder paste can be applied to the surface mount lands by various methods, February 9, 2011 Document No Rev. *A 9

10 the most common being screen-printing and stencil printing [Reference 1.]. Unlike through-hole components, surface mount components (SMCs) rely entirely upon the solder interface for mechanical strength. [Reference 2]. The solder joint properties, and therefore the solder joint design, are of critical importance to the user of the SMC. Reflow profile and peak temperature has a strong influence on void formation. Companies have conducted experiments with different reflow profiles (ramp-to-peak vs. ramp-holdramp), peak reflow temperature, and time above liquidus using Alpha Metal s UP78 solder paste. Some of the representative profiles are shown in Figure 11. Figure 9 is an example of a standard re-flow profile. The exact profile will be determined, and is available, by the manufacture of the paste since the chemistry and viscosity of the flux matrix will vary. These variations will require small changes in the profile in order to achieve an optimized process. A system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the QFN package. The following profile is provided as a quideline, to be customized for varying manufacturing practices and applications. A proper reflow profile must provide adequate time for flux volatilization, proper peak temperature, time above liquidous, ramp up and cool down rates. The profile used has a direct bearing on manufacturing yield, solder joint integrity, and the reliability of the assembly [Reference 3]. A typical reflow profile is made up of four distinct zones: the preheat zone, the soak zone/flux activation zone, the reflow zone, and the cooling zone [Reference 4]. Preheat Zone Typically the heating rate in the preheat zone should be 2 C to 4 C/second and the peak temperature in this zone should be C. If the temperature ramp is too fast, the solder paste may splatter and cause solder balls. Also, to avoid thermal shock to sensitive components such as ceramic chip resistors, the maximum heating rate should be controlled. Soak Zone The soak zone is intended to allow the board and components to reach a uniform temperature, minimizing thermal gradients. The soak zone also acts to activate the flux within the solder paste. The ramp rate in this zone is very low and the temperature is raised near the melting point of solder (183 C for standard 63Sn27Pb solder). The consequences of being at too high a temperature in the soak zone are solder balls due to insufficient fluxing (when the ramp rate is too fast) and solder splatter due to excessive oxidation of paste (when the ramp rate is too slow). Typical soak times are usually around the range of C for 60 to 90 seconds. Reflow Zone In this zone the temperature is kept above the melting point of the solder for 30 to 60 seconds. The peak temperature in this zone should be high enough for adequate flux action and to obtain good wetting. For standard 63Sn37Pb solders, a peak temperature range of C is generally considered acceptable. The temperature, however, should not be so high as to cause component damage, board damage, discoloration or charring of the board. Extended duration above the solder melting point will damage temperature sensitive components and potentially create excessive intermetallic growth between the solder and the I/O pad metallization which makes the solder joint brittle and reduces solder joint fatigue resistance. Additionally high temperatures can promote oxide growth, depending upon the furnace atmosphere, which can degrade solder wetting. Cooling Zone The cooling rate of the solder joint after reflow is also important. For a given solder system, the cooling rate is directly associated with the resulting microstructure which in turn, affects the mechanical behavior of solder joints. The faster the cooling rate, the smaller the grain size of the solder, and hence the higher the fatigue resistance of the solder joint. Conversely rapid cooling will result in residual stresses between mismatched components. Therefore the cooling rate needs to be optimized. The profile of choice can affect any of the following areas, to a different degree, by one of more of the profile zones [Reference 3]. Temperature distribution across the assembly Plastic IC package cracking Solder balling Solder beading Wetting ability February 9, 2011 Document No Rev. *A 10

11 Inspection of Solder Joint The integrity of solder joints is commonly checked with an X- ray inspection system. The inspection of solder joint can detect bridging, shots between pads, opens and voids within the solder as well as any extraneous solder. X-ray inspection system features range from manual to automated optical Inspection. It is recommended that the solder has reflowed sufficiently to form acceptable joints and there is minimal voiding in the EPAD and pad solder joints, also there is no bridging visible between the joints. X-ray inspection can also be useful in highlighting possible process problems such as solder balling and voiding which are often an indication of poorly optimized reflow profiles. The QFN package pads extend up the side of the package and will produce a filleted joint. The solder joints should have enough solder volume with the proper stand-off height so that a proper shaped fillet formation is achieved. Figure 11. Standard Reflow Profile Ramp-up t L Ramp-down Critical Zone T L to T P Table 4. Standard Reflow Profile S n-p b Eutectic Assembly P b - Free Assembly Profile Feature Large Large Body Small Body Body Small Body Average ramp-up rate (T L to T p ) 3 o C/second max 3 o C/second max Preheat Temperature Min (Ts min ) 100 o C 150 o C Temperature Max (Ts max ) 150 o C 200 o C Time (Min to max)(t s ) seconds seconds Ts max to T L Ramp-up Rate 3 o C/second max Time maintained above Temperature (T L ) 183 o C 217 o C Time (t L) seconds seconds Peak Temperature /-5 o C /-5 o C /-5 o C /-5 o C Time within 5 o C of actual Peak Temperature (T P ) seconds seconds seconds seconds Ramp-down Rate 6 o C/second max 6 o C/second max Temperature 6 minutes max 6 minutes max For reflow it is recommended an IR or Forced Convection system be used or a combination system of IR and forced Convection. Cypress recommend that the standard profile provided by the solder paste supplier should be followed. In the absence of a profile the following profile, shown in Figure 11, will provide a suitable reflowed joint on QFN packages. As part of the reliability qualification of Cypress Semiconductor s Pb-free parts, the device have been tested at a maximum peak reflow temperature of 260 C for 10 seconds. Figure 12 below shows the reflow profile suggested to form a mechanically strong joint. For the Pb-free profile a peak temperature of 250 C is required to form a mechanically strong joint, although it should be noted that the package is capable of withstanding a peak temperature of 260 C( 5 /+0) for 20 seconds. Figure 12. Recommended Solder Reflow Profile. Recommended Reflow Solder Profile Temperature Temp4 Temp3 Liquidus Temperature Reflow Zone Temp2 Soaking Zone Pre Heating Zone Cooling Zone Temp1 t 1 t 2 Time t 3 t 4 t 5 February 9, 2011 Document No Rev. *A 11

12 Table 5. Recommended Reflow Profile Profile Feature S n -P b Eutectic P b - Free Assembly Assembly Temperature at point 1 25 o C (Ambient) 25 o C (Ambient) Temperature at point o C 150 o C Temperature at point o C 180 o C Temperature Max 235 o C 250 o C Temperature at point o C 180 o C Time seconds seconds Time seconds seconds Time seconds seconds Time seconds seconds Time seconds seconds Soldering Guidelines for QFN Package PCB Mounting Residue cleanability Residue appearance and characteristics Solder joint voids Metallurgical reactions between solder and substrate surface Board flatness Microstructure of solder joints Residual stress level of the assembly If required, removal of the residual solder flux can be completed by using the recommended procedures set forth by the flux manufacturer. Rework Guidelines for QFN Package After PCB assembly, the package should be inspected in transmission x-ray for the presence of voids, solder balling, or other defects underneath the package. Cross sectioning may also be required to determine the fillet shape and size, and the joint standoff height. In a QFN, only the externalside-fillet solder joint is exposed and any retouch is limited to this area. For rework of defects underneath the package, the whole package needs to be removed. The most common method of repairing surface mount devices is by using hot air devices. During this rework process care should be taken to prevent thermal damage to adjacent component or substrates. The following guidelines should be used to prevent thermal damage and to produce an acceptable solder joint after repair/rework [Reference 1.]: Characterize the rework process carefully so as not to overheat and damage the device. Keep the number of times a part is removed and replaced to a maximum of two. Preheat the substrate for about 30 minutes to about 95 C. Use an appropriate attachment to direct the flow of hot air to the component to be removed or replaced. Minimize the heat time to reduce the device exposure to high temperatures. References 1. Ray P. Prasad; Surface Mount Technology - Principles and Practice; Van Nostrand Reinhold New York; 1989; Pages Ahmer Syed and WonJoon Kang; Board level assembly and reliability considerations for QFN type packages; Amkor Technology, Inc Charles Harper; Electronic Packaging and Interconnect Handbook; Solder Technologies for Electronic Packaging Assembly ; McGraw-Hill 2000; Pages JEDEC Standard J-STD-020B. Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices. July IPC-7525, Stencil Design Guidelines 7. IPC-SM-782, Surface Mount Design and Land Pattern Standard Summary This application note addressed some of the guidelines for the QFN mounting processes and discussed the optimum PCB and stencil layout details. It is no longer necessary to compromise performance to achieve minimal cost and small implementation area. February 9, 2011 Document No Rev. *A 12

13 Document History Page Document Title: Optimum PCB and Stencil Layout for Wireless USB QFN Package Document Number: Revision ECN Orig. of Change Submission Date Description of Change ** NXZ 11/27/2007 New application note. *A NXZ 02/04/2011 Template udpates. Wireless USB is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions. Cypress Semiconductor 198 Champion Court San Jose, CA Phone: Fax: Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. February 9, 2011 Document No Rev. *A 13