PRACE PATC Course Intel MIC Programming Workshop. June, 26-28, 2017, LRZ
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1 PRACE PATC Course Intel MIC Programming Workshop June, 26-28, 2017, LRZ
2 LRZ in the HPC Environment Bavarian Contribution to National Infrastructure German Contribution to European Infrastructure PRACE has 25 members, representing European Union Member States and Associated Countries Intel MIC Programming LRZ
3 PATC Courses Advanced Training Centre (PATC) Courses LRZ is part of the Gauss Centre for Supercomputing (GCS), which is one of the six PRACE Advanced Training Centres (PATCs) that started in 2012: Barcelona Supercomputing Center (Spain), CINECA Consorzio Interuniversitario (Italy) CSC IT Center for Science Ltd (Finland) EPCC at the University of Edinburgh (UK) Gauss Centre for Supercomputing (Germany) Maison de la Simulation (France) Mission: Serve as European hubs and key drivers of advanced high-quality training for researchers working in the computational sciences Intel MIC Programming LRZ
4 Tentative Agenda: Monday Monday, June 26, 2017, Kursraum 2, H.U.010 (course room) 09:00-10:00 Welcome & Introduction (Weinberg) 10:00-10:30 Overview of the Intel MIC architecture (Allalen) 10:30-11:00 Coffee break 11:00-11:30 Overview of the Intel MIC programming models (Allalen) 11:30-12:00 Native mode KNC and KNL programming (Allalen) 12:00-13:00 Lunch break 13:00-14:00 KNL Memory Modes and Cluster Modes, MCDRAM (Weinberg) 14:00-15:30 Offloading (Weinberg) 15:30-16:00 Coffee break 16:00-17:00 MKL (Allalen)
5 Tentative Agenda: Tuesday Tuesday, June 27, 2017, Kursraum 2, H.U.010 (course room) 09:00-10:30 Vectorisation and Intel Xeon Phi performance optimisation (Allalen) 10:30-11:00 Coffee break 11:00-12:00 Guided SuperMUC/MIC Tour (Weinberg/Allalen) 12:00-13:00 Lunch break 13:00-15:30 KNL code optimisation process (Baruffa) 15:30-16:00 Coffee Break 16:00-17:00 Profiling tools: Intel Advisor (Baruffa) 18:00 - open end at GARNIX
6 Tentative Agenda: Wednesday Wednesday, June 28, 2017, 09:00-12:00, Hörsaal, H.E.009 (Lecture Hall) 09:00-10:30 Many-core Programming with OpenMP 4.x (Michael Klemm, Intel) 10:30-10:45 Coffee Break 10:45-12:00 Advanced KNL programming techniques (Intrinsics, Assembler, AVX- 512,...) (Jan Eitzinger, RRZE) 12:00-13:00 Lunch Break
7 Tentative Agenda: Wednesday Wednesday, June 28, 2017, 13:00-18:00, Hörsaal, H.E.009 (Lecture Hall) Plenum session with invited talks on MIC experience and best practice recommendations (joint session with the Scientific Workshop "HPC for natural hazard assessment and disaster mitigation"), public session 13:00-13:30 Luigi Iapichino, "Performance Optimization of Smoothed Particle Hydrodynamics and Experiences on Many-Core Architectures" 13:30-14:00 Michael Bader/Carsten Uphoff, "Extreme-scale Multi-physics Simulation of the 2004 Sumatra Earthquake" 14:00-14:30 Vit Vondrak/Branislav Jansik, "Development of Intel Xeon Phi Accelerated Algorithms and Applications at IT4I" 14:30-15:00 Michael Klemm, Intel: "Application Show Cases on Intel Xeon Phi Processors" 15:00-15:30 Coffee Break 15:30-16:00 Jan Eitzinger, RRZE: "Evaluation of Intel Xeon Phi "Knights Landing": Initial impressions and benchmarking results" 16:00-16:30 Piotr Korcyl, University of Regensburg: "Lattice Quantum Chromodynamics on the MIC architectures" 16:30-17:00 Nils Moschüring, IPP: "The experience of the HLST on Europes biggest KNL cluster" 17:00-17:30 Andreas Marek, Max Planck Computing and Data Facility (MPCDF), "Porting the ELPA library to the KNL architecture" 17:30-18:00 Q&A, Wrap-up
8 Information Lecturers: Dr. Momme Allalen, Dr. Fabio Baruffa, Dr. Volker Weinberg (LRZ) Dr.-Ing. Jan Eitzinger (RRZE) Dr.-Ing. Michael Klemm (Intel Corp.) Complete lecture slides & exercise sheets: workshop_2017/ Examples under: /lrz/sys/courses/mic_workshop
9 Intel Xeon LRZ and EU
10 Intel Xeon Phi and GPU LRZ LRZ (PATC): KNC+GPU LRZ (PATC): KNC+GPU IT4Innovations: KNC LRZ (PATC): KNC+KNL PRACE Seasonal School, Hagenberg: KNC IT4Innovations (PATC): KNC LRZ (PATC): KNL June LRZ (PATC tbc.): KNL inside, Vol. 12, No. 2, p. 102, 2014 inside, Vol. 13, No. 2, p. 79, 2015 inside, Vol. 14, No. 1, p. 76f, 2016 inside, Vol. 14, No. 2, p. 25ff, 2016 inside, Vol. 15, No. 1, p. 48ff, Intel MIC Programming LRZ
11 Evaluating Accelerators at LRZ Research at LRZ within PRACE & KONWIHR: CELL programming Evaluation of CELL programming. IBM announced to discontinue CELL in Nov GPGPU programming Regular GPGPU computing courses at LRZ since Evaluation of GPGPU programming languages: CAPS HMPP PGI accelerator compiler CUDA, cublas, cufft PyCUDA/R Intel Xeon Phi programming Larrabee (2009) Knights Ferry (2010) Knights Corner Intel Xeon Phi (2012) KNL (2016) } OpenACC, OpenMP 4.x
12 IPCC (Intel Parallel Computing Centre) New Intel Parallel Computing Centre (IPCC) since July 2014: Extreme Scaling on MIC/x86 Chair of Scientific Computing at the Department of Informatics in the Technische Universität München (TUM) & LRZ Codes: Simulation of Dynamic Ruptures and Seismic Motion in Complex Domains: SeisSol Numerical Simulation of Cosmological Structure Formation: GADGET Molecular Dynamics Simulation for Chemical Engineering: ls1 mardyn Data Mining in High Dimensional Domains Using Sparse Grids: SG++
13 CzeBaCCA Project Czech-Bavarian Competence Team for Supercomputing Applications (CzeBaCCA) New BMBF funded project that started in Jan to: Foster Czech-German Collaboration in Simulation Supercomputing series of workshops will initiate and deepen collaboration between Czech and German computational scientists Establish Well-Trained Supercomputing Communities joint training program will extend and improve trainings on both sides Improve Simulation Software establish and disseminate role models and best practices of simulation software in supercomputing Intel MIC Programming LRZ
14 CzeBaCCA Trainings and Workshops Intel MIC Programming Workshop, 3 4 February 2016, Ostrava, Czech Republic Scientific Workshop: SeisMIC - Seismic Simulation on Current and Future Supercomputers, 5 February 2016, Ostrava, Czech Republic PRACE PATC Course: Intel MIC Programming Workshop, June 2016, Garching, Germany Scientific Workshop: High Performance Computing for Water Related Hazards, 29 June - 1 July 2016, Garching, Germany PRACE PATC Course: Intel MIC Programming Workshop, 7 8 February 2017, Ostrava, Czech Republic Scientific Workshop: High performance computing in atmosphere modelling and air related environmental hazards, 9 February 2017, Ostrava, Czech Republic PRACE PATC Course: Intel MIC Programming Workshop, June 2017, Garching, Germany Scientific Workshop: HPC for natural hazard assessment and disaster migration, June 2017, Garching, Germany
15 CzeBaCCA Trainings and Workshops 1st workshop series: February IT4I inside, Vol. 14, No. 1, p. 76f, p Intel MIC Programming LRZ
16 CzeBaCCA Trainings and Workshops 2nd workshop series: June LRZ inside, Vol. 14, No. 2, p. 25ff, p Intel MIC Programming LRZ
17 CzeBaCCA Trainings and Workshops 3rd workshop series: February IT4I inside, Vol. 15, No. 1, p. 48ff, p Intel MIC Programming LRZ
18 Intel Xeon Top500 June #2: Tianhe-2 (MilkyWay-2) - TH-IVB-FEP Cluster, Intel Xeon E C 2.200GHz, TH Express-2, Intel Xeon Phi 31S1P, National Super Computer Center in Guangzhou, China #6: Cori - Cray XC40, Intel Xeon Phi C 1.4GHz, Aries interconnect, Cray Inc., DOE/SC/LBNL/NERSC, United States #7: Oakforest-PACS - PRIMERGY CX1640 M1, Intel Xeon Phi C 1.4GHz, Intel Omni-Path, Fujitsu, Joint Center for Advanced High Performance Computing, Japan #12:Stampede2 - PowerEdge C6320P, Intel Xeon Phi C 1.4GHz, Intel Omni-Path, Dell, Texas Advanced Computing Center/Univ. of Texas, United States #14: Marconi, Intel Xeon Phi - CINECA Cluster, Intel Xeon Phi C 1.4GHz, Intel Omni-Path, Lenovo, CINECA, Italy several non European systems #78: Salomon - SGI ICE X, Xeon E5-2680v3 12C 2.5GHz, Infiniband FDR, Intel Xeon Phi 7120P, HPE, IT4Innovations National Supercomputing Center, VSB- Technical University of Ostrava, Czech Republic
19 PRACE: Best Practice Guides
20 Best Practice Guides - Overview The following 4 Best Practice Guides (BPGs) have been written within PRACE-4IP by 13 authors from 8 institutions and have been published in pdf and html format in January 2017 on the PRACE website: Intel Xeon Phi BPG Update of the PRACE-3IP BPG Haswell/Broadwell BPG Written from scratch Knights Landing BPG Written from scratch GPGPU BPG Update of the PRACE-2IP mini-guide Online under:
21 Intel MIC within PRACE: Intel Xeon Phi (KNC) Best Practice Guide Created within PRACE-3IP+4IP. Written in Docbook XML. 122 pages, 13 authors Now including information about existing Xeon Phi based systems in Europe: BAS (NCSA), BSC, LRZ Practice-Guide-Intel-Xeon-Phi-1.pdf
22 Intel MIC within PRACE: Knights Landing Best Practice Guide Created within PRACE-4IP. Written in Docbook XML. 85 pages, 3 authors General information about the KNL architecture and programming environment Benchmark & Application Performance results Practice-Guide-Knights-Landing.pdf
23 Best Practice Guides - Dissemination
24 SuperMIC LRZ
25 SuperMUC System Overview
26 SuperMUC Phase 2: Moving to Haswell LRZ infrastructure (NAS, Archive, Visualization) Internet / Grid Services pruned tree Spine infiniband switches pruned tree Mellanox FDR14 Island switch GPFS for $WORK $SCRATCH Mellanox FDR10 Island switch non blocking Haswell-EP 24 cores/node 2.67 GB/core I/O servers non blocking Thin + Fat islands of SuperMC 6 Haswell islands 512 nodes per island warm water cooling I/O Servers (weak coupling of phases 1+2)
27 SuperMUC Phase 2: Moving to Haswell
28 SuperMIC: Intel Xeon Phi Cluster
29 SuperMIC: Intel Xeon Phi Cluster
30 SuperMIC LRZ 32 compute nodes (diskless) SLES11 SP3 2 Ivy-Bridge host processors E5-2650@2.6 GHz with 16 cores 2 Intel Xeon Phi 5110P coprocessors per node with 60 cores 64 GB (Host) + 2 * 8 GB (Xeon Phi) memory 2 MLNX CX3 FDR PCIe cards attached to each CPU socket Interconnect Mellanox Infiniband FDR14 Through Bridge Interface all nodes and MICs are directly accessible 1 Login- and 1 Management-Server (Batch-System, xcat, ) Air-cooled Supports both native and offload mode Batch-system: LoadLeveler
31 SuperMIC Network Access
32 SuperMIC Access Description of SuperMIC: Training Login Information: aining-login/ Use course account on paper snippets
33 KNL Testsystem First login to Linux-Cluster (directly reachable from the course PCs, use only account a2c06aa!): ssh lxlogin1.lrz.de l a2c06aa Then: ssh mcct03.cos.lrz.de or ssh mcct04.cos.lrz.de Processor: Intel(R) Xeon Phi(TM) CPU cores, 4 threads per core. Frequency: GHz KNL: 64 cores x 1.3 GHz x 8 (SIMD) x 2 x 2 (FMA) = GFLOP/s Compare with: KNC: 60 cores x 1 GHz x 8 (SIMD) x 2 (FMA) = 960 GFLOP/s Sandy-Bridge: 2 sockets x 8 cores x 2.7 GHz x 4 (SIMD) x 2 (ALUs) = GFLOP/s
34 Xeon Phi References Books: James Reinders, James Jeffers, Intel Xeon Phi Coprocessor High Performance Programming, Morgan Kaufman Publ. Inc., ; new KNL edition in July 2016 Rezaur Rahman: Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers, Apress Parallel Programming and Optimization with Intel Xeon Phi Coprocessors, Colfax Training material by CAPS, TACC, EPCC Intel Training Material and Webinars V. Weinberg (Editor) et al., Best Practice Guide - Intel Xeon Phi v2, and references therein Ole Widar Saastad (Editor) et al., Best Practice Guide Knights Landing,
35 Acknowledgements IT4Innovation, Ostrava. Partnership for Advanced Computing in Europe (PRACE) Intel BMBF (Federal Ministry of Education and Research) Dr. Karl Fürlinger (LMU) J. Cazes, R. Evans, K. Milfeld, C. Proctor (TACC) Adrian Jackson (EPCC) Intel MIC Programming LRZ
36 And now Enjoy the course!
PRACE PATC Course Intel MIC Programming Workshop. February, 7-8, 2017, IT4Innovations, Ostrava, Czech Republic
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