Fujitsu Microelectronics Europe User Guide FMEMCU-UG FR60 FAMILY ADAPTER BOARD EMA-MB91V460A-300 USER GUIDE

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1 Fujitsu Microelectronics Europe User Guide FR60 FAMILY ADAPTER BOARD EMA-MB91V460A-300 USER GUIDE

2 Revision History Revision History Date Issue V1.00, RH/AW/MB, First Release V1.01, OGL, several updates, format changes V1.02, China RoHS note added V1.1, OGL, several updates V1.2, OGL, new chapter V1.3, CEy, Restructuring of chapters and additional content (e.g. jumper configuration, connector pin assignments,...) Latest product revision: 1.2 Latest schematic revision: 2.2 Latest PCB revision: 2.0 This document contains 31 pages Fujitsu Microelectronics Europe GmbH

3 Warranty and Disclaimer EMA-MB91V460A-300 Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for the EMA-MB91V460A-300 Board and all its deliverables (eg. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, the EMA-MB91V460A-300 Board and all its deliverables are intended and must only be used in an evaluation laboratory environment. 1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. 2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH s entire liability and the customer s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH. 3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated. 4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH s and its supplier s liability are restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect Fujitsu Microelectronics Europe GmbH - 3 -

4 Contents 0 Contents REVISION HISTORY... 2 WARRANTY AND DISCLAIMER CONTENTS OVERVIEW Abstract General Description INSTALLATION SWITCHES AND JUMPERS Switch FPGA control (S200) FPGA chip select configuration FPGA APIX transmission line configuration EEPROM programming mode Jumpers DREQ DEOT0# DREQ DEOT1# APIX Transaction Buffer Interrupt APIX Event Interrupt Location of the components CONNECTORS APIX Main Link (CON500, CON501, CON503) APIX Sideband Link (CON301) Date code and older Date code External video input (CON502, CON600) FPGA configuration (CON400) STATUS LEDS LED overview (D300 D302, D400) APIX mode FPGA configuration MCU EXTERNAL BUS SETTINGS Fujitsu Microelectronics Europe GmbH

5 Contents 7 FPGA BIT IMAGE UPDATE Required Xilinx Tools Required Hardware Setup Xilinx impact Project Setup Xilinx impact FPGA bit image program procedure MECHANICAL DIMENSIONS INFORMATION IN THE CHINA-ROHS REGULATION RECYCLING Fujitsu Microelectronics Europe GmbH - 5 -

6 Chapter 1 Overview 1 Overview 1.1 Abstract The EMA-MB91V460A-300 in combination with the EMA-MB91V460A-002B/-80/003 and a socket adapter board EMA-MB91F46x-LS/NLS-xxx is a development system for the Fujitsu FR60 MB91V460 Flash microcontroller. This board must only be used for test applications in an evaluation laboratory environment. Before using the EMA-MB91V460A-300 adapter board, make sure that the following packed components have been delivered: o 1 pcs. EMA-MB91V460A-300 board o 1 pcs. User Guide Fujitsu Microelectronics Europe GmbH

1.2 General Description EMA-MB91V460A-300 Chapter 1 Overview The EMA-MB91V460A-300 board extends the current MB91460 series emulation system with an APIX differential main and sideband link interface

7 1.2 General Description EMA-MB91V460A-300 Chapter 1 Overview The EMA-MB91V460A-300 board extends the current MB91460 series emulation system with an APIX differential main and sideband link interface emulation. This board holds the required Remote Handler and ASHELL hardware implemented into an FPGA. Additionally two Inova Semiconductor INAP125T24 ASSP are mounted to provide a physical link interface to the receiver. The physical link connection to the receiver (Indigo) is established via a CAT5 RJ45 Ethernet cable. Figure 1-1: Block Diagram The FPGA board has to be connected to a MB91V460A-002B/-80/-003 board. The Remote Handler register set is mapped via external bus connection into the memory mapped external bus area of the microcontroller during emulation. Upcoming restrictions and differences between emulation system and standalone Flash microcontroller are specified in following appnote: mcu-an e-vxx_mb91f467s_emulation.pdf The user can select between following signal connections to an external receiver: PHY connection via RJ45 connector on EMA-MB91V460A-300 Sideband connection via connectors on EMA-MB91V460A-300 PHY connection and signal routing via socket adapter to target HW Sideband connection signal routing via socket adapter to target HW Fujitsu Microelectronics Europe GmbH - 7 -

8 Chapter 2 Installation 2 Installation Remove carefully the EMA-MB91V460A-300 board from the shipping carton and check if there are any damages. Please refer to the attached document NQPACK/ YQPACK/ HQPACK Technical Information for installation of the socket adapter. Figure 2-1: Installation Fujitsu Microelectronics Europe GmbH

9 3 Switches and Jumpers EMA-MB91V460A-300 Chapter 3 Switches and Jumpers This chapter describes all switches and jumpers that can be modified or accessed on the EMA-MB91V460A-300 board. The default setting is shown with a grey shaded area. 3.1 Switch FPGA control (S200) Switch Description / Function Type Default S200-1 DIP-Switch OFF S200-2 DIP-Switch ON S200-3 Selection of FPGA chip select DIP-Switch ON S200-4 DIP-Switch OFF S200-5 APIX Mode DIP-Switch OFF S200-6 DIP-Switch OFF S200-7 DIP-Switch OFF S200-8 DIP-Switch OFF S200-9 DIP-Switch OFF S EEPROM programming mode DIP-Switch OFF FPGA chip select configuration The configuration of the chip select that is used to access the FPGA via the MCU has to be set accordingly. Be sure the settings below match the settings for the MCU external bus chip select, which are used for accessing the FPGA via the memory mapped external bus area. S200-2 S200-3 S200-4 Chip Select OFF OFF OFF CS0 ON OFF OFF CS1 OFF ON OFF CS2 ON ON OFF CS3 OFF OFF ON CS4 ON OFF ON CS5 OFF ON ON CS6 ON ON ON CS7 Default: S200-2: ON, S200-3: ON, S200-4: OFF Fujitsu Microelectronics Europe GmbH - 9 -

10 Chapter 3 Switches and Jumpers FPGA APIX transmission line configuration The configuration of the physical APIX transmission line is selected via DIP-Switch. Two different transmission lines can be selected, PHY and Interconnect TTL. S200-5 Configuration ON OFF Default: S200-5: ON APIX interconnection TTL selected APIX PHY selected If transmission line APIX PHY is selected, the FPGA APIX in/output signals are routed to the INAP125T24 PHY transceiver and the remote connector CON500 as differential signals. If transmission line APIX interconnection TTL is selected, the FPGA APIX in/output signals are routed to remote connector CON301 as TTL signals EEPROM programming mode To modify the INAP125T24 configuration EEPROM, it is required to switch into a special mode for programming. Within the EEPROM programming mode, no APIX functionality is available. S Configuration OFF ON Default: S200-10: OFF APIX run mode INAP125T24 EEPROM programming mode To program the EEPROM, a dedicated Softune Workbench project (EMA-MB91V460A- 300_EEPROM_APIX_INAP125T) is required Fujitsu Microelectronics Europe GmbH

11 Chapter 3 Switches and Jumpers 3.2 Jumpers Jumper Description / Function Default J200 FPGA DREQ0 MB91V460 DREQ0 Closed J201 FPGA DEOT0# MB91V460 DEOT0# Closed J202 FPGA DREQ1 MB91V460 DREQ1 Closed J203 FPGA DEOT1# MB91V460 DEOT1# Closed J204 Open J205 Open J206 Open J207 Open J208 Open J209 APIX Transaction Buffer IRQ MB91V460 INT13 Closed J210 Open J211 APIX Event IRQ MB91V460 INT15 Closed DREQ0 Jumper Setting Description Open DREQ0 of APIX FPGA is not connected to DREQ0 of MB91V460 J200 Closed DREQ0 of APIX FPGA is connected to DREQ0 of MB91V460 Default: J200 closed DEOT0# Jumper Setting Description Open DEOT0# of APIX FPGA is not connected to DEOT0# of MB91V460 J201 Closed DEOT0# of APIX FPGA is connected to DEOT0# of MB91V460 Default: J201 closed DREQ1 Jumper Setting Description Open DREQ1 of APIX FPGA is not connected to DREQ1 of MB91V460 J202 Closed DREQ1 of APIX FPGA is connected to DREQ1 of MB91V460 Default: J202 closed Fujitsu Microelectronics Europe GmbH

12 Chapter 3 Switches and Jumpers DEOT1# Jumper Setting Description Open DEOT1# of APIX FPGA is not connected to DEOT1# of MB91V460 J203 Closed DEOT1# of APIX FPGA is connected to DEOT1# of MB91V460 Default: J203 closed APIX Transaction Buffer Interrupt Jumper Setting Description J209 Default: J209 closed Open Closed APIX Transaction Buffer IRQ is not connected to INT13 of MB91V460 APIX Transaction Buffer IRQ is connected to INT13 of MB91V APIX Event Interrupt Jumper Setting Description Open APIX Event IRQ is not connected to INT15 of MB91V460 J211 Closed APIX Event IRQ is connected to INT15 of MB91V460 Default: J211 closed Fujitsu Microelectronics Europe GmbH

13 3.3 Location of the components EMA-MB91V460A-300 Chapter 3 Switches and Jumpers Following figures show the location of the described parts on the PCB. The default jumper and switch settings are marked accordingly. Figure 3-1: Location of components, top side Fujitsu Microelectronics Europe GmbH

14 Chapter 3 Switches and Jumpers Figure 3-2: Location of components, bottom side Fujitsu Microelectronics Europe GmbH

15 Chapter 4 Connectors 4 Connectors 4.1 APIX Main Link (CON500, CON501, CON503) For connection of APIX main, high bandwidth, differential signal link. To connect APIX emulation board to receiver like Indigo or MB88F332. CON500 pin CON501 pin CON503 pin Rxxx 1 Name R528 APIX0_SDOUT_P R527 APIX0_SDOUT_M 3-1 R628 (APIX1_SDOUT_P) R526 APIX0_SDIN_P R525 APIX0_SDIN_M 6-2 R627 (APIX1_SDOUT_M) R626 (APIX1_SDIN_P) R625 (APIX1_SDIN_M) 2 1 If you want to route a signal to the bottom-side connectors of the EMA-MB91V460A-300, assemble the board with appropriate 0Ω resistors (or make solder connections). However, it is not recommended to route the APIX Main Link signals to the bottom-side connectors. Please refer also to Userguide of EMA-MB91F467S-LS-176M07 for further necessary settings on that board ² Signal not available Fujitsu Microelectronics Europe GmbH

16 4.2 APIX Sideband Link (CON301) EMA-MB91V460A-300 Chapter 4 Connectors For connection of APIX sideband, low bandwidth, non differential signal link. To connect APIX emulation board to receiver like Jade-D via non-differential link. The pin assignment differs between the various FPGA Module IDs Date code and older Applying to the following Module IDs: 0x , 0x , 0x , 0x , 0x , 0x , 0x CON301 pin Rxxx 1 I/O Name 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, GND 1 R310 - (RCK0)² 3 R311 In RDA01 5 R308 In RDA (TCK1)² 9 R306 - (TDA11)² 11 R307 - (TDA12)² 13 R309 Out(!) TCK0 15 R312 Out TDA01 17 R313 Out TDA (RCK1)² (RDA11)² (RDA12)² 1 Routing to bottom-side connectors not recommended due to wrong pin assignments ² Signal not available Fujitsu Microelectronics Europe GmbH

17 Chapter 4 Connectors Date code Applying to the following Module ID: 0x CON301 pin Rxxx 1 I/O Name 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 - GND 1 R310 In(!) TCK0 3 R311 Out TDA01 5 R308 Out TDA (TCK1)² 9 R306 (TDA11)² 11 R307 (TDA12)² 13 R309 In RCK0 15 R312 In RDA01 17 R313 In RDA (RCK1)² 21 - (RDA11)² 23 - (RDA12)² 1 If you want to route a signal to the bottom-side connectors of the EMA-MB91V460A-300 assemble the board with appropriate 0Ω resistors (or make solder connections).please refer also to Userguide of EMA-MB91F467S- LS-176M07 for further necessary settings on that board ² Signal not available Fujitsu Microelectronics Europe GmbH

18 Chapter 4 Connectors 4.3 External video input (CON502, CON600) To supply APIX main, high bandwidth, differential signal link with pixel data. CON502 / CON600 pin CON502 Name CON600 Name 1, 2, 39, 40 GND GND 19, 20, 21, 22 VDD3 VDD3 3, 4, 11, 12, 23, 24, 35, 37, 38 Not connected Not connected 5 PX0_DATA18 PX1_DATA18 6 PX0_DATA19 PX1_DATA19 7 PX0_DATA20 PX1_DATA20 8 PX0_DATA21 PX1_DATA21 9 PX0_DATA22 PX1_DATA22 10 PX0_DATA23 PX1_DATA23 13 PX0_DATA10 PX1_DATA10 14 PX0_DATA11 PX1_DATA11 15 PX0_DATA12 PX1_DATA12 16 PX0_DATA13 PX1_DATA13 17 PX0_DATA14 PX1_DATA14 18 PX0_DATA15 PX1_DATA15 25 PX0_DATA2 PX1_DATA2 26 PX0_DATA3 PX1_DATA3 27 PX0_DATA4 PX1_DATA4 28 PX0_DATA5 PX1_DATA5 29 PX0_DATA6 PX1_DATA6 30 PX0_DATA7 PX1_DATA7 31 PX0_CTRL0 PX1_CTRL0 32 PX0_CTRL1 PX1_CTRL1 33, 34 PX0_CTRL2 PX1_CTRL2 36 PX0_CLK PX1_CLK Fujitsu Microelectronics Europe GmbH

19 4.4 FPGA configuration (CON400) EMA-MB91V460A-300 Chapter 4 Connectors The configuration memory of the FPGA is re-configurable by programming via CON400. Please refer to for details and tools for Xilinx FPGA configuration. CON400 pin Name 1,3,5,7,9,11,13 GND 2 VDD3 4 TMS 6 TCK 8 TDO 10 TDI Fujitsu Microelectronics Europe GmbH

20 Chapter 5 Status LEDs 5 Status LEDs 5.1 LED overview (D300 D302, D400) LED D300 D301 D302 D400 Description / Function APIX mode Not used (LED = ON) Not used (LED = OFF) FPGA configuration APIX mode D300 Description OFF APIX PHY selected ON APIX interconnection TTL selected Default: D300: OFF FPGA configuration D400 Description OFF FPGA is being configured ON FPGA successfully configured Default: D400: ON Fujitsu Microelectronics Europe GmbH

21 6 MCU external bus settings EMA-MB91V460A-300 Chapter 6 MCU external bus settings To guarantee stable and secure function of the FPGA system, be sure to use the following settings for the Microcontroller bus interface configuration. Be sure to configure and enable the corresponding chip select which has been selected on DIP S200-[2...4] at the FPGA board. Following settings have to be applied: #set CONFIGCSx B' #set WAITREGx B' Ensure the external bus frequency is set to 20MHz! Fujitsu Microelectronics Europe GmbH

1 Required Xilinx Tools 1) Xilinx Platform Cable USB Figure 7-1: Xilinx Platform Cable USB 2) Xilinx impact Programming Software

22 7 FPGA Bit Image Update EMA-MB91V460A-300 Chapter 7 FPGA Bit Image Update If updating of FPGA bit image is required, please follow the procedure below and make sure that all required Xilinx programming tools are installed and available. 7.1 Required Xilinx Tools 1) Xilinx Platform Cable USB Figure 7-1: Xilinx Platform Cable USB 2) Xilinx impact Programming Software Release Version 9.2i Application Version J Required Hardware Setup Figure 7-2: FPGA programming HW Setup Fujitsu Microelectronics Europe GmbH

23 7.3 Xilinx impact Project Setup EMA-MB91V460A-300 Chapter 7 FPGA Bit Image Update 1. Start impact Within the impact project dialog select: create a new project Select a suitable position on the harddrive via the Browse button. 2. Configure JTAG chain Within the impact welcome to impact dialog, asure the settings in the picture below and click the Finish button 3. Scanning process Wait until JTAG scanning process is finished! Fujitsu Microelectronics Europe GmbH

appears. Click: Cancel button Click: Cancel button 5.

24 4. 1 st and 2 nd Assign Configuration file EMA-MB91V460A-300 Chapter 7 FPGA Bit Image Update Wait until first window Assign New Configuration File appears. Click: Cancel button Click: Cancel button 5. Save Project Save the new impact project! (File Save Project) Fujitsu Microelectronics Europe GmbH

Assign New Configuration file Select FPGA bit image file to be programmed (e.g. mcu_tx_rh_21012008_rev2.

25 Chapter 7 FPGA Bit Image Update 7.4 Xilinx impact FPGA bit image program procedure 1. Start Xilinx impact 2. Load impact project 3. Select FPGA bit image file Right Click on Symbol xcf04s and select Assign New Configuration File 4. Assign New Configuration file Select FPGA bit image file to be programmed (e.g. mcu_tx_rh_ _rev2.mcs) Click Open button 5. Start Programming FPGA bit image file Right Click on Symbol xcf04s and select Program Fujitsu Microelectronics Europe GmbH

26 Chapter 7 FPGA Bit Image Update Ensure the following settings below! Clock OK button. 6. Programming process Wait until program process is finished with Program success Fujitsu Microelectronics Europe GmbH

27 8 Mechanical Dimensions EMA-MB91V460A-300 Chapter 8 Mechanical Dimensions 109, Ø2,70 Ø2,70 Top view Ø2,70 Ø2, Figure 8-1: Mechanical dimensions Fujitsu Microelectronics Europe GmbH

28 9 Information in the WWW EMA-MB91V460A-300 Chapter 9 Information in the WWW Information about FUJITSU MICROELECTRONICS Products can be found on the following Internet pages: Microcontrollers (8-, 16- and 32bit), Graphics Controllers Datasheets and Hardware Manuals, Support Tools (Hard- and Software) Linear Products: Power Management, A/D and D/A Converters Media Products: SAW filters, acoustic resonators and VCOs For more information about FUJITUS MICROELECTRONICS Fujitsu Microelectronics Europe GmbH

29 10 China-RoHS regulation EMA-MB91V460A-300 Chapter 10 China-RoHS regulation Evaluation Board 评估板 Emulation Board 仿真板根据 SJ/T 电子信息产品污染控制标识要求特提供如下有关污染控制方面的信息 The following product pollution control information is provided according to SJ/T Marking for Control of Pollution caused by Electronic Information Products. 1. 电子信息产品污染控制标志说明 Explanation of Pollution Control Label 该标志表明本产品含有超过中国标准 SJ/T 电子信息产品中有毒有害物质的限量要求中限量的有毒有害物质标志中的数字为本产品的环保使用期, 表明本产品在正常使用的条件下, 有毒有害物质不会发生外泄或突变, 用户使用本产品不会对环境造成严重污染或对其人身财产造成严重损害的期限, 单位为年为保证所申明的环保使用期限, 应按产品手册中所规定的环境条件和方法进行正常使用, 并严格遵守产品维修手册中规定的定期维修和保养要求产品中的消耗件和某些零部件可能有其单独的环保使用期限标志, 并且其环保使用期限有可能比整个产品本身的环保使用期限短应到期按产品维修程序更换那些消耗件和零部件, 以保证所申明的整个产品的环保使用期限本产品在使用寿命结束时不可作为普通生活垃圾处理, 应被单独收集妥善处理请注意 : 环保使用期限 50 年的指定不是与产品的耐久力, 使用期限或任何担保要求等同的 This symbol to be added to all EIO sold to China, indicates the product contains hazardous materials in excess of the limits established by the Chinese standard SJ/T Requirements for Concentration Limits for Certain Hazardous Substances in Electronic Information Products. The number in the symbol is the Environment-friendly Use Period (EFUP), which indicates the period, starting from the manufacturing date, during which the toxic or hazardous substances or elements contained in electronic information products will not leak or mutate under normal operating conditions so that the use of such electronic information products will not result in any severe environmental pollution, any bodily injury or damage to any assets, the unit of the period is Year. Fujitsu Microelectronics Europe GmbH

30 Chapter 10 China-RoHS regulation In order to maintain the declared EFUP, the product shall be operated normally according to the instructions and environmental conditions as defined in the product manual, and periodic maintenance schedules specified in Product Maintenance Procedures shall be followed strictly. Consumables or certain parts may have their own label with an EFUP value less than the product. Periodic replacement of those consumables or parts to maintain the declared EFUP shall be done in accordance with the Product Maintenance Procedures. This product must not be disposed of as unsorted municipal waste, and must be collected separately and handled properly after decommissioning. Please note: The designation of 10 years EFUP is not to be equated with the durability, useduration or any warranty-claims of the product. 产品中有毒有害物质或元素的名称及含量 Table of hazardous substances name and concentration 有毒有害物质或元素部件名称 EMA-MB91V460A-300 Hazardous substances name 铅汞镉六价铬多溴联苯多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) x o o o o o O: 表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ/T 标准规定的限量要求以下 X: 表示该有毒有害物质至少在该部件的某一均质材料中的含量超出 SJ/T 标准规定的限量要求此表所列数据为发布时所能获得的最佳信息由于缺少经济上或技术上合理可行的替代物质或方案, 此医疗设备运用以上一些有毒有害物质来实现设备的预期临床功能, 或给人员或环境提供更好的保护效果 O: Indicates that this toxic or hazardous substance contained in all of the homogeneous materials for this part is below the limit requirement in SJ/T X: Indicates that this toxic or hazardous substance contained in at least one of the homogeneous materials used for this part is above the limit requirement in SJ/T Data listed in the table represents best information available at the time of publication Fujitsu Microelectronics Europe GmbH

31 Chapter 11 Recycling 11 Recycling Gültig für EU-Länder: Gemäß der Europäischen WEEE-Richtlinie und deren Umsetzung in landesspezifische Gesetze nehmen wir dieses Gerät wieder zurück. Zur Entsorgung schicken Sie das Gerät bitte an die folgende Adresse: Fujitsu Microelectronics Europe GmbH Warehouse Monzastraße 4a Langen Valid for European Union Countries: According to the European WEEE-Directive and its implementation into national laws we take this device back. For disposal please send the device to the following address: Fujitsu Microelectronics Europe GmbH Warehouse Monzastraße 4a Langen Fujitsu Microelectronics Europe GmbH

EMA-MB91F467D-NLS-208M04

Fujitsu Microelectronics Europe User Guide FR60 FAMILY SOCKET ADAPTER BOARD EMA-MB91F467D-NLS-208M04 USER GUIDE Revision History Revision History Date Issue 01.08.2006 V1.00, RH/AW, First Release 08.02.2007