Data Sheet FEATURES Very low voltage noise: nv/ Hz maximum at 00 Hz Excellent current gain match: 0.5% typical Low offset voltage (VOS): 200 μv maximum Outstanding offset voltage drift: 0.03 μv/ C typical High gain bandwidth product: 200 MHz Audio, Dual-Matched NPN Transistor MAT2 PIN CONFIGURATION C 6 C 2 B 2 5 B 2 E 3 4 E 2 NOTE. SUBSTRATE IS CONNECTED TO CASE ON TO-78 PACKAGE. 2. SUBSTRATE IS NORMALLY CONNECTED TO THE MOST NEGATIVE CIRCUIT POTENTIAL, BUT CAN BE FLOATED. Figure. 6-Lead TO-78 09044-00 GENERAL DESCRIPTION The MAT2 is a dual, NPN-matched transistor pair that is specifically designed to meet the requirements of ultralow noise audio systems. With its extremely low input base spreading resistance (rbb' is typically 28 Ω) and high current gain (hfe typically exceeds 600 at IC = ma), the MAT2 can achieve outstanding signalto-noise ratios. The high current gain results in superior performance compared to systems incorporating commercially available monolithic amplifiers. Excellent matching of the current gain (ΔhFE) to about 0.5% and low VOS of less than 0 μv typical make the MAT2 ideal for symmetrically balanced designs, which reduce high-order amplifier harmonic distortion. Stability of the matching parameters is guaranteed by protection diodes across the base emitter junction. These diodes prevent degradation of beta and matching characteristics due to reverse biasing of the base emitter junction. The MAT2 is also an ideal choice for accurate and reliable current biasing and mirroring circuits. Furthermore, because the accuracy of a current mirror degrades exponentially with mismatches of VBE between transistor pairs, the low VOS of the MAT2 does not need offset trimming in most circuit applications. The MAT2 is a good replacement for the MAT02, and its performance and characteristics are guaranteed over the extended temperature range of 40 C to +85 C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA 02062-906, U.S.A. Tel: 78.329.4700 200 204 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
MAT2 TABLE OF CONTENTS Features... Pin Configuration... General Description... Revision History... 2 Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 4 Data Sheet Thermal Resistance...4 ESD Caution...4 Typical Performance Characteristics...5 Applications Information...8 Fast Logarithmic Amplifier...8 Outline Dimensions... 0 Ordering Guide... 0 REVISION HISTORY /4 Rev. 0 to Rev. A Change to Gain Bandwidth Product Parameter... 3 7/0 Revision 0: Initial Version Rev. A Page 2 of 2
Data Sheet MAT2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCB = 5 V, IO = 0 µa, TA = 25 C, unless otherwise specified. Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DC AND AC CHARACTERISTICS Current Gain hfe IC = ma 300 605 40 C TA +85 C 300 IC = 0 µa 200 550 40 C TA +85 C 200 Current Gain Match 2 ΔhFE 0 µa IC ma 0.5 5 % Noise Voltage Density 3 en IC = ma, VCB = 0 V fo = 0 Hz.6 2 nv/ Hz fo = 00 Hz 0.9 nv/ Hz fo = khz 0.85 nv/ Hz fo = 0 khz 0.85 nv/ Hz Low Frequency Noise (0. Hz to 0 Hz) en p-p IC = ma 0.4 µv p-p Offset Voltage VOS VCB = 0 V, IC = ma 0 200 µv 40 C TA +85 C 220 µv Offset Voltage Change vs. VCB ΔVOS/ΔVCB 0 V VCB VMAX 4, µa IC ma 5 0 50 µv Offset Voltage Change vs. IC ΔVOS/ΔIC µa IC ma 5, VCB = 0 V 5 70 µv Offset Voltage Drift ΔVOS/ΔT 40 C TA +85 C 0.08 µv/ C 40 C TA +85 C, VOS trimmed to 0 V 0.03 0.3 µv/ C Breakdown Voltage, Collector to Emitter BVCEO 40 V Gain Bandwidth Product ft IC = 0 ma, VCE = 0 V 200 MHz Collector-to-Base Leakage Current ICBO VCB = VMAX 25 500 pa 40 C TA +85 C 3 na Collector-to-Collector Leakage Current 6, 7 ICC VCC = VMAX 35 500 pa 40 C TA +85 C 4 na Collector-to-Emitter Leakage Current 6, 7 ICES VCE = VMAX, VBE = 0 V 35 500 pa 40 C TA +85 C 4 na Input Bias Current IB IC = 0 µa 50 na 40 C TA +85 C 50 na Input Offset Current IOS IC = 0 µa 6.2 na 40 C TA +85 C 3 na Input Offset Current Drift 6 ΔIOS/ΔT IC = 0 µa, 40 C TA +85 C 40 50 pa/ C Collector Saturation Voltage VCE (SAT ) IC = ma, IB = 00 µa 0.05 0.2 V Output Capacitance COB VCB = 5 V, IE = 0 µa 23 pf Bulk Resistance 6 RBE 0 µa IC 0 ma 0.3.6 Ω Collector-to-Collector Capacitance CCC VCC = 0 V 35 pf Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to VMAX at the indicated collector currents. 2 Current gain match (ΔhFE) is defined as follows: ΔhFE = (00(ΔIB)(hFE min)/ic). 3 Noise voltage density is guaranteed, but not 00% tested. 4 This is the maximum change in VOS as VCB is swept from 0 V to 40 V. 5 Measured at IC = 0 µa and guaranteed by design over the specified range of IC. 6 Guaranteed by design. 7 ICC and ICES are verified by the measurement of ICBO. Rev. A Page 3 of 2
MAT2 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Breakdown Voltage of 40 V Collector-to-Base Voltage (BVCBO) Breakdown Voltage of 40 V Collector-to-Emitter Voltage (BVCEO) Breakdown Voltage of 40 V Collector-to-Collector Voltage (BVCC) Breakdown Voltage of 40 V Emitter-to-Emitter Voltage (BVEE) Collector Current (IC) 20 ma Emitter Current (IE) 20 ma Storage Temperature Range 65 C to +50 C Operating Temperature Range 40 C to +85 C Junction Temperature Range 65 C to +50 C Lead Temperature (Soldering, 60 sec) 300 C THERMAL RESISTANCE Data Sheet θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type θja θjc Unit 6-Lead TO-78 50 45 C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A Page 4 of 2
Data Sheet MAT2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25 C, VCE = 5 V, unless otherwise specified. CH 4.92V p-p 900 800 T A = +25 C 700 CURRENT GAIN (h FE ) 600 500 400 T A = +25 C T A = 55 C 300 200 CH 2.00V M4.00s A CH 5.8V Figure 2. Low Frequency Noise (0. Hz to 0 Hz), IC = ma, Gain = 0,000,000 09044-002 00 0.00 0.0 0. COLLECTOR CURRENT (ma) Figure 5. Current Gain vs. Collector Current (VCB = 0 V) 09044-005 k 900 NOISE VOLTAGE DENSITY (nv/ Hz) 00 0 I C = µa TEST I C = 0µA TEST I C = ma TEST CURRENT GAIN (h FE ) 800 700 600 500 400 300 200 00 ma µa 0. 0. 0 00 k 0k 00k FREQUENCY (Hz) 09044-003 0 00 50 0 50 00 50 TEMPERATURE ( C) 09044-006 Figure 3. Noise Voltage Density vs. Frequency Figure 6. Current Gain vs. Temperature (Excludes ICBO) 00 0.70 0.65 TOTAL NOISE (nv/ Hz) 80 60 40 20 R S = 00kΩ R S = 0kΩ R S = kω BASE EMITTER VOLTAGE, V BE (V) 0.60 0.55 0.50 0.45 0.40 0.35 V CE = 5V 0 0.00 0.0 0. COLLECTOR CURRENT, I C (ma) 09044-004 0.30 0.00 0.0 0. 0 COLLECTOR CURRENT, I C (ma) 09044-007 Figure 4. Total Noise vs. Collector Current, f = khz Figure 7. Base Emitter Voltage vs. Collector Current Rev. A Page 5 of 2
MAT2 Data Sheet 00 000 INPUT RESISTANCE, h IE (MΩ) 0 0. 0.0 V CE = 5V CURRENT, I CBO (na) 00 0 0. 0.00 0.00 0.0 0. 0 COLLECTOR CURRENT, I C (ma) Figure 8. Small Signal Input Resistance vs. Collector Current 09044-008 0.0 25 50 75 00 25 TEMPERATURE ( C) Figure. Collector-to-Base Leakage Current vs. Temperature 09044-00 m 40 35 CONDUCTANCE, h OE (mho) 0.m 0.0m µ 0.µ V CE = 5V CAPACITANCE, C CB (pf) 30 25 20 5 0 5 0.0µ 0.00 0.0 0. 0 00 000 COLLECTOR CURRENT, I C (ma) Figure 9. Small Signal Output Conductance vs. Collector Current 09044-009 0 0 0 20 30 40 50 REVERSE BIAS VOLTAGE (V) Figure 2. Collector-to-Base Capacitance vs. Reverse Bias Voltage 09044-0 00 40 35 COLLECTOR CURRENT, I C (ma) 0 0. T A = 55 C T A = +25 C T A = +25 C CAPACITANCE, C CC (pf) 30 25 20 5 0 5 0.0 0 0. 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 SATURATION VOLTAGE, V SAT (V) Figure 0. Collector Current vs. Saturation Voltage 09044-08 0 0 0 20 30 40 50 COLLECTOR-TO-SUBSTRATE VOLTAGE (V) Figure 3. Collector-to-Collector Capacitance vs. Collector-to-Substrate Voltage 09044-02 Rev. A Page 6 of 2
Data Sheet MAT2 000 4.0 COLLECTOR-TO-COLLECTOR LEAKAGE CURRENT, I CC (na) 00 0 0. COLLECTOR-TO-COLLECTOR CAPACITANCE, C CC (pf) 3.5 3.0 2.5 2.0.5.0 0.5 0.0 25 50 75 00 25 TEMPERATURE ( C) Figure 4. Collector-to-Collector Leakage Current vs. Temperature 09044-03 0 0 0 20 30 40 50 REVERSE BIAS VOLTAGE (V) Figure 5. Collector-to-Collector Capacitance vs. Reverse Bias Voltage 09044-04 Rev. A Page 7 of 2
MAT2 APPLICATIONS INFORMATION FAST LOGARITHMIC AMPLIFIER The circuit of Figure 6 is a modification of a standard logarithmic amplifier configuration. Running the MAT2 at 2.5 ma per side (full scale) allows for a fast response with a wide dynamic range. The circuit has a seven decade current range and a five decade voltage range, and it is capable of 2.5 µs settling time to % with a V to 0 V step. The output follows the equation: V O R3 + R = R 2 2 kt V ln q V REF IN Data Sheet To compensate for the temperature dependence of the kt/q term, a resistor with a positive 0.35%/ C temperature coefficient is selected for R2. The output is inverted with respect to the input and is nominally V/decade using the component values indicated. +5V V IN (0V TO 0V) R S 4kΩ 2 3 8 AD852 4 V O 5V 330pF R 3 7.5kΩ 330pF MAT2 V REF 0V R 4kΩ 6 5 /2 AD852 7 4kΩ R 2 500Ω R 2 = 0.35%/ C 09044-05 Figure 6. Fast Logarithmic Amplifier Rev. A Page 8 of 2
Data Sheet LOG CONFORMANCE TESTING The log conformance of the MAT2 is tested using the circuit shown in Figure 8. The circuit employs a dual transdiode logarithmic converter operating at a fixed ratio of collector currents that are swept over a 0: range. The output of each transdiode converter is the VBE of the transistor plus an error term, which is the product of the collector current and rbe, the bulk emitter resistance. The difference of the VBE is amplified at a gain of 00 by the AMP02 instrumentation amplifier. The differential emitter base voltage ( VBE) consists of a temperaturedependent dc level plus an ac error voltage, which is the deviation from true log conformity as the collector currents vary. The output of the transdiode logarithmic converter comes from the following idealized intrinsic transistor equation (for silicon) kt I C VBE = ln () q I S where: k is Boltzmann s constant (.38062 0 23 J/K). q is the unit electron charge (.6029 0 9 C). T is the absolute temperature, K (= C + 273.2). IS is the extrapolated current for VBE 0 (VBE tending to zero). IC is the collector current. An error term must be added to Equation to allow for the bulk resistance (rbe) of the transistor. Error due to the op amp input current is limited by use of the AD852 dual op amp. The resulting AMP02 input is: kt IC VBE = = ln + ICrBE IC2rBE2 (2) q I C2 A ramp function that sweeps from V to 0 V is converted by the op amps to a collector current ramp through each transistor. MAT2 Because IC is made equal to 0 IC2, and assuming TA = 25 C, Equation 2 becomes VBE = 59 mv + 0.9 IC rbe ( rbe ~ 0) As viewed on an oscilloscope, the change in VBE for a 0: change in IC is shown in Figure 7. LOGGING ERROR, ΔV BE (mv) 6.5 6.0 60.5 60.0 59.5 59.0 58.5 0 00 COLLECTOR CURRENT (ma) Figure 7. Emitter Base, Log Conformity With the oscilloscope ac-coupled, the temperature dependent term becomes a dc offset and the trace represents the deviation from true log conformity. The bulk resistance can be calculated from the voltage deviation, VO, and the change in collector current (9 ma): VO r BE = (3) 9 ma 00 This procedure solves for rbe for Side A. Switching R and R2 provides the rbe for Side B. Differential rbe is found by making R = R2. 09044-06 kω V CC I C SIDE A DUT Q V + BE +5V /2 AD852 N94 500Ω +5V 00pF 5V V CC 00pF A V = 00 AMP02 V OUT = 00ΔV BE kω 5V I C2 /2 AD852 N94 500Ω 5V + V +5V BE Q2 SIDE B DUT Figure 8. Log Conformance Circuit 09044-07 Rev. A Page 9 of 2
MAT2 Data Sheet OUTLINE DIMENSIONS 0.370 (9.40) 0.335 (8.5) 0.335 (8.5) 0.305 (7.75) 0.85 (4.70) 0.65 (4.9) 0.040 (.02) MAX 0.045 (.4) 0.00 (0.25) REFERENCE PLANE 0.750 (9.05) 0.500 (2.70) 0.250 (6.35) MIN 0.00 (2.54) BSC 0.050 (.27) MAX 0.09 (0.48) 0.06 (0.4) 0.02 (0.53) 0.06 (0.4) 0.200 (5.08) BSC 0.00 (2.54) BSC BASE & SEATING PLANE 3 2 4 5 6 0.034 (0.86) 0.027 (0.69) 0.60 (4.06) 0.0 (2.79) 45 BSC 0.045 (.4) 0.027 (0.69) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 9. 6-Pin Metal Header Package [TO-78] (H-06) Dimensions shown in inches and (millimeters) 022306-A ORDERING GUIDE Model Temperature Range Package Description Package Option MAT2AHZ 40 C to +85 C 6-Pin Metal Header Package [TO-78] H-06 Z = RoHS Compliant Part. Rev. A Page 0 of 2
Data Sheet MAT2 NOTES Rev. A Page of 2
MAT2 Data Sheet NOTES 200 204 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09044-0-/4(A) Rev. A Page 2 of 2