Micron MT66R7072A10AB5ZZW 45 nm BiCMOS PCM Process Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
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Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product 2.2 Package 2.3 U57M Mobile LPDDR2 and IMOLA PCM Dies 2.4 IMOLA PCM Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Phase Change Memory Layers 3.8 Isolation 3.9 Wells and Substrate 4 PCM Cell Analysis 4.1 Overview 4.2 Plan-View Analysis 4.3 Cross-Sectional Analysis 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Smartphone Tilt View 2.1.2 Smartphone Front 2.1.3 Smartphone Back 2.1.4 Smartphone Battery Pack 2.1.5 Main Circuit Board Front 2.1.6 Main Circuit Board Back 2.2.1 Package Top 2.2.2 Package Bottom 2.2.3 Package X-Ray Top 2.2.4 Package X-Ray Side 2.3.1 U57M Mobile LPDDR2 Die 2.3.2 U57M Mobile LPDDR2 Die Markings 2.3.3 IMOLA PCM Die 2.3.4 IMOLA PCM Die Markings 2.3.5 Annotated Photograph of the IMOLA PCM Die Delayered to Poly 2.3.6 IMOLA Die Cross Sections 2.4.1 Die Corner A 2.4.2 Die Corner B 2.4.3 Die Corner C 2.4.4 Die Corner D 2.4.5 Minimum Pitch Bond Pads 2.4.6 PCM Tile Top Metal 2.4.7 PCM Tile Poly 3 Process Analysis 3.1.1 IMOLA PCM Die General View 3.1.2 Die Edge 3.1.3 Die Edge Detail 3.2.1 Bond Pad 3.2.2 Right Bond Pad Edge 3.3.1 Passivation 3.3.2 Passivation Over Closely Spaced Metal 4 Lines 3.3.3 TEM IMD 3 3.3.4 ILD 2 3.3.5 ILD 1 3.3.6 TEM PMD Periphery (Die A) 3.3.7 TEM PMD Periphery (Die B) 3.3.8 SEM PMD Memory Array to Periphery Transition 3.3.9 TEM PMD Memory Array to Periphery Transition 3.3.10 TEM PMD PCM Memory Array 3.4.1 Minimum Pitch Metal 4 SEM 3.4.2 Metal 4 Barrier TEM
Overview 1-2 3.4.3 Minimum Pitch Metal 3 SEM 3.4.4 Metal 3 TEM 3.4.5 Metal 3 Liner TEM 3.4.6 Minimum Pitch Metal 2 in Periphery SEM 3.4.7 Metal 2 in Memory Array TEM 3.4.8 Minimum Pitch Metal 1 (Die A) in Periphery SEM 3.4.9 Minimum Pitch Metal 1 (Die A) in Memory Array SEM 3.4.10 Metal 1 (Die A) Detail in Periphery TEM 3.4.11 Metal 1 (Die A) Bottom and Liner Detail TEM 3.4.12 Metal 1 (Die B) Detail in Logic TEM 3.5.1 Minimum Pitch Via 3s 3.5.2 Minimum Pitch Via 2 SEM 3.5.3 Minimum Pitch Via 1s in Periphery SEM 3.5.4 Minimum Pitch Via 1s in Periphery TEM 3.5.5 Minimum Pitch Contacts in Periphery 3.5.6 TEM Contact in Periphery (Die A) 3.5.7 TEM Contact in Periphery Top 3.5.8 TEM Contact in Periphery Bottom 3.5.9 W Plug Stack (Via 1/Contact 1/Contact 0) in Memory Array TEM 3.5.10 W Contact 0 Interface with Substrate Diffusion in Memory Array TEM 3.5.11 W Contact 1 Interface with W Contact 0 in Memory Array TEM 3.5.12 W Via 1 Interface with W Contact 1 in Memory Array TEM 3.5.13 W Via 1 Interface with Metal 1 in Memory Array TEM 3.6.1 Minimum Contacted Gate Pitch 3.6.2 Minimum Gate Length MOS Transistor TEM 3.6.3 Right Edge and Sidewall Spacer Structure of a MOS Transistor TEM 3.6.4 Logic Transistor Gate Oxide TEM 3.6.5 Peripheral Long Gate Transistor TEM 3.6.6 Peripheral Long Gate Sidewall Spacer TEM 3.6.7 Peripheral Long Gate Transistor Gate Oxide TEM 3.6.8 Minimum Gate Length NMOS Transistors 3.6.9 Minimum Gate Length PMOS Transistors 3.7.1 PCM Cell Schematic 3.7.2 TEM Cross Section of PCM Cell (Length) 3.7.3 SEM Cross Section of PCM Cell (Si Stain) 3.7.4 Gap Between PCM Cells TEM 3.7.5 PCM Top Electrode Contact 3.7.6 PCM (Length) 3.7.7 GST TEM-EDS 3.7.8 PCM TEM (Width) 3.7.9 PCM Layers in Detail TEM (Width) 3.7.10 PCM Over Nitride Pedestal in Detail (Width) 3.7.11 Heater Intersection with GST PCM Layer 3.7.12 Heater TEM-EDS 3.8.1 Poly Over Isolation
Overview 1-3 3.8.2 STI Wordlines 3.8.3 STI Bitlines 3.9.1 Wells Periphery to PCM Transition SCM 3.9.2 P-Epi and P-Type Substrate SEM (Si Stain) 3.9.3 Epi and Substrate SRP 3.9.4 Array P-Well SRP 3.9.5 SEM N + Base, N - Base, and P + Emitter Si Stain with Etch Conditions of Type A (Perpendicular to PCM Line) 3.9.6 SEM N + Base, N - Base, and P + Emitter Si Stain with Etch Conditions of Type B (Perpendicular to PCM Line) 3.9.7 P + Emitter and N - Base SEM (Parallel to PCM Line) 3.9.8 P + Emitter and N - Base SCM (Parallel to PCM Line) 3.9.9 N + Base and N - Base SEM (Parallel to PCM Line) 3.9.10 Peripheral N-Well 2 and P-Well SCM 3.9.11 Peripheral P-Well and N-Well 2 SRP 3.9.12 Peripheral N-Well 1 and N-Well 2 SRP 4 PCM Cell Analysis 4.1.1 PCM Schematic Circuit 4.2.1 PCM Array Edge at Metal 3 to Metal 2 Transition 4.2.2 Metal 2 Wordlines and Bitlines 4.2.3 Metal 2 Wordlines Detail 4.2.4 Metal 2 Wordlines to Metal 1 Bitlines Transition 4.2.5 Metal 1 Bitlines Overview at the Array Edge 4.2.6 Metal 1 Bitlines Detail 4.2.7 Contacts to the Base (Wordline) and Emitter of BJT Overview 4.2.8 Contacts to the Base (Wordline) and Emitter of BJT Detail 4.2.9 Memory Array at Interface Between Contact and Diffusion 4.2.10 PCM at Diffusion 4.3.1 PCM Overview Cross Section (Parallel to Metal 2 Wordline) 4.3.2 Active PCM Cells Detailed Cross Section (Parallel to Metal 2 Wordline) 4.3.3 Dummy PCM Cells at Memory Array to Periphery Transition (Parallel to Wordline) 4.3.4 PCM Overview Cross Section (Parallel to Metal 1 Bitline) 4.3.5 PCM Detailed Cross Section (Edge of PCM Line) 4.3.6 Dummy PCM Cells at Memory Array to Periphery Transition (Parallel to Bitlines)
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.5.2 IMOLA Die Device Summary 1.6.1 Process Summary 2 Device Overview 2.3.1 Functional Block Sizes 2.4.1 Package, Die, and Bond Pad Sizes 3 Process Analysis 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Horizontal Dimensions 3.6.1 Transistor Horizontal Dimensions 3.6.2 Transistor and Polycide Vertical Dimensions 3.7.1 PCM Stack Vertical Dimensions 3.7.2 PCM Stack Horizontal Dimensions 3.8.1 STI Vertical Dimensions 3.8.2 STI Horizontal Dimensions 3.9.1 Die Thickness, Well Depths, and Doping Concentrations 4 PCM Cell Analysis 4.3.1 PCM Cell Dimensions 5 Critical Dimensions 5.1.1 Package, Die, and Bond Pad Sizes 5.1.2 Metallization Horizontal Dimensions 5.1.3 Via and Contact Horizontal Dimensions 5.1.4 Transistor Horizontal Dimensions 5.1.5 PCM Stack Horizontal Dimensions 5.1.6 PCM Cell Dimensions 5.1.7 STI Horizontal Dimensions 5.2.1 Dielectric Thicknesses 5.2.2 Metallization Vertical Dimensions 5.2.3 Transistor and Polycide Vertical Dimensions 5.2.4 PCM Stack Vertical Dimensions 5.2.5 STI Vertical Dimensions 5.2.6 Die Thickness and Well Depths
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