TVS Diodes Transient Voltage Suppressor Diodes BGF120A Dual Channel UltraLow Capacitance ESD Diode Datasheet Rev. 1.4, 20120917 Final Power Management & Multimarket
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BGF120A Dual Channel UltraLow Capacitance ESD Diode 1 BGF120A Dual Channel UltraLow Capacitance ESD Diode 1.1 Features ESD /transient protection of highspeed data and RF antenna lines exceeding: IEC6100042 (ESD): 18 kv (contact) Max. reverse working voltage: 5.3 V Ultralow capacitance: < 0.75 pf (max.) in bidirectional configuration < 1.5 pf (max.) in unidirectional configuration Very low reverse current: < 1 na (typ.) Small leadless plastic package with 0.75 mm x 0.75 mm size (typ.) and 0.66 mm height (max.) 400 μm pad pitch and 40 μm Sn solder depot on pads RoHS and WEEE compliant package 1.2 Application USB 2.0, 10/100/1000 Ethernet, Firewire, DVI, HDMI, SATA RF antenna protection e.g. GPS, FM radio, mobile TV 1.3 Description The BGF120A can be used for 2 lines unidirectional or 1 line bidirectional ESD and surge protection up to 20 kv contact discharge according to IEC6100042. The capacitance of the device is less then 0.75 pf (max.) in bidirectional configuration and less than 1.5 pf (max.) in unidirectional configuration. Maximum reverse working voltage is 5.3 V (unidirectional) or ±5.3 V (bidirectional). The reverse leakage current is less than 1 na (typ.). The leadless plastic package has 0.75 mm x 0.75 mm typical size and maximum height of 0.66 mm. The pads have 400 μm pitch and offer 40 μm Sn for high reliability soldering Pin 1 A1 A2 Pin 4 A1 A2 Pin 2 B1 B2 Pin 3 B1 B2 (a) Pin configuration (top view) (b) Schematic diagram BGF120A_pin_configuration_schematic.vsd Figure 11 Pin Configuration and Schematic Diagram Type Package Configuration Marking code BGF120A TSLP48 2 lines, unidirectional 1) A 1) Or 1 line, bidirectional between A1 and A2, if B1, B2 are not connected Final Datasheet 4 Rev. 1.4, 20120917
Electrical Characteristics 2 Electrical Characteristics Table 21 Maximum Ratings T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Operating temperature range T OP 40 +125 C Storage temperature range T STG 65 +150 C Contact discharge 1) V ESD 18 kv 1) V ESD according to IEC6100042 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 22 DC Electrical Characteristics T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse working voltage V RWM 5.3 V Breakdown voltage V BR 6 V I BR = 1mA Reverse current I R <1 50 na V R =5.3V Table 23 DC Electrical Characteristics T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Line capacitance 1) A1 or A2 to B1/B2 A1 to A2, B1/B2 n.c. C L Series inductance per diode L S 0.25 nh 1) Total capacitance line to ground 1.5 0.75 pf V R =0V, f =1MHz Final Datasheet 5 Rev. 1.4, 20120917
Electrical Characteristics V V Table 24 ESD Characteristics at T A = 25 C, unless otherwise specified Parameter Symbol Values Unit Note / Min. Typ. Max. Test Condition Reverse clamping voltage 1) V A1 or A2 vs B1, B2 CL 22 I TLP =16A, A1 or A2 vs B1, B2 31 I TLP =30A, Forward clamping voltage 1) V A1 or A2 vs B1, B2 FC 14 I TLP =16A, A1 or A2 vs B1, B2 20 I TLP =30A, Dynamic resistance 1) positive pulse A1 or A2 vs. B1, B2 negative pulse A1 or A2 vs B1, B2 R DYN 1) ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitive Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z 0 =50Ω, t p = 100 ns, t r=0.6ns, I TLP and V TLP averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristic between I PP1 = 10 A and I PP2 = 30 A. Please refer to Application Note AN210[1]. 0.7 0.5 Ω Final Datasheet 6 Rev. 1.4, 20120917
Typical Characteristics 3 Typical Characteristics 10 3 10 4 10 5 10 6 I R [A] 10 7 10 8 10 9 10 10 10 11 10 12 0 1 2 3 4 5 V R [V] Figure 31 Reverse current I R =f(v R ) 1.5 1.25 1 C L [pf] 0.75 0.5 0.25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 V R [V] Figure 32 Capacitance A1vs. B1, A2 vs. B2, C L(A1,B1) = C L(A2,B2) = f(v R ) Final Datasheet 7 Rev. 1.4, 20120917
Typical Characteristics 70 60 Scope: 20 GS/s V CL [V] 50 40 30 20 10 0 V CLmaxpeak = 62.5 [V] V CL30nspeak = 18.6 [V] 10 100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 33 Clamping voltage at +8 kv discharge according IEC6100042 (R =330Ω, C =150pF) 10 0 Scope: 20 GS/s V CL [V] 10 20 30 40 50 60 V CLmaxpeak = 62.7 [V] V CL30nspeak = 10.6 [V] 70 100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 34 Clamping voltage at 8 kv discharge according IEC6100042 (R =330Ω, C = 150 pf) Final Datasheet 8 Rev. 1.4, 20120917
Typical Characteristics 120 Scope: 20 GS/s 100 V CL [V] 80 60 40 V CLmaxpeak = 104.2 [V] V CL30nspeak = 25.4 [V] 20 0 20 100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 35 Clamping voltage at +15 kv discharge according IEC6100042 (R =330Ohm, C = 150 pf) 20 Scope: 20 GS/s 0 20 V CL [V] 40 60 80 V CLmaxpeak = 108.3 [V] V CL30nspeak = 14.9 [V] 100 120 100 0 100 200 300 400 500 600 700 800 900 t p [ns] Figure 36 Clamping voltage at 15 kv discharge according IEC6100042 (R =330Ω, C =150pF) Final Datasheet 9 Rev. 1.4, 20120917
Typical Characteristics 40 35 BGF120A A1B1 R DYN 20 17.5 30 15 25 R DYN = 0.67 Ω 12.5 20 10 15 7.5 10 5 I TLP [A] 5 0 5 2.5 0 2.5 Equivalent V IEC [kv] 10 5 15 7.5 20 10 25 R DYN = 0.45 Ω 12.5 30 15 35 17.5 40 20 40 35 30 25 20 15 10 5 0 5 10 15 20 25 30 35 40 V TLP [V] Figure 37 Clamping voltage (TLP): I TLP = f(v TLP ) according ANSI/ESD STM5.5.1 Electrostatic Dischange Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z 0 =50Ω, t p =100ns, t r =0.6ns, I TLP and V TLP averaging window: t 1 =30ns to t 2 = 60 ns, extraction of dynamic resistance using squares fit to ELP charactersistic between I TLP1 = 10 A and I TLP2 = 30 A. Please refer to Application Note AN210 [1] Final Datasheet 10 Rev. 1.4, 20120917
Application and Signal Routing 4 Application and Signal Routing Application example for highspeed data line protection (unidirectional) This low parasitic capacitance dual channel TVS diode array can be used either in a 2 channel unidirectional configuration or in a single channel bidirectional configuration. Due to the low capacitance and low inductance the configurations are perfect fit for ultra highspeed interfaces, such as USB2.0/3.0, SATA, DVI or HDMI ports. Connector Signal level: 0 +5.3V A1 A2 B1 B2 ESD sensitive circuit Theprotectiondiode should be placed very close to the location where the ESD or other transients can occur to keep loops and inductances as small as possible. Pin B1, B2 should be directly connected to a ground plane on the board. Figure 41 Application example for highspeed data line protection (unidirectional) Application example for RF antenna line (bidirectional) Connecting pin A1(A2) to the signal line and A2(A1) to GND and leaving pin B1/B2 floating even further reduces the parasitics to 0.75 pf only and correspondingly enable the user to add reliable ESD protection to RF antennas in e.g. GPS, FM radio or mobile TV applications without influence of the RF circuitry. Signal level: 5.3V +5.3V A1 B1 ESD sensitive circuit Pin A1 (or A2) should be directly connected to the RF signal line and A2 (or A1) should be connected directly to a ground plane on the board. A2 B2 B1, B2 should be not connected. Figure 42 Application example for RF antenna line (bidirectional) Final Datasheet 11 Rev. 1.4, 20120917
Package 5 Package Top view Bottom view 0.055 MAX. +0.06 0.6 0.25 0.75 ±0.035 1) ±0.025 0.4 ±0.025 2 3 1 4 1) ±0.025 0.25 0.75 ±0.035 Pin 1 marking 0.4 ±0.025 1) Dimension applies to plated terminals TSLP48PO V01 Figure 51 Package outline for TSLP48 (dimension in mm) 0.4 0.4 0.25 TSLP48FP V01 Figure 52 Package footprint for TSLP48 (dimension in mm) 4 0.23 0.85 8 Pin 1 marking 0.85 0.7 TSLP48TP V03 Figure 53 Tape and Reel Information for TSLP48 (dimension in mm) Pin 1 marking Type code Figure 54 Marking (example) for TSLP48 Final Datasheet 12 Rev. 1.4, 20120917
References References [1] Infineon Technologies AG, Effective ESD Protection Design at System Level Using VFTLP Characterization Methodology, Application Note 210, RF and Protection Devices, April 22, 2010, Rev.1.0 [2] Infineon Technologies AG, Recommendation for PCB Assembly of Infineon TSLP and TSSLP Packages. Final Datasheet 13 Rev. 1.4, 20120917
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