CHAPTER 4 DESIGN OF DC LINK VOLTAGE CONTROLLER FOR SHUNT ACTIVE POWER FILTER

68 CHAPTER 4 DESIGN OF DC LINK VOLTAGE CONTROLLER FOR SHUNT ACTIVE POWER FILTER The Shunt Active Power Filters (SAPFs) are tools which are powerful for compensating not only of current harmonics created by nonlinear loads likewise of reactive power and unbalance of distorted and fluctuating loads. Voltage compensation is based on capacitor DC link voltage.the synchronous reference frame theory is proposed in this thesis for time domain approach based reference current estimation method. It achieves the operation in steady state or transient state as well as for generic voltage and current waveforms. This chapter deliberates the principle of active power filter and DC link capacitor. 4.1 PRINCIPLE OF ACTIVE POWER FILTER The Shunt Active Power Filter (SAPF) is designed to suppress the source current harmonics as well as to improve the power factor of a source. SAPF is connected at a point of common coupling point (PCC) in the distribution grid through filter inductance (Ramos2013). The harmonics formed by the switching operation of the power inverter is reduced by the filter inductance. An injection of equal and opposite current harmonic components at PCC cancels the original distortion and improves the power quality of the connected power distribution system. The shunt active power filter works with either controllable voltage or current source. The voltage

69 source converter (VSC) based shunt active power filter is by far the most common today, due to its well-known topology and straightforward installation procedure as shown in Figure 4.1. It consists of a DC link capacitor C DC, Active filter by power electronic switches and filter inductors L f.the capacitor acts as a voltage source for compensation. Figure 4.1 Operation principle of SAPF System The instantaneous can be written by i source(t)= i load(t)- i compensation(t) (4.1) The source voltage is VmSinωt (4.2) Applying a nonlinear load into the load side, the load current will have fundamental component and harmonic components that can be expressed by,

70 i load (t)= InSin(nωt +φ n ) n=1 I1Sin(nωt +φ n )+ Sin(nωt +φ n ) (4.3) n=2 1 2 The first part is the fundamental component of the load current and the second part is the harmonic component. The instantaneous load power can be calculated by P Load (t)= v source(t) i load(t) (4.4) V I Sin ωt Cosf +V I Sinωt Cosωt Sinf +V Sinωt I Sin(nωt +φ ) 2 m 1 1 m 1 1 m n n n=2 1 2 3 (4.5) The first term is the active power of load current at the fundamental frequency. The reactive power of the load current at the fundamental frequency is the second term and the power constituted by harmonics is the third term. P fundamental(t)= v s(t) i s(t) (4.6) From the equation (4.6) the source current after compensation is P i = = I Cosθ Sinωt = I Sinωt fundamental source 1 1 SM v s(t) (4.7)

71 Where I SM = I1Cosθ 1 The instantaneous value of the total active current is subtracted from the total current demanded by the load from which reference compensation current of the converter is calculated as in equation (4.8). i Compensation(t)= i Load(t)- i Source(t) (4.8) Robustness analysis of the current control system is relevant to choosing the final APF design. The plant parameters, R f, and L f, are expected to vary in frequency and magnitude of the APF current. Magnetic core effects and switch losses are the causes of such plant model nonlinearity. With this parameter uncertainty, the closed-loop pole of the reference to an output transfer function moves along the real axis of the S-plane, away from the origin. The stability on load variation and the accuracy of the harmonic current compensation are extremely dependent on the PLL response. 4.2 CONTROL ALGORITHM FOR SHUNT ACTIVE FILTER The synchronous reference frame theory is based on time domain reference signal estimation techniques. It performs the operation in the steady state or transient state as well as for generic voltage and current waveforms (Zaveri 2012). The current control scheme of SAPF based on the synchronous reference detection method is shown in Figure 4.2. For simple and accurate control initially the three phase line currents i a, i b, and i c are transformed from three phase (a-b-c) reference frame to two phase (d-q) stationary reference frame currents I d and I q using park transform. The equation (4.9) shows the park transformation for abc - dq calculation.

72 2π 2π sinωt- sinωt+ i i a d 2 sinωt 3 3 = i 3 ib q cosωt 2π 2π cosωt- cosωt+ 3 3 ic (4.9) The park transformation converts the fundamental current component to continuous component whereas the harmonic current components experience a shift in the frequency spectrum; the continuous component can be reduced by adding Butter worth low pass filter (50Hz). When the Butterworth low pass filter is used it provides a maximally flat response. The advantage of this filter is the calculations are simpler when compared with other forms of filter. The level of performance and simple calculation is more than adequate to use Butterworth low pass filter for many electronics application. Hence it is likely to derive the formula for the Butterworth filter frequency response: 2 V 1 = out V f 2n in 1+( ) fc (4.10) Where: f = frequency at which calculation is made fc = the cut-off frequency, i.e. half power or -3dB frequency V in = input voltage V out = output voltage n = number of elements in the filter The low pass filter helps to remove higher order harmonics. Harmonic current references can be obtained by performing the inverse transform of parks synchronized with network frequency. The Phase Locked Loop (PLL) performance and the load current (fundamental and harmonic components) determine the d-q transformation output signals. The PLL circuit

73 is responsible for the rotation speed of rotating reference frame, where ωt is set as fundamental frequency component. The synchronization of sin and cos is done based on Vectorized 50 Hz frequency and 30 0 phase angle of the PLL circuit. The steady state error of the DC component of d axis reference signals is eliminated by using the PI controller. Additionally it maintains capacitor voltage approximately constant. For compensating the inverter losses and to regulate the DC link voltage V dc, a PI controller is used. sinωt cosωt i 2π 2π sinωt - cosωt - i i = 3 3 i i 2π 2π * a * b * c sinωt + cosωt + 3 3 (4.11) d q by the equation 4.11 The current expressions I d and I q in (d-q) reference frame are given Figure 4.2 Current control Scheme for SAPF System

74 4.3 DESIGN OF DC CAPACITOR GENERAL CONCEPT The DC voltage control loop retains the voltage constant under steady state operating conditions. Still during, transient changes the instantaneous power absorbed by the load, produce voltage fluctuations across dc capacitor. By maintaining appropriate dc capacitor value the amplitude of these voltage fluctuations can be controlled effectively. Some rules are followed when designing the capacitor. In steady state, the fluctuating voltage of the capacitor is very small compared to the average voltage. The converter is lossless The variation of the harmonic power is the reason behind the voltage fluctuation in the dc capacitor under steady state and the energy stored in the reactor. There are two components, distorted current and ripple current which are superimposed on reference current because of the switching action of the converter. For the first current the energy variation is null since it is a periodic ac waveform. The second part contains the energy that the inductor releases in the capacitor inside one switching period. During the on state, energy is stored across the inductor and this energy is engrossed by the capacitor during the off state. Because the switching frequency is high, the effect of this energy deviation on the dc bus is ignored. For the single phase case, by balancing the instantaneous input power to the instantaneous output power we obtain, v. si = af i. +. dc1v dc1 i dc2v (4.12) dc2 v = dc1 V + dc1 V (4.13) dc1

75 v = dc2 V + dc2 V (4.14) dc2 dv dc1 i = 2.C. (4.15) dc1 dt dv dc2 i = 2.C. (4.16) dc2 dt Using the detail, that the average dc voltage of each capacitor is approximately equal then, dv dt dc v. si = C. af V (4.17) dc v =. 2sinωt s V (4.18) s i = af I. 2.sin(hωt - ) af.h φ (4.19) h h=3,5 The voltage fluctuation across the capacitor is V dc Vdc V (4.20) max dc min Δ = - The energy variation across the capacitor is Emax E (4.21) min ΔE = - Where

76 t vi (4.22) s af 0 E =..dt V Δ = dc C. ΔE V dc (4.23) It can be shown that using almost high switching frequency the instantaneous energy can be represented as t vi (4.24) s load.h 0 E =..dt The equation 4.24 shows that the voltage fluctuation across the capacitor. The main function of the converter is to reduce instantaneous energy fluctuation, DC bus voltage and size of the capacitor. The regulation of the dc voltage is defined as the ratio between the change in dc bus voltage and the actual dc bus voltage and is expressed as, r v Δ = V V dc dc (4.25) regulation is given by Finally the minimum capacitor value to meet the required voltage C min 1 = ΔE 2 V. dc r v (4.26) For three phase case the equation is replaced by

77 t 0 vs.ji (4.27) jh j=a,b,c E =..dt The capacitors are designed to produce the dc voltage ripple to a limit of 1 to 2%. The capacitor should be designed for the least scenario. Since active power filter will operate in several modes. May perhaps in single phase or unbalanced load. It follows that capacitor value is load dependent, and simulation is one way of estimating the least possible case. The least case occurs when the active filter is compensating the load. The harmonic frequencies of the dc bus voltage in the case of a single phase load can be found by expanding the above equation t E = (V s. 2. I h. 2.sin(ωt).sin(hωt - φh )).dt 0h=2,4 (4.28) Transforming the product into summation yields, E= t 2. V s. I h.(cos[(h -1)ωt - φh ] - cos(h+1)ωt - φh ]) 0h=2,4 (4.29) Integrating 1 1 E = V s. I h sin[(h - 1)ωt - φ ] - sin[(h+1)ωt - φ ] +c (h - 1)ω h (h+1)ω h te h=2,4 (4.30) The equation 4.30 shows the dc bus voltage has harmonic components which is twice the main frequency, resulting from the third harmonic of the load, a harmonic component which is four times the main frequency, which is influencing the third and fifth harmonic of the load, hence at the even harmonics are present in the spectrum of the dc bus voltage. The

78 spectrum of the dc bus has similar harmonic distribution, under unbalanced load condition. The dc bus ripple components are situated at multiples of six times the mains frequency under balanced load state. 4.4 DC CAPACITOR VOLTAGE FOR SUDDEN CHANGING LOAD In certain circumstances, there will be sudden change in load, for instance disconnection from the AC line or sudden connection to the AC line. The active filter current has not yet changed until the next cycle even when the load current is dropped. Hence this extra current (ΔI af ) will charge the capacitor. Where ΔI af is the step drop of the peak value of active filter, accompanied with the drop of the fundamental load current. We have, 2 C dvdc = v. 2 dt s iaf (4.31) Let V dm = V dc + V dc, then the equation becomes 2 4 V s. 2.ΔI af Δ V dc+ 2. V dc.δv dc - = 0 Cω (4.32) The previous equation shows that the voltage rises when the load steps down. For the calculated value C, the voltage increase is gained by solving the second order equation. If the voltage increase is not tolerable, then new value of the capacitor is gained by imposing a tolerable voltage range. It is found that the new value of capacitor is greater. Likewise, when the load current has a step increase, the energy stored in the capacitor must be released instantly to support the step increase of the power consumed by the load. In

79 this case the I af is replaced by - I af and the voltage drop V dc is replaced by - V dc. Hence, the voltage drop is obtained. 4.5 ACTIVE FILTER CURRENT COMPENSATION CAPACITY The calculation of maximum current that the active filter can compensate is based on the frequency of the current to track. The data is gained by means of maximum rate of increase of the current to compensate as equal to the maximum rate of increase produced by the active filter. The current to compensate is given by i = I Sin(ω t - f ) h h h h (4.33) Since the di/dt capability of the active filter is defined by diaf 0.5Vdc -Vs 2 = dt Laf (4.34) The compensation capability is calculated by 0.5Vdc -Vs 2 I h = 2πf L h af (4.35) The curves in Figure 4.3 show that the compensation capability of the active filter increases if the dc bus voltage is increased.

80 Figure 4.3 Current compensation capability of the active filter as a function of frequency 4.6 EFFECT OF DC BUS RIPPLE ON COMPENSATION CAPABILITY Up to now the dc bus voltage was assumed and without ripple. To study the outcome of capacitor, a ripple component at twice the main frequency is considered in the dc bus voltage. The instantaneous dc bus voltage is defined as v = V + A sin(2ωt - ) (4.36) dc dc r r f Where A r is the amplitude of the ripple component obtains Connecting the amplitude of ripple to voltage regulation ratio, one V v V ω = + 2 r sin( t - ) (4.37) dc dc dc v r r f

81 The compensation capability of the active filter is given by, di dt af 0.5Vdc -V = L af s (4.38) In switching period of the converter, the poorest case happens when the ripple component is at its least value, thus decreasing the driving voltage important to produce the di/dt which is expressed by, di dt af 0.5Vdc - r v.v dc / 4 -V s. 2 = L af (4.39) Let d represents the ratio of the dv/dt of active filter with ripple over the di/dt of active filter without a ripple. Additionally, this ratio denotes the ratio by which the peak current is reduced in the presence of ripple in the dc bus voltage. di dt withripple d= (4.40) di dt withoutripple 1-0.5r - m d= 1- m v 0 0 (4.41) In the dc bus there is a ripple which makes a voltage drop at the output of the active filter, thus decreasing the driving voltage through the inductor. The result of the ripple is represented in Figure 4.4. The curves shows that the compensation capability of the active filter decreases when the ripple in the dc bus voltage increases (Rahmani 2010).

82 Figure 4.4 Effect of the DC bus ripple on di/dt capability of active filter A smaller capacitor value is allowed, in case that the di/dt of the active filter remains greater than the di/dt of the distorting current. 4.7 REQUIRED HARMONIC POWER BY ACTIVE FILTER The sinusoidal current can be obtained at the main, when harmonic power is inserted into the system, thus abandoning the distorting power of the load. In the general case, if the Reactive power and harmonic power is injected, H+Q, then, H +Q = Scom Sinφ 2 2 1 i +THD 1++THD 2 i (4.42) Figure 4.5 gives the required reactive and harmonic power from the active filter about the evaluation of load converter, as function of the total harmonic distortion of load current, for several displacement power factors. The curve shows that if reactive power is combined with harmonic compensation, the required rating is substantially increased. Also, the curves in Figure 4.5 shows that the required rating increases with a faster rate as the load THD rises. For harmonic compensation, the equation 4.43 are used.

83 H S com = THDi 1+THD 2 i (4.43) H =V s* I i*thd i (4.44) The power factor correction is the main difference between combined harmonic and reactive compensation, H+Q and harmonic injection, H. In case one, the current in the mains has a unity power factor and a sinusoidal waveform, in case two the supply is harmonic free. Though, the supply voltage and current are not in phase. Here H is the harmonic compensation and Q is the reactive power compensation. Figure 4.5 Required harmonic and reactive power from active filter as a function of load THD When the H and Q compensations are eliminated, the power quality of the power system undertaken is free of voltage and current pollution, and hence the source power is a pure sinusoidal waveform.

84 4.8 DC LINK VOLTAGE CONTROLLER Initially, the system is analyzed with traditional PI controller. Figure 4.6 Block diagram of PI controller Figure 4.6 shows the block diagram of PI controller. In this chapter voltage error e(t) is taken as input to PI controller and output is taken to the system. General equation of the PI controller is U (t) = Kp e (t) + K i e(t) (4.45) e (t)= SP-PV where e(t) is the error of actual measured value (PV) from the set-point (SP). K p is proportional gain; K i is the integral gain, U (t) is the controller output.

85 In this thesis Ziegler Nichols method of tuning is implemented to find the optimum value of K p & K i values (Astrom 2004). The effect of proportional term and integral term are as follows, Proportional Term: Figure 4.7 Plot of PV vs. time, for three values of K p (K i and K d held constant) The Figure 4.7 shows the proportional term which generates an output value that is proportional to the current error value. The proportional reaction can be attuned by multiplying the error by a proportional gain constant K p. The proportional term is given by: P out = K p e (t) (4.46) A high proportional gain results in a huge change in the output for a given change in the error. If the proportional gain is very high, the system

86 can become unstable. In contrast, a small gain results in a lesser output reply to a large input error and a less reactive or less sensitive controller. If the proportional gain is very low, the control action may be as well small when responding to system disturbances. Tuning theory and industrial practice specify that the proportional term should contribute the majority of the output change. Droop: Because a non zero error is required to drive the controller, a pure proportional controller generally operates with a steady state error, referred to as droop. Droop is inversely proportional to proportional gain and proportional to the process gain. Droop may be eased by adding a compensating bias term to the output or set point, or corrected by adding an integral term. Integral term: Figure 4.8 Plot of PV vs. time, for three values of K i (K p and K d held constant)

87 The Figure 4.8 shows the contribution from the integral term is proportional to both the duration of the error and the magnitude of the error. The integral in a PID controller is the sum of instantaneous error over time and provides the accumulated offset that should have been corrected before. The accumulated error is then multiplied by the integral gain K i and finally added to the output of the controller. The integral term is given by: I out K t = e(τ)dτ i 0 (4.47) The integral term accelerates the movement of the process towards set point and removes the residual steady state error that occurs with a pure proportional controller. Though, the integral term responds to accumulated errors from the earlier, it can cause the present value to overshoot the set point values which are shown in Table 4.1. Table. 4.1 Effects of increasing a parameter independently Parameter Rise Settling Steadystate error Overshoot time time Stability K p Decrease Increase Minor Decrease Degrade change K i Decrease Increase Increase Eliminate Degrade 4.9 PWM HYSTERESIS CURRENT CONTROLLER Due to the simplicity and robustness HCCPWM technique is used to produce gating pulses for the switching devices of shunt active power filter

88 which is shown in Figure.4.9. Satisfactory control of current without requiring intensive knowledge of control system parameters is obtained with this strategy hysteresis current control method is pre-eminent, as it follows more accurately the reference current of the filter. Instantaneous monitoring of actual source currents are done, which is then compared with the reference source currents shown in Figure 4.10. In each phase leg, the positive and the negative group device is switched in a complementary manner for avoiding short circuit. The current controllers are designed to operate independently for three phases. The switching signals to the inverter are determined by the current controller. The switching logic for phase A is as below. If Ica*- Ica >HB, upper switch G1 is OFF and lower switch G4 is ON. If Ica*- Ica <HB, upper switch G1 is ON and lower switch G4 is OFF The switching for phase B and C devices are derived in the same manner. The approach adopted to generate the reference current and the gating pulses determine the Figure 4.9 HCCPWM pulses for Shunt Active Power Filter Performance of the active power filter. The implementation of control strategy is done in 3 stages. The essential voltage and current signals are measured to acquire accurate system information in the first stage.

89 Figure 4.10 Simulink Model of HCCPWM In the next stage, the reference compensating current are derived and PI controller is used for DC link control and reference current generation. The gating signals for the solid state devices are generated using HCCPWM method in the third stage. 4.10 SIMULATION SETUP AND RESULTS The Figure 4.11 shows the overall arrangement of PI controller based shunt active Power filter. Simulations based on MATLAB/SIMULINK were applied to verify the proposed Shunt Active Power Filter with PI controller scheme. The circuit parameters of the equivalent power system based on Simulink model shown in Figure 4.12 are as follows: V rms =100V, V dc =300v, L s =1.0 mh, L f = 0.3mH. The power converter is switched at a frequency of 10 khz. Load current and source current were analyzed to obtain the Total Harmonic Distortion. The Figure 4.13 shows that the uncompensated source current is deviated from the actual sinusoidal current with the effect of non linear load.

90 Figure 4.11 Traditional Controller Based Shunt Active Power Filter Figure 4.12 Simulink Model of SRF Based Shunt Active Power Filter

Current in Amps 91 8 Source current before Compensation 6 4 2 0-2 -4-6 -8 0.05 0.1 0.15 0.2 0.25 0.3 Time in S Figure 4.13 Uncompensated source current Figure 4.12 shows the model of SRF based SAPF with the nonlinear load. In this model nonlinear load is variable. Three phase breaker controls the ON/OFF of SAPF in the power system. Figure 4.13 shows the status of source current in the OFF state of SAPF using three phase breaker. In this analysis to show the performance of shunt active power filter system. It is activated at the time of 0.2 Sec. The compensation current produced after 0.2 Sec is shown in Figure 4.14, It is injected in to the point of common coupling (PCC). From the Figure 4.14 it is clear that compensation current is produced with respect to load current. The effect of compensation current in a source current is shown in Figure 4.15 which shows the compensated source current.

Source Current in Amps Icc Icb Ica 92 4 2 SAPF is ON at 0.2 S COMPENSATED CURRENT FOR PHASE A 0-2 -4 4 0.2 0.25 0.3 0.35 0.4 0.45 0.5 COMPENSATED CURRENT FOR PHASE B 2 0-2 -4 4 0.2 0.25 0.3 0.35 0.4 0.45 0.5 COMPENSATED CURRENT FOR PHASE C 2 0-2 -4 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Time in 'S' Figure 4.14 Compensation Current 8 SAPF is ON at 0.2 S Source Current after Compensation 6 4 2 0-2 -4-6 -8 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Time in S Figure 4.15 Source current after compensation

Voltage in Volts 93 The DC link capacitor voltage before and after the activation of SAPF system is shown in Figure 4.16. 316 DC LINK VOLTAGE 314 312 310 SAPF is ON at 0.2 S 308 306 304 302 300 298 0.2 0.4 0.6 0.8 1 1.2 1.4 Time in S Figure 4.16 DC link voltage control with PI control scheme From the Figure 4.15 it is noted that the source current become pure sine wave after the activation SAPF. DC link voltage with respect to activation of filter is obvious from the Figure 4.16. The Figure 4.17 shows the performance of SRF based shunt active power filter in terms of phase angle. The SAPF System makes the compensated source current to in phase with source voltage

Source Voltage & Current 94 100 Source Voltage & Current after Compensation SAPF is ON at 0.2 S 80 60 40 20 0-20 -40-60 -80-100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Time in S Figure 4.17 Source current and voltage after compensation From the Figure 4.17 it is noted that the SAPF System makes the compensated source current to in phase with source voltage. Figure 4.18 shows the Total harmonic distortion of the compensated source current. Figure4.18 Overall THD

95 From the Figure 4.14 to 4.17 it is noted that after the activation of SAPF (0.2 sec), VSC is activated to deliver the compensation current with capacitor voltage as a source. Figure 4.15 shows that after 0.2 sec, the shape of current is improved which improve the power factor as shown Figure 4.17 and reduce harmonics as shown in the Figure 4.18. 4.11 SUMMARY The traditional controller based Shunt Active Power Filter is able to efficiently compensate reactive power and suppress harmonic distorted loads. The Shunt Active power filter with digital filter based SRF algorithm was observed in this chapter. From the analysis, simulation, it is seen that the algorithm presented in this chapter has some advantages namely; 1) clear physical meaning, 2) rapid operation. The result shows that butter worth filter based SRF algorithm meets the recommended harmonic standards such as IEEE 519, where the one with the PI scheme attained the best performance in terms of Active Filtering. But the PI controller is slow in adapting to load changes and also a PI controller does not have the ability to evaluate the performance of the controller in the system. Since PI controller deals with the present error alone. It cannot reduce the rise time and eliminate steady state error. It has poor transient response. The integral action increases the oscillations in the output of the system. Hence the THD is increased and also the capacitor gets stressed during load changing.